fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / drivers / scsi / qla2xxx / qla_dbg.h
bloba50ecf0b7c8452b144b1459d247897a9bfef6b4f
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 /*
8 * Driver debug definitions.
9 */
10 /* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */
11 /* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */
12 /* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */
13 /* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */
14 /* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */
15 /* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */
16 /* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */
17 /* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */
18 /* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */
19 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
20 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
21 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
22 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
23 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
24 /* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
26 * Local Macro Definitions.
28 #if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \
29 defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \
30 defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \
31 defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8) || \
32 defined(QL_DEBUG_LEVEL_9) || defined(QL_DEBUG_LEVEL_10) || \
33 defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \
34 defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14) || \
35 defined(QL_DEBUG_LEVEL_15)
36 #define QL_DEBUG_ROUTINES
37 #endif
40 * Macros use for debugging the driver.
43 #define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0)
45 #if defined(QL_DEBUG_LEVEL_1)
46 #define DEBUG1(x) do {x;} while (0)
47 #else
48 #define DEBUG1(x) do {} while (0)
49 #endif
51 #define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0)
52 #define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0)
53 #define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
54 #define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0)
55 #define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
56 #define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0)
58 #if defined(QL_DEBUG_LEVEL_3)
59 #define DEBUG3(x) do {x;} while (0)
60 #define DEBUG3_11(x) do {x;} while (0)
61 #else
62 #define DEBUG3(x) do {} while (0)
63 #endif
65 #if defined(QL_DEBUG_LEVEL_4)
66 #define DEBUG4(x) do {x;} while (0)
67 #else
68 #define DEBUG4(x) do {} while (0)
69 #endif
71 #if defined(QL_DEBUG_LEVEL_5)
72 #define DEBUG5(x) do {x;} while (0)
73 #else
74 #define DEBUG5(x) do {} while (0)
75 #endif
77 #if defined(QL_DEBUG_LEVEL_7)
78 #define DEBUG7(x) do {x;} while (0)
79 #else
80 #define DEBUG7(x) do {} while (0)
81 #endif
83 #if defined(QL_DEBUG_LEVEL_9)
84 #define DEBUG9(x) do {x;} while (0)
85 #define DEBUG9_10(x) do {x;} while (0)
86 #else
87 #define DEBUG9(x) do {} while (0)
88 #endif
90 #if defined(QL_DEBUG_LEVEL_10)
91 #define DEBUG10(x) do {x;} while (0)
92 #define DEBUG9_10(x) do {x;} while (0)
93 #else
94 #define DEBUG10(x) do {} while (0)
95 #if !defined(DEBUG9_10)
96 #define DEBUG9_10(x) do {} while (0)
97 #endif
98 #endif
100 #if defined(QL_DEBUG_LEVEL_11)
101 #define DEBUG11(x) do{x;} while(0)
102 #if !defined(DEBUG3_11)
103 #define DEBUG3_11(x) do{x;} while(0)
104 #endif
105 #else
106 #define DEBUG11(x) do{} while(0)
107 #if !defined(QL_DEBUG_LEVEL_3)
108 #define DEBUG3_11(x) do{} while(0)
109 #endif
110 #endif
112 #if defined(QL_DEBUG_LEVEL_12)
113 #define DEBUG12(x) do {x;} while (0)
114 #else
115 #define DEBUG12(x) do {} while (0)
116 #endif
118 #if defined(QL_DEBUG_LEVEL_13)
119 #define DEBUG13(x) do {x;} while (0)
120 #else
121 #define DEBUG13(x) do {} while (0)
122 #endif
124 #if defined(QL_DEBUG_LEVEL_14)
125 #define DEBUG14(x) do {x;} while (0)
126 #else
127 #define DEBUG14(x) do {} while (0)
128 #endif
130 #if defined(QL_DEBUG_LEVEL_15)
131 #define DEBUG15(x) do {x;} while (0)
132 #else
133 #define DEBUG15(x) do {} while (0)
134 #endif
137 * Firmware Dump structure definition
140 struct qla2300_fw_dump {
141 uint16_t hccr;
142 uint16_t pbiu_reg[8];
143 uint16_t risc_host_reg[8];
144 uint16_t mailbox_reg[32];
145 uint16_t resp_dma_reg[32];
146 uint16_t dma_reg[48];
147 uint16_t risc_hdw_reg[16];
148 uint16_t risc_gp0_reg[16];
149 uint16_t risc_gp1_reg[16];
150 uint16_t risc_gp2_reg[16];
151 uint16_t risc_gp3_reg[16];
152 uint16_t risc_gp4_reg[16];
153 uint16_t risc_gp5_reg[16];
154 uint16_t risc_gp6_reg[16];
155 uint16_t risc_gp7_reg[16];
156 uint16_t frame_buf_hdw_reg[64];
157 uint16_t fpm_b0_reg[64];
158 uint16_t fpm_b1_reg[64];
159 uint16_t risc_ram[0xf800];
160 uint16_t stack_ram[0x1000];
161 uint16_t data_ram[1];
164 struct qla2100_fw_dump {
165 uint16_t hccr;
166 uint16_t pbiu_reg[8];
167 uint16_t mailbox_reg[32];
168 uint16_t dma_reg[48];
169 uint16_t risc_hdw_reg[16];
170 uint16_t risc_gp0_reg[16];
171 uint16_t risc_gp1_reg[16];
172 uint16_t risc_gp2_reg[16];
173 uint16_t risc_gp3_reg[16];
174 uint16_t risc_gp4_reg[16];
175 uint16_t risc_gp5_reg[16];
176 uint16_t risc_gp6_reg[16];
177 uint16_t risc_gp7_reg[16];
178 uint16_t frame_buf_hdw_reg[16];
179 uint16_t fpm_b0_reg[64];
180 uint16_t fpm_b1_reg[64];
181 uint16_t risc_ram[0xf000];
184 struct qla24xx_fw_dump {
185 uint32_t host_status;
186 uint32_t host_reg[32];
187 uint32_t shadow_reg[7];
188 uint16_t mailbox_reg[32];
189 uint32_t xseq_gp_reg[128];
190 uint32_t xseq_0_reg[16];
191 uint32_t xseq_1_reg[16];
192 uint32_t rseq_gp_reg[128];
193 uint32_t rseq_0_reg[16];
194 uint32_t rseq_1_reg[16];
195 uint32_t rseq_2_reg[16];
196 uint32_t cmd_dma_reg[16];
197 uint32_t req0_dma_reg[15];
198 uint32_t resp0_dma_reg[15];
199 uint32_t req1_dma_reg[15];
200 uint32_t xmt0_dma_reg[32];
201 uint32_t xmt1_dma_reg[32];
202 uint32_t xmt2_dma_reg[32];
203 uint32_t xmt3_dma_reg[32];
204 uint32_t xmt4_dma_reg[32];
205 uint32_t xmt_data_dma_reg[16];
206 uint32_t rcvt0_data_dma_reg[32];
207 uint32_t rcvt1_data_dma_reg[32];
208 uint32_t risc_gp_reg[128];
209 uint32_t lmc_reg[112];
210 uint32_t fpm_hdw_reg[192];
211 uint32_t fb_hdw_reg[176];
212 uint32_t code_ram[0x2000];
213 uint32_t ext_mem[1];
216 struct qla25xx_fw_dump {
217 uint32_t host_status;
218 uint32_t host_risc_reg[32];
219 uint32_t pcie_regs[4];
220 uint32_t host_reg[32];
221 uint32_t shadow_reg[11];
222 uint32_t risc_io_reg;
223 uint16_t mailbox_reg[32];
224 uint32_t xseq_gp_reg[128];
225 uint32_t xseq_0_reg[48];
226 uint32_t xseq_1_reg[16];
227 uint32_t rseq_gp_reg[128];
228 uint32_t rseq_0_reg[32];
229 uint32_t rseq_1_reg[16];
230 uint32_t rseq_2_reg[16];
231 uint32_t aseq_gp_reg[128];
232 uint32_t aseq_0_reg[32];
233 uint32_t aseq_1_reg[16];
234 uint32_t aseq_2_reg[16];
235 uint32_t cmd_dma_reg[16];
236 uint32_t req0_dma_reg[15];
237 uint32_t resp0_dma_reg[15];
238 uint32_t req1_dma_reg[15];
239 uint32_t xmt0_dma_reg[32];
240 uint32_t xmt1_dma_reg[32];
241 uint32_t xmt2_dma_reg[32];
242 uint32_t xmt3_dma_reg[32];
243 uint32_t xmt4_dma_reg[32];
244 uint32_t xmt_data_dma_reg[16];
245 uint32_t rcvt0_data_dma_reg[32];
246 uint32_t rcvt1_data_dma_reg[32];
247 uint32_t risc_gp_reg[128];
248 uint32_t lmc_reg[128];
249 uint32_t fpm_hdw_reg[192];
250 uint32_t fb_hdw_reg[192];
251 uint32_t code_ram[0x2000];
252 uint32_t ext_mem[1];
255 #define EFT_NUM_BUFFERS 4
256 #define EFT_BYTES_PER_BUFFER 0x4000
257 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
259 struct qla2xxx_fw_dump {
260 uint8_t signature[4];
261 uint32_t version;
263 uint32_t fw_major_version;
264 uint32_t fw_minor_version;
265 uint32_t fw_subminor_version;
266 uint32_t fw_attributes;
268 uint32_t vendor;
269 uint32_t device;
270 uint32_t subsystem_vendor;
271 uint32_t subsystem_device;
273 uint32_t fixed_size;
274 uint32_t mem_size;
275 uint32_t req_q_size;
276 uint32_t rsp_q_size;
278 uint32_t eft_size;
279 uint32_t eft_addr_l;
280 uint32_t eft_addr_h;
282 uint32_t header_size;
284 union {
285 struct qla2100_fw_dump isp21;
286 struct qla2300_fw_dump isp23;
287 struct qla24xx_fw_dump isp24;
288 struct qla25xx_fw_dump isp25;
289 } isp;