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fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / drivers / usb / gadget / omap_udc.c
blob87c4f50dfb61b6af50d929efa52cd10ce9db9dc2
1 /*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #undef DEBUG
23 #undef VERBOSE
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/ioport.h>
28 #include <linux/types.h>
29 #include <linux/errno.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/interrupt.h>
36 #include <linux/proc_fs.h>
37 #include <linux/mm.h>
38 #include <linux/moduleparam.h>
39 #include <linux/platform_device.h>
40 #include <linux/usb/ch9.h>
41 #include <linux/usb/gadget.h>
42 #include <linux/usb/otg.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/clk.h>
45
46 #include <asm/byteorder.h>
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/system.h>
50 #include <asm/unaligned.h>
51 #include <asm/mach-types.h>
52
53 #include <asm/arch/dma.h>
54 #include <asm/arch/usb.h>
55
56 #include "omap_udc.h"
57
58 #undef USB_TRACE
59
60 /* bulk DMA seems to be behaving for both IN and OUT */
61 #define USE_DMA
62
63 /* FIXME: OMAP2 currently has some problem in DMA mode */
64 #ifdef CONFIG_ARCH_OMAP2
65 #undef USE_DMA
66 #endif
67
68 /* ISO too */
69 #define USE_ISO
70
71 #define DRIVER_DESC "OMAP UDC driver"
72 #define DRIVER_VERSION "4 October 2004"
73
74 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
75
76
77 /*
78 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
79 * D+ pullup to allow enumeration. That's too early for the gadget
80 * framework to use from usb_endpoint_enable(), which happens after
81 * enumeration as part of activating an interface. (But if we add an
82 * optional new "UDC not yet running" state to the gadget driver model,
83 * even just during driver binding, the endpoint autoconfig logic is the
84 * natural spot to manufacture new endpoints.)
85 *
86 * So instead of using endpoint enable calls to control the hardware setup,
87 * this driver defines a "fifo mode" parameter. It's used during driver
88 * initialization to choose among a set of pre-defined endpoint configs.
89 * See omap_udc_setup() for available modes, or to add others. That code
90 * lives in an init section, so use this driver as a module if you need
91 * to change the fifo mode after the kernel boots.
92 *
93 * Gadget drivers normally ignore endpoints they don't care about, and
94 * won't include them in configuration descriptors. That means only
95 * misbehaving hosts would even notice they exist.
96 */
97 #ifdef USE_ISO
98 static unsigned fifo_mode = 3;
99 #else
100 static unsigned fifo_mode = 0;
101 #endif
102
103 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
104 * boot parameter "omap_udc:fifo_mode=42"
105 */
106 module_param (fifo_mode, uint, 0);
107 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
108
109 #ifdef USE_DMA
110 static unsigned use_dma = 1;
111
112 /* "modprobe omap_udc use_dma=y", or else as a kernel
113 * boot parameter "omap_udc:use_dma=y"
114 */
115 module_param (use_dma, bool, 0);
116 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
117 #else /* !USE_DMA */
118
119 /* save a bit of code */
120 #define use_dma 0
121 #endif /* !USE_DMA */
122
123
124 static const char driver_name [] = "omap_udc";
125 static const char driver_desc [] = DRIVER_DESC;
126
127 /*-------------------------------------------------------------------------*/
128
129 /* there's a notion of "current endpoint" for modifying endpoint
130 * state, and PIO access to its FIFO.
131 */
132
133 static void use_ep(struct omap_ep *ep, u16 select)
134 {
135 u16 num = ep->bEndpointAddress & 0x0f;
136
137 if (ep->bEndpointAddress & USB_DIR_IN)
138 num |= UDC_EP_DIR;
139 UDC_EP_NUM_REG = num | select;
140 /* when select, MUST deselect later !! */
141 }
142
143 static inline void deselect_ep(void)
144 {
145 UDC_EP_NUM_REG &= ~UDC_EP_SEL;
146 /* 6 wait states before TX will happen */
147 }
148
149 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
150
151 /*-------------------------------------------------------------------------*/
152
153 static int omap_ep_enable(struct usb_ep *_ep,
154 const struct usb_endpoint_descriptor *desc)
155 {
156 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
157 struct omap_udc *udc;
158 unsigned long flags;
159 u16 maxp;
160
161 /* catch various bogus parameters */
162 if (!_ep || !desc || ep->desc
163 || desc->bDescriptorType != USB_DT_ENDPOINT
164 || ep->bEndpointAddress != desc->bEndpointAddress
165 || ep->maxpacket < le16_to_cpu
166 (desc->wMaxPacketSize)) {
167 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
168 return -EINVAL;
169 }
170 maxp = le16_to_cpu (desc->wMaxPacketSize);
171 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
172 && maxp != ep->maxpacket)
173 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
174 || !desc->wMaxPacketSize) {
175 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
176 return -ERANGE;
177 }
178
179 #ifdef USE_ISO
180 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
181 && desc->bInterval != 1)) {
182 /* hardware wants period = 1; USB allows 2^(Interval-1) */
183 DBG("%s, unsupported ISO period %dms\n", _ep->name,
184 1 << (desc->bInterval - 1));
185 return -EDOM;
186 }
187 #else
188 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
189 DBG("%s, ISO nyet\n", _ep->name);
190 return -EDOM;
191 }
192 #endif
193
194 /* xfer types must match, except that interrupt ~= bulk */
195 if (ep->bmAttributes != desc->bmAttributes
196 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
197 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
198 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
199 return -EINVAL;
200 }
201
202 udc = ep->udc;
203 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
204 DBG("%s, bogus device state\n", __FUNCTION__);
205 return -ESHUTDOWN;
206 }
207
208 spin_lock_irqsave(&udc->lock, flags);
209
210 ep->desc = desc;
211 ep->irqs = 0;
212 ep->stopped = 0;
213 ep->ep.maxpacket = maxp;
214
215 /* set endpoint to initial state */
216 ep->dma_channel = 0;
217 ep->has_dma = 0;
218 ep->lch = -1;
219 use_ep(ep, UDC_EP_SEL);
220 UDC_CTRL_REG = udc->clr_halt;
221 ep->ackwait = 0;
222 deselect_ep();
223
224 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
225 list_add(&ep->iso, &udc->iso);
226
227 /* maybe assign a DMA channel to this endpoint */
228 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
229 /* FIXME ISO can dma, but prefers first channel */
230 dma_channel_claim(ep, 0);
231
232 /* PIO OUT may RX packets */
233 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
234 && !ep->has_dma
235 && !(ep->bEndpointAddress & USB_DIR_IN)) {
236 UDC_CTRL_REG = UDC_SET_FIFO_EN;
237 ep->ackwait = 1 + ep->double_buf;
238 }
239
240 spin_unlock_irqrestore(&udc->lock, flags);
241 VDBG("%s enabled\n", _ep->name);
242 return 0;
243 }
244
245 static void nuke(struct omap_ep *, int status);
246
247 static int omap_ep_disable(struct usb_ep *_ep)
248 {
249 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
250 unsigned long flags;
251
252 if (!_ep || !ep->desc) {
253 DBG("%s, %s not enabled\n", __FUNCTION__,
254 _ep ? ep->ep.name : NULL);
255 return -EINVAL;
256 }
257
258 spin_lock_irqsave(&ep->udc->lock, flags);
259 ep->desc = NULL;
260 nuke (ep, -ESHUTDOWN);
261 ep->ep.maxpacket = ep->maxpacket;
262 ep->has_dma = 0;
263 UDC_CTRL_REG = UDC_SET_HALT;
264 list_del_init(&ep->iso);
265 del_timer(&ep->timer);
266
267 spin_unlock_irqrestore(&ep->udc->lock, flags);
268
269 VDBG("%s disabled\n", _ep->name);
270 return 0;
271 }
272
273 /*-------------------------------------------------------------------------*/
274
275 static struct usb_request *
276 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
277 {
278 struct omap_req *req;
279
280 req = kzalloc(sizeof(*req), gfp_flags);
281 if (req) {
282 req->req.dma = DMA_ADDR_INVALID;
283 INIT_LIST_HEAD (&req->queue);
284 }
285 return &req->req;
286 }
287
288 static void
289 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
290 {
291 struct omap_req *req = container_of(_req, struct omap_req, req);
292
293 if (_req)
294 kfree (req);
295 }
296
297 /*-------------------------------------------------------------------------*/
298
299 static void
300 done(struct omap_ep *ep, struct omap_req *req, int status)
301 {
302 unsigned stopped = ep->stopped;
303
304 list_del_init(&req->queue);
305
306 if (req->req.status == -EINPROGRESS)
307 req->req.status = status;
308 else
309 status = req->req.status;
310
311 if (use_dma && ep->has_dma) {
312 if (req->mapped) {
313 dma_unmap_single(ep->udc->gadget.dev.parent,
314 req->req.dma, req->req.length,
315 (ep->bEndpointAddress & USB_DIR_IN)
316 ? DMA_TO_DEVICE
317 : DMA_FROM_DEVICE);
318 req->req.dma = DMA_ADDR_INVALID;
319 req->mapped = 0;
320 } else
321 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
322 req->req.dma, req->req.length,
323 (ep->bEndpointAddress & USB_DIR_IN)
324 ? DMA_TO_DEVICE
325 : DMA_FROM_DEVICE);
326 }
327
328 #ifndef USB_TRACE
329 if (status && status != -ESHUTDOWN)
330 #endif
331 VDBG("complete %s req %p stat %d len %u/%u\n",
332 ep->ep.name, &req->req, status,
333 req->req.actual, req->req.length);
334
335 /* don't modify queue heads during completion callback */
336 ep->stopped = 1;
337 spin_unlock(&ep->udc->lock);
338 req->req.complete(&ep->ep, &req->req);
339 spin_lock(&ep->udc->lock);
340 ep->stopped = stopped;
341 }
342
343 /*-------------------------------------------------------------------------*/
344
345 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
346 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
347
348 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
349 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
350
351 static inline int
352 write_packet(u8 *buf, struct omap_req *req, unsigned max)
353 {
354 unsigned len;
355 u16 *wp;
356
357 len = min(req->req.length - req->req.actual, max);
358 req->req.actual += len;
359
360 max = len;
361 if (likely((((int)buf) & 1) == 0)) {
362 wp = (u16 *)buf;
363 while (max >= 2) {
364 UDC_DATA_REG = *wp++;
365 max -= 2;
366 }
367 buf = (u8 *)wp;
368 }
369 while (max--)
370 *(volatile u8 *)&UDC_DATA_REG = *buf++;
371 return len;
372 }
373
374 // FIXME change r/w fifo calling convention
375
376
377 // return: 0 = still running, 1 = completed, negative = errno
378 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
379 {
380 u8 *buf;
381 unsigned count;
382 int is_last;
383 u16 ep_stat;
384
385 buf = req->req.buf + req->req.actual;
386 prefetch(buf);
387
388 /* PIO-IN isn't double buffered except for iso */
389 ep_stat = UDC_STAT_FLG_REG;
390 if (ep_stat & UDC_FIFO_UNWRITABLE)
391 return 0;
392
393 count = ep->ep.maxpacket;
394 count = write_packet(buf, req, count);
395 UDC_CTRL_REG = UDC_SET_FIFO_EN;
396 ep->ackwait = 1;
397
398 /* last packet is often short (sometimes a zlp) */
399 if (count != ep->ep.maxpacket)
400 is_last = 1;
401 else if (req->req.length == req->req.actual
402 && !req->req.zero)
403 is_last = 1;
404 else
405 is_last = 0;
406
407 /* NOTE: requests complete when all IN data is in a
408 * FIFO (or sometimes later, if a zlp was needed).
409 * Use usb_ep_fifo_status() where needed.
410 */
411 if (is_last)
412 done(ep, req, 0);
413 return is_last;
414 }
415
416 static inline int
417 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
418 {
419 unsigned len;
420 u16 *wp;
421
422 len = min(req->req.length - req->req.actual, avail);
423 req->req.actual += len;
424 avail = len;
425
426 if (likely((((int)buf) & 1) == 0)) {
427 wp = (u16 *)buf;
428 while (avail >= 2) {
429 *wp++ = UDC_DATA_REG;
430 avail -= 2;
431 }
432 buf = (u8 *)wp;
433 }
434 while (avail--)
435 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
436 return len;
437 }
438
439 // return: 0 = still running, 1 = queue empty, negative = errno
440 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
441 {
442 u8 *buf;
443 unsigned count, avail;
444 int is_last;
445
446 buf = req->req.buf + req->req.actual;
447 prefetchw(buf);
448
449 for (;;) {
450 u16 ep_stat = UDC_STAT_FLG_REG;
451
452 is_last = 0;
453 if (ep_stat & FIFO_EMPTY) {
454 if (!ep->double_buf)
455 break;
456 ep->fnf = 1;
457 }
458 if (ep_stat & UDC_EP_HALTED)
459 break;
460
461 if (ep_stat & UDC_FIFO_FULL)
462 avail = ep->ep.maxpacket;
463 else {
464 avail = UDC_RXFSTAT_REG;
465 ep->fnf = ep->double_buf;
466 }
467 count = read_packet(buf, req, avail);
468
469 /* partial packet reads may not be errors */
470 if (count < ep->ep.maxpacket) {
471 is_last = 1;
472 /* overflowed this request? flush extra data */
473 if (count != avail) {
474 req->req.status = -EOVERFLOW;
475 avail -= count;
476 while (avail--)
477 (void) *(volatile u8 *)&UDC_DATA_REG;
478 }
479 } else if (req->req.length == req->req.actual)
480 is_last = 1;
481 else
482 is_last = 0;
483
484 if (!ep->bEndpointAddress)
485 break;
486 if (is_last)
487 done(ep, req, 0);
488 break;
489 }
490 return is_last;
491 }
492
493 /*-------------------------------------------------------------------------*/
494
495 static inline dma_addr_t dma_csac(unsigned lch)
496 {
497 dma_addr_t csac;
498
499 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
500 * read before the DMA controller finished disabling the channel.
501 */
502 csac = OMAP_DMA_CSAC_REG(lch);
503 if (csac == 0)
504 csac = OMAP_DMA_CSAC_REG(lch);
505 return csac;
506 }
507
508 static inline dma_addr_t dma_cdac(unsigned lch)
509 {
510 dma_addr_t cdac;
511
512 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
513 * read before the DMA controller finished disabling the channel.
514 */
515 cdac = OMAP_DMA_CDAC_REG(lch);
516 if (cdac == 0)
517 cdac = OMAP_DMA_CDAC_REG(lch);
518 return cdac;
519 }
520
521 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
522 {
523 dma_addr_t end;
524
525 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
526 * the last transfer's bytecount by more than a FIFO's worth.
527 */
528 if (cpu_is_omap15xx())
529 return 0;
530
531 end = dma_csac(ep->lch);
532 if (end == ep->dma_counter)
533 return 0;
534
535 end |= start & (0xffff << 16);
536 if (end < start)
537 end += 0x10000;
538 return end - start;
539 }
540
541 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
542 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
543 : dma_cdac(x))
544
545 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
546 {
547 dma_addr_t end;
548
549 end = DMA_DEST_LAST(ep->lch);
550 if (end == ep->dma_counter)
551 return 0;
552
553 end |= start & (0xffff << 16);
554 if (cpu_is_omap15xx())
555 end++;
556 if (end < start)
557 end += 0x10000;
558 return end - start;
559 }
560
561
562 /* Each USB transfer request using DMA maps to one or more DMA transfers.
563 * When DMA completion isn't request completion, the UDC continues with
564 * the next DMA transfer for that USB transfer.
565 */
566
567 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
568 {
569 u16 txdma_ctrl;
570 unsigned length = req->req.length - req->req.actual;
571 const int sync_mode = cpu_is_omap15xx()
572 ? OMAP_DMA_SYNC_FRAME
573 : OMAP_DMA_SYNC_ELEMENT;
574
575 /* measure length in either bytes or packets */
576 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
577 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
578 txdma_ctrl = UDC_TXN_EOT | length;
579 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
580 length, 1, sync_mode, 0, 0);
581 } else {
582 length = min(length / ep->maxpacket,
583 (unsigned) UDC_TXN_TSC + 1);
584 txdma_ctrl = length;
585 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
586 ep->ep.maxpacket >> 1, length, sync_mode,
587 0, 0);
588 length *= ep->maxpacket;
589 }
590 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
591 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
592 0, 0);
593
594 omap_start_dma(ep->lch);
595 ep->dma_counter = dma_csac(ep->lch);
596 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
597 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
598 req->dma_bytes = length;
599 }
600
601 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
602 {
603 if (status == 0) {
604 req->req.actual += req->dma_bytes;
605
606 /* return if this request needs to send data or zlp */
607 if (req->req.actual < req->req.length)
608 return;
609 if (req->req.zero
610 && req->dma_bytes != 0
611 && (req->req.actual % ep->maxpacket) == 0)
612 return;
613 } else
614 req->req.actual += dma_src_len(ep, req->req.dma
615 + req->req.actual);
616
617 /* tx completion */
618 omap_stop_dma(ep->lch);
619 UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
620 done(ep, req, status);
621 }
622
623 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
624 {
625 unsigned packets;
626
627 /* NOTE: we filtered out "short reads" before, so we know
628 * the buffer has only whole numbers of packets.
629 */
630
631 /* set up this DMA transfer, enable the fifo, start */
632 packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
633 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
634 req->dma_bytes = packets * ep->ep.maxpacket;
635 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
636 ep->ep.maxpacket >> 1, packets,
637 OMAP_DMA_SYNC_ELEMENT,
638 0, 0);
639 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
640 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
641 0, 0);
642 ep->dma_counter = DMA_DEST_LAST(ep->lch);
643
644 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
645 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
646 UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
647 UDC_CTRL_REG = UDC_SET_FIFO_EN;
648
649 omap_start_dma(ep->lch);
650 }
651
652 static void
653 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
654 {
655 u16 count;
656
657 if (status == 0)
658 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
659 count = dma_dest_len(ep, req->req.dma + req->req.actual);
660 count += req->req.actual;
661 if (one)
662 count--;
663 if (count <= req->req.length)
664 req->req.actual = count;
665
666 if (count != req->dma_bytes || status)
667 omap_stop_dma(ep->lch);
668
669 /* if this wasn't short, request may need another transfer */
670 else if (req->req.actual < req->req.length)
671 return;
672
673 /* rx completion */
674 UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
675 done(ep, req, status);
676 }
677
678 static void dma_irq(struct omap_udc *udc, u16 irq_src)
679 {
680 u16 dman_stat = UDC_DMAN_STAT_REG;
681 struct omap_ep *ep;
682 struct omap_req *req;
683
684 /* IN dma: tx to host */
685 if (irq_src & UDC_TXN_DONE) {
686 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
687 ep->irqs++;
688 /* can see TXN_DONE after dma abort */
689 if (!list_empty(&ep->queue)) {
690 req = container_of(ep->queue.next,
691 struct omap_req, queue);
692 finish_in_dma(ep, req, 0);
693 }
694 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
695
696 if (!list_empty (&ep->queue)) {
697 req = container_of(ep->queue.next,
698 struct omap_req, queue);
699 next_in_dma(ep, req);
700 }
701 }
702
703 /* OUT dma: rx from host */
704 if (irq_src & UDC_RXN_EOT) {
705 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
706 ep->irqs++;
707 /* can see RXN_EOT after dma abort */
708 if (!list_empty(&ep->queue)) {
709 req = container_of(ep->queue.next,
710 struct omap_req, queue);
711 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
712 }
713 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
714
715 if (!list_empty (&ep->queue)) {
716 req = container_of(ep->queue.next,
717 struct omap_req, queue);
718 next_out_dma(ep, req);
719 }
720 }
721
722 if (irq_src & UDC_RXN_CNT) {
723 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
724 ep->irqs++;
725 /* omap15xx does this unasked... */
726 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
727 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
728 }
729 }
730
731 static void dma_error(int lch, u16 ch_status, void *data)
732 {
733 struct omap_ep *ep = data;
734
735 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
736 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
737 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
738
739 /* complete current transfer ... */
740 }
741
742 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
743 {
744 u16 reg;
745 int status, restart, is_in;
746
747 is_in = ep->bEndpointAddress & USB_DIR_IN;
748 if (is_in)
749 reg = UDC_TXDMA_CFG_REG;
750 else
751 reg = UDC_RXDMA_CFG_REG;
752 reg |= UDC_DMA_REQ; /* "pulse" activated */
753
754 ep->dma_channel = 0;
755 ep->lch = -1;
756 if (channel == 0 || channel > 3) {
757 if ((reg & 0x0f00) == 0)
758 channel = 3;
759 else if ((reg & 0x00f0) == 0)
760 channel = 2;
761 else if ((reg & 0x000f) == 0) /* preferred for ISO */
762 channel = 1;
763 else {
764 status = -EMLINK;
765 goto just_restart;
766 }
767 }
768 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
769 ep->dma_channel = channel;
770
771 if (is_in) {
772 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
773 ep->ep.name, dma_error, ep, &ep->lch);
774 if (status == 0) {
775 UDC_TXDMA_CFG_REG = reg;
776 /* EMIFF */
777 omap_set_dma_src_burst_mode(ep->lch,
778 OMAP_DMA_DATA_BURST_4);
779 omap_set_dma_src_data_pack(ep->lch, 1);
780 /* TIPB */
781 omap_set_dma_dest_params(ep->lch,
782 OMAP_DMA_PORT_TIPB,
783 OMAP_DMA_AMODE_CONSTANT,
784 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
785 0, 0);
786 }
787 } else {
788 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
789 ep->ep.name, dma_error, ep, &ep->lch);
790 if (status == 0) {
791 UDC_RXDMA_CFG_REG = reg;
792 /* TIPB */
793 omap_set_dma_src_params(ep->lch,
794 OMAP_DMA_PORT_TIPB,
795 OMAP_DMA_AMODE_CONSTANT,
796 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
797 0, 0);
798 /* EMIFF */
799 omap_set_dma_dest_burst_mode(ep->lch,
800 OMAP_DMA_DATA_BURST_4);
801 omap_set_dma_dest_data_pack(ep->lch, 1);
802 }
803 }
804 if (status)
805 ep->dma_channel = 0;
806 else {
807 ep->has_dma = 1;
808 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
809
810 /* channel type P: hw synch (fifo) */
811 if (!cpu_is_omap15xx())
812 OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
813 }
814
815 just_restart:
816 /* restart any queue, even if the claim failed */
817 restart = !ep->stopped && !list_empty(&ep->queue);
818
819 if (status)
820 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
821 restart ? " (restart)" : "");
822 else
823 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
824 is_in ? 't' : 'r',
825 ep->dma_channel - 1, ep->lch,
826 restart ? " (restart)" : "");
827
828 if (restart) {
829 struct omap_req *req;
830 req = container_of(ep->queue.next, struct omap_req, queue);
831 if (ep->has_dma)
832 (is_in ? next_in_dma : next_out_dma)(ep, req);
833 else {
834 use_ep(ep, UDC_EP_SEL);
835 (is_in ? write_fifo : read_fifo)(ep, req);
836 deselect_ep();
837 if (!is_in) {
838 UDC_CTRL_REG = UDC_SET_FIFO_EN;
839 ep->ackwait = 1 + ep->double_buf;
840 }
841 /* IN: 6 wait states before it'll tx */
842 }
843 }
844 }
845
846 static void dma_channel_release(struct omap_ep *ep)
847 {
848 int shift = 4 * (ep->dma_channel - 1);
849 u16 mask = 0x0f << shift;
850 struct omap_req *req;
851 int active;
852
853 /* abort any active usb transfer request */
854 if (!list_empty(&ep->queue))
855 req = container_of(ep->queue.next, struct omap_req, queue);
856 else
857 req = NULL;
858
859 active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
860
861 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
862 active ? "active" : "idle",
863 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
864 ep->dma_channel - 1, req);
865
866 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
867 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
868 */
869
870 /* wait till current packet DMA finishes, and fifo empties */
871 if (ep->bEndpointAddress & USB_DIR_IN) {
872 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
873
874 if (req) {
875 finish_in_dma(ep, req, -ECONNRESET);
876
877 /* clear FIFO; hosts probably won't empty it */
878 use_ep(ep, UDC_EP_SEL);
879 UDC_CTRL_REG = UDC_CLR_EP;
880 deselect_ep();
881 }
882 while (UDC_TXDMA_CFG_REG & mask)
883 udelay(10);
884 } else {
885 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
886
887 /* dma empties the fifo */
888 while (UDC_RXDMA_CFG_REG & mask)
889 udelay(10);
890 if (req)
891 finish_out_dma(ep, req, -ECONNRESET, 0);
892 }
893 omap_free_dma(ep->lch);
894 ep->dma_channel = 0;
895 ep->lch = -1;
896 /* has_dma still set, till endpoint is fully quiesced */
897 }
898
899
900 /*-------------------------------------------------------------------------*/
901
902 static int
903 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
904 {
905 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
906 struct omap_req *req = container_of(_req, struct omap_req, req);
907 struct omap_udc *udc;
908 unsigned long flags;
909 int is_iso = 0;
910
911 /* catch various bogus parameters */
912 if (!_req || !req->req.complete || !req->req.buf
913 || !list_empty(&req->queue)) {
914 DBG("%s, bad params\n", __FUNCTION__);
915 return -EINVAL;
916 }
917 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
918 DBG("%s, bad ep\n", __FUNCTION__);
919 return -EINVAL;
920 }
921 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
922 if (req->req.length > ep->ep.maxpacket)
923 return -EMSGSIZE;
924 is_iso = 1;
925 }
926
927 /* this isn't bogus, but OMAP DMA isn't the only hardware to
928 * have a hard time with partial packet reads... reject it.
929 */
930 if (use_dma
931 && ep->has_dma
932 && ep->bEndpointAddress != 0
933 && (ep->bEndpointAddress & USB_DIR_IN) == 0
934 && (req->req.length % ep->ep.maxpacket) != 0) {
935 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
936 return -EMSGSIZE;
937 }
938
939 udc = ep->udc;
940 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
941 return -ESHUTDOWN;
942
943 if (use_dma && ep->has_dma) {
944 if (req->req.dma == DMA_ADDR_INVALID) {
945 req->req.dma = dma_map_single(
946 ep->udc->gadget.dev.parent,
947 req->req.buf,
948 req->req.length,
949 (ep->bEndpointAddress & USB_DIR_IN)
950 ? DMA_TO_DEVICE
951 : DMA_FROM_DEVICE);
952 req->mapped = 1;
953 } else {
954 dma_sync_single_for_device(
955 ep->udc->gadget.dev.parent,
956 req->req.dma, req->req.length,
957 (ep->bEndpointAddress & USB_DIR_IN)
958 ? DMA_TO_DEVICE
959 : DMA_FROM_DEVICE);
960 req->mapped = 0;
961 }
962 }
963
964 VDBG("%s queue req %p, len %d buf %p\n",
965 ep->ep.name, _req, _req->length, _req->buf);
966
967 spin_lock_irqsave(&udc->lock, flags);
968
969 req->req.status = -EINPROGRESS;
970 req->req.actual = 0;
971
972 /* maybe kickstart non-iso i/o queues */
973 if (is_iso)
974 UDC_IRQ_EN_REG |= UDC_SOF_IE;
975 else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
976 int is_in;
977
978 if (ep->bEndpointAddress == 0) {
979 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
980 spin_unlock_irqrestore(&udc->lock, flags);
981 return -EL2HLT;
982 }
983
984 /* empty DATA stage? */
985 is_in = udc->ep0_in;
986 if (!req->req.length) {
987
988 /* chip became CONFIGURED or ADDRESSED
989 * earlier; drivers may already have queued
990 * requests to non-control endpoints
991 */
992 if (udc->ep0_set_config) {
993 u16 irq_en = UDC_IRQ_EN_REG;
994
995 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
996 if (!udc->ep0_reset_config)
997 irq_en |= UDC_EPN_RX_IE
998 | UDC_EPN_TX_IE;
999 UDC_IRQ_EN_REG = irq_en;
1000 }
1001
1002 /* STATUS for zero length DATA stages is
1003 * always an IN ... even for IN transfers,
1004 * a wierd case which seem to stall OMAP.
1005 */
1006 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1007 UDC_CTRL_REG = UDC_CLR_EP;
1008 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1009 UDC_EP_NUM_REG = UDC_EP_DIR;
1010
1011 /* cleanup */
1012 udc->ep0_pending = 0;
1013 done(ep, req, 0);
1014 req = NULL;
1015
1016 /* non-empty DATA stage */
1017 } else if (is_in) {
1018 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1019 } else {
1020 if (udc->ep0_setup)
1021 goto irq_wait;
1022 UDC_EP_NUM_REG = UDC_EP_SEL;
1023 }
1024 } else {
1025 is_in = ep->bEndpointAddress & USB_DIR_IN;
1026 if (!ep->has_dma)
1027 use_ep(ep, UDC_EP_SEL);
1028 /* if ISO: SOF IRQs must be enabled/disabled! */
1029 }
1030
1031 if (ep->has_dma)
1032 (is_in ? next_in_dma : next_out_dma)(ep, req);
1033 else if (req) {
1034 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1035 req = NULL;
1036 deselect_ep();
1037 if (!is_in) {
1038 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1039 ep->ackwait = 1 + ep->double_buf;
1040 }
1041 /* IN: 6 wait states before it'll tx */
1042 }
1043 }
1044
1045 irq_wait:
1046 /* irq handler advances the queue */
1047 if (req != NULL)
1048 list_add_tail(&req->queue, &ep->queue);
1049 spin_unlock_irqrestore(&udc->lock, flags);
1050
1051 return 0;
1052 }
1053
1054 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1055 {
1056 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1057 struct omap_req *req;
1058 unsigned long flags;
1059
1060 if (!_ep || !_req)
1061 return -EINVAL;
1062
1063 spin_lock_irqsave(&ep->udc->lock, flags);
1064
1065 /* make sure it's actually queued on this endpoint */
1066 list_for_each_entry (req, &ep->queue, queue) {
1067 if (&req->req == _req)
1068 break;
1069 }
1070 if (&req->req != _req) {
1071 spin_unlock_irqrestore(&ep->udc->lock, flags);
1072 return -EINVAL;
1073 }
1074
1075 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1076 int channel = ep->dma_channel;
1077
1078 /* releasing the channel cancels the request,
1079 * reclaiming the channel restarts the queue
1080 */
1081 dma_channel_release(ep);
1082 dma_channel_claim(ep, channel);
1083 } else
1084 done(ep, req, -ECONNRESET);
1085 spin_unlock_irqrestore(&ep->udc->lock, flags);
1086 return 0;
1087 }
1088
1089 /*-------------------------------------------------------------------------*/
1090
1091 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1092 {
1093 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1094 unsigned long flags;
1095 int status = -EOPNOTSUPP;
1096
1097 spin_lock_irqsave(&ep->udc->lock, flags);
1098
1099 /* just use protocol stalls for ep0; real halts are annoying */
1100 if (ep->bEndpointAddress == 0) {
1101 if (!ep->udc->ep0_pending)
1102 status = -EINVAL;
1103 else if (value) {
1104 if (ep->udc->ep0_set_config) {
1105 WARN("error changing config?\n");
1106 UDC_SYSCON2_REG = UDC_CLR_CFG;
1107 }
1108 UDC_SYSCON2_REG = UDC_STALL_CMD;
1109 ep->udc->ep0_pending = 0;
1110 status = 0;
1111 } else /* NOP */
1112 status = 0;
1113
1114 /* otherwise, all active non-ISO endpoints can halt */
1115 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1116
1117 /* IN endpoints must already be idle */
1118 if ((ep->bEndpointAddress & USB_DIR_IN)
1119 && !list_empty(&ep->queue)) {
1120 status = -EAGAIN;
1121 goto done;
1122 }
1123
1124 if (value) {
1125 int channel;
1126
1127 if (use_dma && ep->dma_channel
1128 && !list_empty(&ep->queue)) {
1129 channel = ep->dma_channel;
1130 dma_channel_release(ep);
1131 } else
1132 channel = 0;
1133
1134 use_ep(ep, UDC_EP_SEL);
1135 if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1136 UDC_CTRL_REG = UDC_SET_HALT;
1137 status = 0;
1138 } else
1139 status = -EAGAIN;
1140 deselect_ep();
1141
1142 if (channel)
1143 dma_channel_claim(ep, channel);
1144 } else {
1145 use_ep(ep, 0);
1146 UDC_CTRL_REG = ep->udc->clr_halt;
1147 ep->ackwait = 0;
1148 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1149 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1150 ep->ackwait = 1 + ep->double_buf;
1151 }
1152 }
1153 }
1154 done:
1155 VDBG("%s %s halt stat %d\n", ep->ep.name,
1156 value ? "set" : "clear", status);
1157
1158 spin_unlock_irqrestore(&ep->udc->lock, flags);
1159 return status;
1160 }
1161
1162 static struct usb_ep_ops omap_ep_ops = {
1163 .enable = omap_ep_enable,
1164 .disable = omap_ep_disable,
1165
1166 .alloc_request = omap_alloc_request,
1167 .free_request = omap_free_request,
1168
1169 .queue = omap_ep_queue,
1170 .dequeue = omap_ep_dequeue,
1171
1172 .set_halt = omap_ep_set_halt,
1173 // fifo_status ... report bytes in fifo
1174 // fifo_flush ... flush fifo
1175 };
1176
1177 /*-------------------------------------------------------------------------*/
1178
1179 static int omap_get_frame(struct usb_gadget *gadget)
1180 {
1181 u16 sof = UDC_SOF_REG;
1182 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1183 }
1184
1185 static int omap_wakeup(struct usb_gadget *gadget)
1186 {
1187 struct omap_udc *udc;
1188 unsigned long flags;
1189 int retval = -EHOSTUNREACH;
1190
1191 udc = container_of(gadget, struct omap_udc, gadget);
1192
1193 spin_lock_irqsave(&udc->lock, flags);
1194 if (udc->devstat & UDC_SUS) {
1195 /* NOTE: OTG spec erratum says that OTG devices may
1196 * issue wakeups without host enable.
1197 */
1198 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1199 DBG("remote wakeup...\n");
1200 UDC_SYSCON2_REG = UDC_RMT_WKP;
1201 retval = 0;
1202 }
1203
1204 /* NOTE: non-OTG systems may use SRP TOO... */
1205 } else if (!(udc->devstat & UDC_ATT)) {
1206 if (udc->transceiver)
1207 retval = otg_start_srp(udc->transceiver);
1208 }
1209 spin_unlock_irqrestore(&udc->lock, flags);
1210
1211 return retval;
1212 }
1213
1214 static int
1215 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1216 {
1217 struct omap_udc *udc;
1218 unsigned long flags;
1219 u16 syscon1;
1220
1221 udc = container_of(gadget, struct omap_udc, gadget);
1222 spin_lock_irqsave(&udc->lock, flags);
1223 syscon1 = UDC_SYSCON1_REG;
1224 if (is_selfpowered)
1225 syscon1 |= UDC_SELF_PWR;
1226 else
1227 syscon1 &= ~UDC_SELF_PWR;
1228 UDC_SYSCON1_REG = syscon1;
1229 spin_unlock_irqrestore(&udc->lock, flags);
1230
1231 return 0;
1232 }
1233
1234 static int can_pullup(struct omap_udc *udc)
1235 {
1236 return udc->driver && udc->softconnect && udc->vbus_active;
1237 }
1238
1239 static void pullup_enable(struct omap_udc *udc)
1240 {
1241 udc->gadget.dev.parent->power.power_state = PMSG_ON;
1242 udc->gadget.dev.power.power_state = PMSG_ON;
1243 UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1244 if (!gadget_is_otg(udc->gadget) && !cpu_is_omap15xx())
1245 OTG_CTRL_REG |= OTG_BSESSVLD;
1246 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1247 }
1248
1249 static void pullup_disable(struct omap_udc *udc)
1250 {
1251 if (!gadget_is_otg(udc->gadget) && !cpu_is_omap15xx())
1252 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1253 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1254 UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1255 }
1256
1257 static struct omap_udc *udc;
1258
1259 static void omap_udc_enable_clock(int enable)
1260 {
1261 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1262 return;
1263
1264 if (enable) {
1265 clk_enable(udc->dc_clk);
1266 clk_enable(udc->hhc_clk);
1267 udelay(100);
1268 } else {
1269 clk_disable(udc->hhc_clk);
1270 clk_disable(udc->dc_clk);
1271 }
1272 }
1273
1274 /*
1275 * Called by whatever detects VBUS sessions: external transceiver
1276 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1277 */
1278 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1279 {
1280 struct omap_udc *udc;
1281 unsigned long flags;
1282
1283 udc = container_of(gadget, struct omap_udc, gadget);
1284 spin_lock_irqsave(&udc->lock, flags);
1285 VDBG("VBUS %s\n", is_active ? "on" : "off");
1286 udc->vbus_active = (is_active != 0);
1287 if (cpu_is_omap15xx()) {
1288 /* "software" detect, ignored if !VBUS_MODE_1510 */
1289 if (is_active)
1290 FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1291 else
1292 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1293 }
1294 if (udc->dc_clk != NULL && is_active) {
1295 if (!udc->clk_requested) {
1296 omap_udc_enable_clock(1);
1297 udc->clk_requested = 1;
1298 }
1299 }
1300 if (can_pullup(udc))
1301 pullup_enable(udc);
1302 else
1303 pullup_disable(udc);
1304 if (udc->dc_clk != NULL && !is_active) {
1305 if (udc->clk_requested) {
1306 omap_udc_enable_clock(0);
1307 udc->clk_requested = 0;
1308 }
1309 }
1310 spin_unlock_irqrestore(&udc->lock, flags);
1311 return 0;
1312 }
1313
1314 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1315 {
1316 struct omap_udc *udc;
1317
1318 udc = container_of(gadget, struct omap_udc, gadget);
1319 if (udc->transceiver)
1320 return otg_set_power(udc->transceiver, mA);
1321 return -EOPNOTSUPP;
1322 }
1323
1324 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1325 {
1326 struct omap_udc *udc;
1327 unsigned long flags;
1328
1329 udc = container_of(gadget, struct omap_udc, gadget);
1330 spin_lock_irqsave(&udc->lock, flags);
1331 udc->softconnect = (is_on != 0);
1332 if (can_pullup(udc))
1333 pullup_enable(udc);
1334 else
1335 pullup_disable(udc);
1336 spin_unlock_irqrestore(&udc->lock, flags);
1337 return 0;
1338 }
1339
1340 static struct usb_gadget_ops omap_gadget_ops = {
1341 .get_frame = omap_get_frame,
1342 .wakeup = omap_wakeup,
1343 .set_selfpowered = omap_set_selfpowered,
1344 .vbus_session = omap_vbus_session,
1345 .vbus_draw = omap_vbus_draw,
1346 .pullup = omap_pullup,
1347 };
1348
1349 /*-------------------------------------------------------------------------*/
1350
1351 /* dequeue ALL requests; caller holds udc->lock */
1352 static void nuke(struct omap_ep *ep, int status)
1353 {
1354 struct omap_req *req;
1355
1356 ep->stopped = 1;
1357
1358 if (use_dma && ep->dma_channel)
1359 dma_channel_release(ep);
1360
1361 use_ep(ep, 0);
1362 UDC_CTRL_REG = UDC_CLR_EP;
1363 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1364 UDC_CTRL_REG = UDC_SET_HALT;
1365
1366 while (!list_empty(&ep->queue)) {
1367 req = list_entry(ep->queue.next, struct omap_req, queue);
1368 done(ep, req, status);
1369 }
1370 }
1371
1372 /* caller holds udc->lock */
1373 static void udc_quiesce(struct omap_udc *udc)
1374 {
1375 struct omap_ep *ep;
1376
1377 udc->gadget.speed = USB_SPEED_UNKNOWN;
1378 nuke(&udc->ep[0], -ESHUTDOWN);
1379 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1380 nuke(ep, -ESHUTDOWN);
1381 }
1382
1383 /*-------------------------------------------------------------------------*/
1384
1385 static void update_otg(struct omap_udc *udc)
1386 {
1387 u16 devstat;
1388
1389 if (!gadget_is_otg(udc->gadget))
1390 return;
1391
1392 if (OTG_CTRL_REG & OTG_ID)
1393 devstat = UDC_DEVSTAT_REG;
1394 else
1395 devstat = 0;
1396
1397 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1398 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1399 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1400
1401 /* Enable HNP early, avoiding races on suspend irq path.
1402 * ASSUMES OTG state machine B_BUS_REQ input is true.
1403 */
1404 if (udc->gadget.b_hnp_enable)
1405 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1406 & ~OTG_PULLUP;
1407 }
1408
1409 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1410 {
1411 struct omap_ep *ep0 = &udc->ep[0];
1412 struct omap_req *req = NULL;
1413
1414 ep0->irqs++;
1415
1416 /* Clear any pending requests and then scrub any rx/tx state
1417 * before starting to handle the SETUP request.
1418 */
1419 if (irq_src & UDC_SETUP) {
1420 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1421
1422 nuke(ep0, 0);
1423 if (ack) {
1424 UDC_IRQ_SRC_REG = ack;
1425 irq_src = UDC_SETUP;
1426 }
1427 }
1428
1429 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1430 * This driver uses only uses protocol stalls (ep0 never halts),
1431 * and if we got this far the gadget driver already had a
1432 * chance to stall. Tries to be forgiving of host oddities.
1433 *
1434 * NOTE: the last chance gadget drivers have to stall control
1435 * requests is during their request completion callback.
1436 */
1437 if (!list_empty(&ep0->queue))
1438 req = container_of(ep0->queue.next, struct omap_req, queue);
1439
1440 /* IN == TX to host */
1441 if (irq_src & UDC_EP0_TX) {
1442 int stat;
1443
1444 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1445 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1446 stat = UDC_STAT_FLG_REG;
1447 if (stat & UDC_ACK) {
1448 if (udc->ep0_in) {
1449 /* write next IN packet from response,
1450 * or set up the status stage.
1451 */
1452 if (req)
1453 stat = write_fifo(ep0, req);
1454 UDC_EP_NUM_REG = UDC_EP_DIR;
1455 if (!req && udc->ep0_pending) {
1456 UDC_EP_NUM_REG = UDC_EP_SEL;
1457 UDC_CTRL_REG = UDC_CLR_EP;
1458 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1459 UDC_EP_NUM_REG = 0;
1460 udc->ep0_pending = 0;
1461 } /* else: 6 wait states before it'll tx */
1462 } else {
1463 /* ack status stage of OUT transfer */
1464 UDC_EP_NUM_REG = UDC_EP_DIR;
1465 if (req)
1466 done(ep0, req, 0);
1467 }
1468 req = NULL;
1469 } else if (stat & UDC_STALL) {
1470 UDC_CTRL_REG = UDC_CLR_HALT;
1471 UDC_EP_NUM_REG = UDC_EP_DIR;
1472 } else {
1473 UDC_EP_NUM_REG = UDC_EP_DIR;
1474 }
1475 }
1476
1477 /* OUT == RX from host */
1478 if (irq_src & UDC_EP0_RX) {
1479 int stat;
1480
1481 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1482 UDC_EP_NUM_REG = UDC_EP_SEL;
1483 stat = UDC_STAT_FLG_REG;
1484 if (stat & UDC_ACK) {
1485 if (!udc->ep0_in) {
1486 stat = 0;
1487 /* read next OUT packet of request, maybe
1488 * reactiviting the fifo; stall on errors.
1489 */
1490 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1491 UDC_SYSCON2_REG = UDC_STALL_CMD;
1492 udc->ep0_pending = 0;
1493 stat = 0;
1494 } else if (stat == 0)
1495 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1496 UDC_EP_NUM_REG = 0;
1497
1498 /* activate status stage */
1499 if (stat == 1) {
1500 done(ep0, req, 0);
1501 /* that may have STALLed ep0... */
1502 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1503 UDC_CTRL_REG = UDC_CLR_EP;
1504 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1505 UDC_EP_NUM_REG = UDC_EP_DIR;
1506 udc->ep0_pending = 0;
1507 }
1508 } else {
1509 /* ack status stage of IN transfer */
1510 UDC_EP_NUM_REG = 0;
1511 if (req)
1512 done(ep0, req, 0);
1513 }
1514 } else if (stat & UDC_STALL) {
1515 UDC_CTRL_REG = UDC_CLR_HALT;
1516 UDC_EP_NUM_REG = 0;
1517 } else {
1518 UDC_EP_NUM_REG = 0;
1519 }
1520 }
1521
1522 /* SETUP starts all control transfers */
1523 if (irq_src & UDC_SETUP) {
1524 union u {
1525 u16 word[4];
1526 struct usb_ctrlrequest r;
1527 } u;
1528 int status = -EINVAL;
1529 struct omap_ep *ep;
1530
1531 /* read the (latest) SETUP message */
1532 do {
1533 UDC_EP_NUM_REG = UDC_SETUP_SEL;
1534 /* two bytes at a time */
1535 u.word[0] = UDC_DATA_REG;
1536 u.word[1] = UDC_DATA_REG;
1537 u.word[2] = UDC_DATA_REG;
1538 u.word[3] = UDC_DATA_REG;
1539 UDC_EP_NUM_REG = 0;
1540 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1541
1542 #define w_value le16_to_cpu(u.r.wValue)
1543 #define w_index le16_to_cpu(u.r.wIndex)
1544 #define w_length le16_to_cpu(u.r.wLength)
1545
1546 /* Delegate almost all control requests to the gadget driver,
1547 * except for a handful of ch9 status/feature requests that
1548 * hardware doesn't autodecode _and_ the gadget API hides.
1549 */
1550 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1551 udc->ep0_set_config = 0;
1552 udc->ep0_pending = 1;
1553 ep0->stopped = 0;
1554 ep0->ackwait = 0;
1555 switch (u.r.bRequest) {
1556 case USB_REQ_SET_CONFIGURATION:
1557 /* udc needs to know when ep != 0 is valid */
1558 if (u.r.bRequestType != USB_RECIP_DEVICE)
1559 goto delegate;
1560 if (w_length != 0)
1561 goto do_stall;
1562 udc->ep0_set_config = 1;
1563 udc->ep0_reset_config = (w_value == 0);
1564 VDBG("set config %d\n", w_value);
1565
1566 /* update udc NOW since gadget driver may start
1567 * queueing requests immediately; clear config
1568 * later if it fails the request.
1569 */
1570 if (udc->ep0_reset_config)
1571 UDC_SYSCON2_REG = UDC_CLR_CFG;
1572 else
1573 UDC_SYSCON2_REG = UDC_DEV_CFG;
1574 update_otg(udc);
1575 goto delegate;
1576 case USB_REQ_CLEAR_FEATURE:
1577 /* clear endpoint halt */
1578 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1579 goto delegate;
1580 if (w_value != USB_ENDPOINT_HALT
1581 || w_length != 0)
1582 goto do_stall;
1583 ep = &udc->ep[w_index & 0xf];
1584 if (ep != ep0) {
1585 if (w_index & USB_DIR_IN)
1586 ep += 16;
1587 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1588 || !ep->desc)
1589 goto do_stall;
1590 use_ep(ep, 0);
1591 UDC_CTRL_REG = udc->clr_halt;
1592 ep->ackwait = 0;
1593 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1594 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1595 ep->ackwait = 1 + ep->double_buf;
1596 }
1597 /* NOTE: assumes the host behaves sanely,
1598 * only clearing real halts. Else we may
1599 * need to kill pending transfers and then
1600 * restart the queue... very messy for DMA!
1601 */
1602 }
1603 VDBG("%s halt cleared by host\n", ep->name);
1604 goto ep0out_status_stage;
1605 case USB_REQ_SET_FEATURE:
1606 /* set endpoint halt */
1607 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1608 goto delegate;
1609 if (w_value != USB_ENDPOINT_HALT
1610 || w_length != 0)
1611 goto do_stall;
1612 ep = &udc->ep[w_index & 0xf];
1613 if (w_index & USB_DIR_IN)
1614 ep += 16;
1615 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1616 || ep == ep0 || !ep->desc)
1617 goto do_stall;
1618 if (use_dma && ep->has_dma) {
1619 /* this has rude side-effects (aborts) and
1620 * can't really work if DMA-IN is active
1621 */
1622 DBG("%s host set_halt, NYET \n", ep->name);
1623 goto do_stall;
1624 }
1625 use_ep(ep, 0);
1626 /* can't halt if fifo isn't empty... */
1627 UDC_CTRL_REG = UDC_CLR_EP;
1628 UDC_CTRL_REG = UDC_SET_HALT;
1629 VDBG("%s halted by host\n", ep->name);
1630 ep0out_status_stage:
1631 status = 0;
1632 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1633 UDC_CTRL_REG = UDC_CLR_EP;
1634 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1635 UDC_EP_NUM_REG = UDC_EP_DIR;
1636 udc->ep0_pending = 0;
1637 break;
1638 case USB_REQ_GET_STATUS:
1639 /* USB_ENDPOINT_HALT status? */
1640 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1641 goto intf_status;
1642
1643 /* ep0 never stalls */
1644 if (!(w_index & 0xf))
1645 goto zero_status;
1646
1647 /* only active endpoints count */
1648 ep = &udc->ep[w_index & 0xf];
1649 if (w_index & USB_DIR_IN)
1650 ep += 16;
1651 if (!ep->desc)
1652 goto do_stall;
1653
1654 /* iso never stalls */
1655 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1656 goto zero_status;
1657
1658 /* FIXME don't assume non-halted endpoints!! */
1659 ERR("%s status, can't report\n", ep->ep.name);
1660 goto do_stall;
1661
1662 intf_status:
1663 /* return interface status. if we were pedantic,
1664 * we'd detect non-existent interfaces, and stall.
1665 */
1666 if (u.r.bRequestType
1667 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1668 goto delegate;
1669
1670 zero_status:
1671 /* return two zero bytes */
1672 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1673 UDC_DATA_REG = 0;
1674 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1675 UDC_EP_NUM_REG = UDC_EP_DIR;
1676 status = 0;
1677 VDBG("GET_STATUS, interface %d\n", w_index);
1678 /* next, status stage */
1679 break;
1680 default:
1681 delegate:
1682 /* activate the ep0out fifo right away */
1683 if (!udc->ep0_in && w_length) {
1684 UDC_EP_NUM_REG = 0;
1685 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1686 }
1687
1688 /* gadget drivers see class/vendor specific requests,
1689 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1690 * and more
1691 */
1692 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1693 u.r.bRequestType, u.r.bRequest,
1694 w_value, w_index, w_length);
1695
1696 #undef w_value
1697 #undef w_index
1698 #undef w_length
1699
1700 /* The gadget driver may return an error here,
1701 * causing an immediate protocol stall.
1702 *
1703 * Else it must issue a response, either queueing a
1704 * response buffer for the DATA stage, or halting ep0
1705 * (causing a protocol stall, not a real halt). A
1706 * zero length buffer means no DATA stage.
1707 *
1708 * It's fine to issue that response after the setup()
1709 * call returns, and this IRQ was handled.
1710 */
1711 udc->ep0_setup = 1;
1712 spin_unlock(&udc->lock);
1713 status = udc->driver->setup (&udc->gadget, &u.r);
1714 spin_lock(&udc->lock);
1715 udc->ep0_setup = 0;
1716 }
1717
1718 if (status < 0) {
1719 do_stall:
1720 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1721 u.r.bRequestType, u.r.bRequest, status);
1722 if (udc->ep0_set_config) {
1723 if (udc->ep0_reset_config)
1724 WARN("error resetting config?\n");
1725 else
1726 UDC_SYSCON2_REG = UDC_CLR_CFG;
1727 }
1728 UDC_SYSCON2_REG = UDC_STALL_CMD;
1729 udc->ep0_pending = 0;
1730 }
1731 }
1732 }
1733
1734 /*-------------------------------------------------------------------------*/
1735
1736 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1737
1738 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1739 {
1740 u16 devstat, change;
1741
1742 devstat = UDC_DEVSTAT_REG;
1743 change = devstat ^ udc->devstat;
1744 udc->devstat = devstat;
1745
1746 if (change & (UDC_USB_RESET|UDC_ATT)) {
1747 udc_quiesce(udc);
1748
1749 if (change & UDC_ATT) {
1750 /* driver for any external transceiver will
1751 * have called omap_vbus_session() already
1752 */
1753 if (devstat & UDC_ATT) {
1754 udc->gadget.speed = USB_SPEED_FULL;
1755 VDBG("connect\n");
1756 if (!udc->transceiver)
1757 pullup_enable(udc);
1758 // if (driver->connect) call it
1759 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1760 udc->gadget.speed = USB_SPEED_UNKNOWN;
1761 if (!udc->transceiver)
1762 pullup_disable(udc);
1763 DBG("disconnect, gadget %s\n",
1764 udc->driver->driver.name);
1765 if (udc->driver->disconnect) {
1766 spin_unlock(&udc->lock);
1767 udc->driver->disconnect(&udc->gadget);
1768 spin_lock(&udc->lock);
1769 }
1770 }
1771 change &= ~UDC_ATT;
1772 }
1773
1774 if (change & UDC_USB_RESET) {
1775 if (devstat & UDC_USB_RESET) {
1776 VDBG("RESET=1\n");
1777 } else {
1778 udc->gadget.speed = USB_SPEED_FULL;
1779 INFO("USB reset done, gadget %s\n",
1780 udc->driver->driver.name);
1781 /* ep0 traffic is legal from now on */
1782 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1783 }
1784 change &= ~UDC_USB_RESET;
1785 }
1786 }
1787 if (change & UDC_SUS) {
1788 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1789 // FIXME tell isp1301 to suspend/resume (?)
1790 if (devstat & UDC_SUS) {
1791 VDBG("suspend\n");
1792 update_otg(udc);
1793 /* HNP could be under way already */
1794 if (udc->gadget.speed == USB_SPEED_FULL
1795 && udc->driver->suspend) {
1796 spin_unlock(&udc->lock);
1797 udc->driver->suspend(&udc->gadget);
1798 spin_lock(&udc->lock);
1799 }
1800 if (udc->transceiver)
1801 otg_set_suspend(udc->transceiver, 1);
1802 } else {
1803 VDBG("resume\n");
1804 if (udc->transceiver)
1805 otg_set_suspend(udc->transceiver, 0);
1806 if (udc->gadget.speed == USB_SPEED_FULL
1807 && udc->driver->resume) {
1808 spin_unlock(&udc->lock);
1809 udc->driver->resume(&udc->gadget);
1810 spin_lock(&udc->lock);
1811 }
1812 }
1813 }
1814 change &= ~UDC_SUS;
1815 }
1816 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1817 update_otg(udc);
1818 change &= ~OTG_FLAGS;
1819 }
1820
1821 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1822 if (change)
1823 VDBG("devstat %03x, ignore change %03x\n",
1824 devstat, change);
1825
1826 UDC_IRQ_SRC_REG = UDC_DS_CHG;
1827 }
1828
1829 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1830 {
1831 struct omap_udc *udc = _udc;
1832 u16 irq_src;
1833 irqreturn_t status = IRQ_NONE;
1834 unsigned long flags;
1835
1836 spin_lock_irqsave(&udc->lock, flags);
1837 irq_src = UDC_IRQ_SRC_REG;
1838
1839 /* Device state change (usb ch9 stuff) */
1840 if (irq_src & UDC_DS_CHG) {
1841 devstate_irq(_udc, irq_src);
1842 status = IRQ_HANDLED;
1843 irq_src &= ~UDC_DS_CHG;
1844 }
1845
1846 /* EP0 control transfers */
1847 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1848 ep0_irq(_udc, irq_src);
1849 status = IRQ_HANDLED;
1850 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1851 }
1852
1853 /* DMA transfer completion */
1854 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1855 dma_irq(_udc, irq_src);
1856 status = IRQ_HANDLED;
1857 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1858 }
1859
1860 irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1861 if (irq_src)
1862 DBG("udc_irq, unhandled %03x\n", irq_src);
1863 spin_unlock_irqrestore(&udc->lock, flags);
1864
1865 return status;
1866 }
1867
1868 /* workaround for seemingly-lost IRQs for RX ACKs... */
1869 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1870 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1871
1872 static void pio_out_timer(unsigned long _ep)
1873 {
1874 struct omap_ep *ep = (void *) _ep;
1875 unsigned long flags;
1876 u16 stat_flg;
1877
1878 spin_lock_irqsave(&ep->udc->lock, flags);
1879 if (!list_empty(&ep->queue) && ep->ackwait) {
1880 use_ep(ep, UDC_EP_SEL);
1881 stat_flg = UDC_STAT_FLG_REG;
1882
1883 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1884 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1885 struct omap_req *req;
1886
1887 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1888 req = container_of(ep->queue.next,
1889 struct omap_req, queue);
1890 (void) read_fifo(ep, req);
1891 UDC_EP_NUM_REG = ep->bEndpointAddress;
1892 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1893 ep->ackwait = 1 + ep->double_buf;
1894 } else
1895 deselect_ep();
1896 }
1897 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1898 spin_unlock_irqrestore(&ep->udc->lock, flags);
1899 }
1900
1901 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1902 {
1903 u16 epn_stat, irq_src;
1904 irqreturn_t status = IRQ_NONE;
1905 struct omap_ep *ep;
1906 int epnum;
1907 struct omap_udc *udc = _dev;
1908 struct omap_req *req;
1909 unsigned long flags;
1910
1911 spin_lock_irqsave(&udc->lock, flags);
1912 epn_stat = UDC_EPN_STAT_REG;
1913 irq_src = UDC_IRQ_SRC_REG;
1914
1915 /* handle OUT first, to avoid some wasteful NAKs */
1916 if (irq_src & UDC_EPN_RX) {
1917 epnum = (epn_stat >> 8) & 0x0f;
1918 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1919 status = IRQ_HANDLED;
1920 ep = &udc->ep[epnum];
1921 ep->irqs++;
1922
1923 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1924 ep->fnf = 0;
1925 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1926 ep->ackwait--;
1927 if (!list_empty(&ep->queue)) {
1928 int stat;
1929 req = container_of(ep->queue.next,
1930 struct omap_req, queue);
1931 stat = read_fifo(ep, req);
1932 if (!ep->double_buf)
1933 ep->fnf = 1;
1934 }
1935 }
1936 /* min 6 clock delay before clearing EP_SEL ... */
1937 epn_stat = UDC_EPN_STAT_REG;
1938 epn_stat = UDC_EPN_STAT_REG;
1939 UDC_EP_NUM_REG = epnum;
1940
1941 /* enabling fifo _after_ clearing ACK, contrary to docs,
1942 * reduces lossage; timer still needed though (sigh).
1943 */
1944 if (ep->fnf) {
1945 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1946 ep->ackwait = 1 + ep->double_buf;
1947 }
1948 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1949 }
1950
1951 /* then IN transfers */
1952 else if (irq_src & UDC_EPN_TX) {
1953 epnum = epn_stat & 0x0f;
1954 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1955 status = IRQ_HANDLED;
1956 ep = &udc->ep[16 + epnum];
1957 ep->irqs++;
1958
1959 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1960 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1961 ep->ackwait = 0;
1962 if (!list_empty(&ep->queue)) {
1963 req = container_of(ep->queue.next,
1964 struct omap_req, queue);
1965 (void) write_fifo(ep, req);
1966 }
1967 }
1968 /* min 6 clock delay before clearing EP_SEL ... */
1969 epn_stat = UDC_EPN_STAT_REG;
1970 epn_stat = UDC_EPN_STAT_REG;
1971 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1972 /* then 6 clocks before it'd tx */
1973 }
1974
1975 spin_unlock_irqrestore(&udc->lock, flags);
1976 return status;
1977 }
1978
1979 #ifdef USE_ISO
1980 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1981 {
1982 struct omap_udc *udc = _dev;
1983 struct omap_ep *ep;
1984 int pending = 0;
1985 unsigned long flags;
1986
1987 spin_lock_irqsave(&udc->lock, flags);
1988
1989 /* handle all non-DMA ISO transfers */
1990 list_for_each_entry (ep, &udc->iso, iso) {
1991 u16 stat;
1992 struct omap_req *req;
1993
1994 if (ep->has_dma || list_empty(&ep->queue))
1995 continue;
1996 req = list_entry(ep->queue.next, struct omap_req, queue);
1997
1998 use_ep(ep, UDC_EP_SEL);
1999 stat = UDC_STAT_FLG_REG;
2000
2001 /* NOTE: like the other controller drivers, this isn't
2002 * currently reporting lost or damaged frames.
2003 */
2004 if (ep->bEndpointAddress & USB_DIR_IN) {
2005 if (stat & UDC_MISS_IN)
2006 /* done(ep, req, -EPROTO) */;
2007 else
2008 write_fifo(ep, req);
2009 } else {
2010 int status = 0;
2011
2012 if (stat & UDC_NO_RXPACKET)
2013 status = -EREMOTEIO;
2014 else if (stat & UDC_ISO_ERR)
2015 status = -EILSEQ;
2016 else if (stat & UDC_DATA_FLUSH)
2017 status = -ENOSR;
2018
2019 if (status)
2020 /* done(ep, req, status) */;
2021 else
2022 read_fifo(ep, req);
2023 }
2024 deselect_ep();
2025 /* 6 wait states before next EP */
2026
2027 ep->irqs++;
2028 if (!list_empty(&ep->queue))
2029 pending = 1;
2030 }
2031 if (!pending)
2032 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2033 UDC_IRQ_SRC_REG = UDC_SOF;
2034
2035 spin_unlock_irqrestore(&udc->lock, flags);
2036 return IRQ_HANDLED;
2037 }
2038 #endif
2039
2040 /*-------------------------------------------------------------------------*/
2041
2042 static inline int machine_without_vbus_sense(void)
2043 {
2044 return (machine_is_omap_innovator()
2045 || machine_is_omap_osk()
2046 || machine_is_omap_apollon()
2047 #ifndef CONFIG_MACH_OMAP_H4_OTG
2048 || machine_is_omap_h4()
2049 #endif
2050 || machine_is_sx1()
2051 );
2052 }
2053
2054 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2055 {
2056 int status = -ENODEV;
2057 struct omap_ep *ep;
2058 unsigned long flags;
2059
2060 /* basic sanity tests */
2061 if (!udc)
2062 return -ENODEV;
2063 if (!driver
2064 // FIXME if otg, check: driver->is_otg
2065 || driver->speed < USB_SPEED_FULL
2066 || !driver->bind
2067 || !driver->setup)
2068 return -EINVAL;
2069
2070 spin_lock_irqsave(&udc->lock, flags);
2071 if (udc->driver) {
2072 spin_unlock_irqrestore(&udc->lock, flags);
2073 return -EBUSY;
2074 }
2075
2076 /* reset state */
2077 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2078 ep->irqs = 0;
2079 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2080 continue;
2081 use_ep(ep, 0);
2082 UDC_CTRL_REG = UDC_SET_HALT;
2083 }
2084 udc->ep0_pending = 0;
2085 udc->ep[0].irqs = 0;
2086 udc->softconnect = 1;
2087
2088 /* hook up the driver */
2089 driver->driver.bus = NULL;
2090 udc->driver = driver;
2091 udc->gadget.dev.driver = &driver->driver;
2092 spin_unlock_irqrestore(&udc->lock, flags);
2093
2094 if (udc->dc_clk != NULL)
2095 omap_udc_enable_clock(1);
2096
2097 status = driver->bind (&udc->gadget);
2098 if (status) {
2099 DBG("bind to %s --> %d\n", driver->driver.name, status);
2100 udc->gadget.dev.driver = NULL;
2101 udc->driver = NULL;
2102 goto done;
2103 }
2104 DBG("bound to driver %s\n", driver->driver.name);
2105
2106 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2107
2108 /* connect to bus through transceiver */
2109 if (udc->transceiver) {
2110 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2111 if (status < 0) {
2112 ERR("can't bind to transceiver\n");
2113 if (driver->unbind) {
2114 driver->unbind (&udc->gadget);
2115 udc->gadget.dev.driver = NULL;
2116 udc->driver = NULL;
2117 }
2118 goto done;
2119 }
2120 } else {
2121 if (can_pullup(udc))
2122 pullup_enable (udc);
2123 else
2124 pullup_disable (udc);
2125 }
2126
2127 /* boards that don't have VBUS sensing can't autogate 48MHz;
2128 * can't enter deep sleep while a gadget driver is active.
2129 */
2130 if (machine_without_vbus_sense())
2131 omap_vbus_session(&udc->gadget, 1);
2132
2133 done:
2134 if (udc->dc_clk != NULL)
2135 omap_udc_enable_clock(0);
2136 return status;
2137 }
2138 EXPORT_SYMBOL(usb_gadget_register_driver);
2139
2140 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2141 {
2142 unsigned long flags;
2143 int status = -ENODEV;
2144
2145 if (!udc)
2146 return -ENODEV;
2147 if (!driver || driver != udc->driver || !driver->unbind)
2148 return -EINVAL;
2149
2150 if (udc->dc_clk != NULL)
2151 omap_udc_enable_clock(1);
2152
2153 if (machine_without_vbus_sense())
2154 omap_vbus_session(&udc->gadget, 0);
2155
2156 if (udc->transceiver)
2157 (void) otg_set_peripheral(udc->transceiver, NULL);
2158 else
2159 pullup_disable(udc);
2160
2161 spin_lock_irqsave(&udc->lock, flags);
2162 udc_quiesce(udc);
2163 spin_unlock_irqrestore(&udc->lock, flags);
2164
2165 driver->unbind(&udc->gadget);
2166 udc->gadget.dev.driver = NULL;
2167 udc->driver = NULL;
2168
2169 if (udc->dc_clk != NULL)
2170 omap_udc_enable_clock(0);
2171 DBG("unregistered driver '%s'\n", driver->driver.name);
2172 return status;
2173 }
2174 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2175
2176
2177 /*-------------------------------------------------------------------------*/
2178
2179 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2180
2181 #include <linux/seq_file.h>
2182
2183 static const char proc_filename[] = "driver/udc";
2184
2185 #define FOURBITS "%s%s%s%s"
2186 #define EIGHTBITS FOURBITS FOURBITS
2187
2188 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2189 {
2190 u16 stat_flg;
2191 struct omap_req *req;
2192 char buf[20];
2193
2194 use_ep(ep, 0);
2195
2196 if (use_dma && ep->has_dma)
2197 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2198 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2199 ep->dma_channel - 1, ep->lch);
2200 else
2201 buf[0] = 0;
2202
2203 stat_flg = UDC_STAT_FLG_REG;
2204 seq_printf(s,
2205 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2206 ep->name, buf,
2207 ep->double_buf ? "dbuf " : "",
2208 ({char *s; switch(ep->ackwait){
2209 case 0: s = ""; break;
2210 case 1: s = "(ackw) "; break;
2211 case 2: s = "(ackw2) "; break;
2212 default: s = "(?) "; break;
2213 } s;}),
2214 ep->irqs, stat_flg,
2215 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2216 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2217 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2218 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2219 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2220 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2221 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2222 (stat_flg & UDC_STALL) ? "STALL " : "",
2223 (stat_flg & UDC_NAK) ? "NAK " : "",
2224 (stat_flg & UDC_ACK) ? "ACK " : "",
2225 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2226 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2227 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2228
2229 if (list_empty (&ep->queue))
2230 seq_printf(s, "\t(queue empty)\n");
2231 else
2232 list_for_each_entry (req, &ep->queue, queue) {
2233 unsigned length = req->req.actual;
2234
2235 if (use_dma && buf[0]) {
2236 length += ((ep->bEndpointAddress & USB_DIR_IN)
2237 ? dma_src_len : dma_dest_len)
2238 (ep, req->req.dma + length);
2239 buf[0] = 0;
2240 }
2241 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2242 &req->req, length,
2243 req->req.length, req->req.buf);
2244 }
2245 }
2246
2247 static char *trx_mode(unsigned m, int enabled)
2248 {
2249 switch (m) {
2250 case 0: return enabled ? "*6wire" : "unused";
2251 case 1: return "4wire";
2252 case 2: return "3wire";
2253 case 3: return "6wire";
2254 default: return "unknown";
2255 }
2256 }
2257
2258 static int proc_otg_show(struct seq_file *s)
2259 {
2260 u32 tmp;
2261 u32 trans;
2262 char *ctrl_name;
2263
2264 tmp = OTG_REV_REG;
2265 if (cpu_is_omap24xx()) {
2266 ctrl_name = "control_devconf";
2267 trans = CONTROL_DEVCONF_REG;
2268 } else {
2269 ctrl_name = "tranceiver_ctrl";
2270 trans = USB_TRANSCEIVER_CTRL_REG;
2271 }
2272 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2273 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2274 tmp = OTG_SYSCON_1_REG;
2275 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2276 FOURBITS "\n", tmp,
2277 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2278 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2279 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2280 ? "internal"
2281 : trx_mode(USB0_TRX_MODE(tmp), 1),
2282 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2283 (tmp & HST_IDLE_EN) ? " !host" : "",
2284 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2285 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2286 tmp = OTG_SYSCON_2_REG;
2287 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2288 " b_ase_brst=%d hmc=%d\n", tmp,
2289 (tmp & OTG_EN) ? " otg_en" : "",
2290 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2291 // much more SRP stuff
2292 (tmp & SRP_DATA) ? " srp_data" : "",
2293 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2294 (tmp & OTG_PADEN) ? " otg_paden" : "",
2295 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2296 (tmp & UHOST_EN) ? " uhost_en" : "",
2297 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2298 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2299 B_ASE_BRST(tmp),
2300 OTG_HMC(tmp));
2301 tmp = OTG_CTRL_REG;
2302 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2303 (tmp & OTG_ASESSVLD) ? " asess" : "",
2304 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2305 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2306 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2307 (tmp & OTG_ID) ? " id" : "",
2308 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2309 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2310 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2311 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2312 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2313 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2314 (tmp & OTG_PULLDOWN) ? " down" : "",
2315 (tmp & OTG_PULLUP) ? " up" : "",
2316 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2317 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2318 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2319 (tmp & OTG_PU_ID) ? " pu_id" : ""
2320 );
2321 tmp = OTG_IRQ_EN_REG;
2322 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2323 tmp = OTG_IRQ_SRC_REG;
2324 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2325 tmp = OTG_OUTCTRL_REG;
2326 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2327 tmp = OTG_TEST_REG;
2328 seq_printf(s, "otg_test %04x" "\n", tmp);
2329 return 0;
2330 }
2331
2332 static int proc_udc_show(struct seq_file *s, void *_)
2333 {
2334 u32 tmp;
2335 struct omap_ep *ep;
2336 unsigned long flags;
2337
2338 spin_lock_irqsave(&udc->lock, flags);
2339
2340 seq_printf(s, "%s, version: " DRIVER_VERSION
2341 #ifdef USE_ISO
2342 " (iso)"
2343 #endif
2344 "%s\n",
2345 driver_desc,
2346 use_dma ? " (dma)" : "");
2347
2348 tmp = UDC_REV_REG & 0xff;
2349 seq_printf(s,
2350 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2351 "hmc %d, transceiver %s\n",
2352 tmp >> 4, tmp & 0xf,
2353 fifo_mode,
2354 udc->driver ? udc->driver->driver.name : "(none)",
2355 HMC,
2356 udc->transceiver
2357 ? udc->transceiver->label
2358 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2359 ? "external" : "(none)"));
2360 if (cpu_class_is_omap1()) {
2361 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2362 __REG16(ULPD_CLOCK_CTRL),
2363 __REG16(ULPD_SOFT_REQ),
2364 __REG16(ULPD_STATUS_REQ));
2365 }
2366
2367 /* OTG controller registers */
2368 if (!cpu_is_omap15xx())
2369 proc_otg_show(s);
2370
2371 tmp = UDC_SYSCON1_REG;
2372 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2373 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2374 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2375 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2376 (tmp & UDC_NAK_EN) ? " nak" : "",
2377 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2378 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2379 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2380 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2381 // syscon2 is write-only
2382
2383 /* UDC controller registers */
2384 if (!(tmp & UDC_PULLUP_EN)) {
2385 seq_printf(s, "(suspended)\n");
2386 spin_unlock_irqrestore(&udc->lock, flags);
2387 return 0;
2388 }
2389
2390 tmp = UDC_DEVSTAT_REG;
2391 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2392 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2393 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2394 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2395 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2396 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2397 (tmp & UDC_SUS) ? " SUS" : "",
2398 (tmp & UDC_CFG) ? " CFG" : "",
2399 (tmp & UDC_ADD) ? " ADD" : "",
2400 (tmp & UDC_DEF) ? " DEF" : "",
2401 (tmp & UDC_ATT) ? " ATT" : "");
2402 seq_printf(s, "sof %04x\n", UDC_SOF_REG);
2403 tmp = UDC_IRQ_EN_REG;
2404 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2405 (tmp & UDC_SOF_IE) ? " sof" : "",
2406 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2407 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2408 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2409 (tmp & UDC_EP0_IE) ? " ep0" : "");
2410 tmp = UDC_IRQ_SRC_REG;
2411 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2412 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2413 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2414 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2415 (tmp & UDC_SOF) ? " sof" : "",
2416 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2417 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2418 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2419 (tmp & UDC_SETUP) ? " setup" : "",
2420 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2421 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2422 if (use_dma) {
2423 unsigned i;
2424
2425 tmp = UDC_DMA_IRQ_EN_REG;
2426 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2427 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2428 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2429 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2430
2431 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2432 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2433 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2434
2435 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2436 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2437 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2438
2439 tmp = UDC_RXDMA_CFG_REG;
2440 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2441 if (tmp) {
2442 for (i = 0; i < 3; i++) {
2443 if ((tmp & (0x0f << (i * 4))) == 0)
2444 continue;
2445 seq_printf(s, "rxdma[%d] %04x\n", i,
2446 UDC_RXDMA_REG(i + 1));
2447 }
2448 }
2449 tmp = UDC_TXDMA_CFG_REG;
2450 seq_printf(s, "txdma_cfg %04x\n", tmp);
2451 if (tmp) {
2452 for (i = 0; i < 3; i++) {
2453 if (!(tmp & (0x0f << (i * 4))))
2454 continue;
2455 seq_printf(s, "txdma[%d] %04x\n", i,
2456 UDC_TXDMA_REG(i + 1));
2457 }
2458 }
2459 }
2460
2461 tmp = UDC_DEVSTAT_REG;
2462 if (tmp & UDC_ATT) {
2463 proc_ep_show(s, &udc->ep[0]);
2464 if (tmp & UDC_ADD) {
2465 list_for_each_entry (ep, &udc->gadget.ep_list,
2466 ep.ep_list) {
2467 if (ep->desc)
2468 proc_ep_show(s, ep);
2469 }
2470 }
2471 }
2472 spin_unlock_irqrestore(&udc->lock, flags);
2473 return 0;
2474 }
2475
2476 static int proc_udc_open(struct inode *inode, struct file *file)
2477 {
2478 return single_open(file, proc_udc_show, NULL);
2479 }
2480
2481 static const struct file_operations proc_ops = {
2482 .open = proc_udc_open,
2483 .read = seq_read,
2484 .llseek = seq_lseek,
2485 .release = single_release,
2486 };
2487
2488 static void create_proc_file(void)
2489 {
2490 struct proc_dir_entry *pde;
2491
2492 pde = create_proc_entry (proc_filename, 0, NULL);
2493 if (pde)
2494 pde->proc_fops = &proc_ops;
2495 }
2496
2497 static void remove_proc_file(void)
2498 {
2499 remove_proc_entry(proc_filename, NULL);
2500 }
2501
2502 #else
2503
2504 static inline void create_proc_file(void) {}
2505 static inline void remove_proc_file(void) {}
2506
2507 #endif
2508
2509 /*-------------------------------------------------------------------------*/
2510
2511 /* Before this controller can enumerate, we need to pick an endpoint
2512 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2513 * buffer space among the endpoints we'll be operating.
2514 *
2515 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2516 * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that
2517 * capability yet though.
2518 */
2519 static unsigned __init
2520 omap_ep_setup(char *name, u8 addr, u8 type,
2521 unsigned buf, unsigned maxp, int dbuf)
2522 {
2523 struct omap_ep *ep;
2524 u16 epn_rxtx = 0;
2525
2526 /* OUT endpoints first, then IN */
2527 ep = &udc->ep[addr & 0xf];
2528 if (addr & USB_DIR_IN)
2529 ep += 16;
2530
2531 /* in case of ep init table bugs */
2532 BUG_ON(ep->name[0]);
2533
2534 /* chip setup ... bit values are same for IN, OUT */
2535 if (type == USB_ENDPOINT_XFER_ISOC) {
2536 switch (maxp) {
2537 case 8: epn_rxtx = 0 << 12; break;
2538 case 16: epn_rxtx = 1 << 12; break;
2539 case 32: epn_rxtx = 2 << 12; break;
2540 case 64: epn_rxtx = 3 << 12; break;
2541 case 128: epn_rxtx = 4 << 12; break;
2542 case 256: epn_rxtx = 5 << 12; break;
2543 case 512: epn_rxtx = 6 << 12; break;
2544 default: BUG();
2545 }
2546 epn_rxtx |= UDC_EPN_RX_ISO;
2547 dbuf = 1;
2548 } else {
2549 /* double-buffering "not supported" on 15xx,
2550 * and ignored for PIO-IN on newer chips
2551 * (for more reliable behavior)
2552 */
2553 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2554 dbuf = 0;
2555
2556 switch (maxp) {
2557 case 8: epn_rxtx = 0 << 12; break;
2558 case 16: epn_rxtx = 1 << 12; break;
2559 case 32: epn_rxtx = 2 << 12; break;
2560 case 64: epn_rxtx = 3 << 12; break;
2561 default: BUG();
2562 }
2563 if (dbuf && addr)
2564 epn_rxtx |= UDC_EPN_RX_DB;
2565 init_timer(&ep->timer);
2566 ep->timer.function = pio_out_timer;
2567 ep->timer.data = (unsigned long) ep;
2568 }
2569 if (addr)
2570 epn_rxtx |= UDC_EPN_RX_VALID;
2571 BUG_ON(buf & 0x07);
2572 epn_rxtx |= buf >> 3;
2573
2574 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2575 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2576
2577 if (addr & USB_DIR_IN)
2578 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2579 else
2580 UDC_EP_RX_REG(addr) = epn_rxtx;
2581
2582 /* next endpoint's buffer starts after this one's */
2583 buf += maxp;
2584 if (dbuf)
2585 buf += maxp;
2586 BUG_ON(buf > 2048);
2587
2588 /* set up driver data structures */
2589 BUG_ON(strlen(name) >= sizeof ep->name);
2590 strlcpy(ep->name, name, sizeof ep->name);
2591 INIT_LIST_HEAD(&ep->queue);
2592 INIT_LIST_HEAD(&ep->iso);
2593 ep->bEndpointAddress = addr;
2594 ep->bmAttributes = type;
2595 ep->double_buf = dbuf;
2596 ep->udc = udc;
2597
2598 ep->ep.name = ep->name;
2599 ep->ep.ops = &omap_ep_ops;
2600 ep->ep.maxpacket = ep->maxpacket = maxp;
2601 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2602
2603 return buf;
2604 }
2605
2606 static void omap_udc_release(struct device *dev)
2607 {
2608 complete(udc->done);
2609 kfree (udc);
2610 udc = NULL;
2611 }
2612
2613 static int __init
2614 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2615 {
2616 unsigned tmp, buf;
2617
2618 /* abolish any previous hardware state */
2619 UDC_SYSCON1_REG = 0;
2620 UDC_IRQ_EN_REG = 0;
2621 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2622 UDC_DMA_IRQ_EN_REG = 0;
2623 UDC_RXDMA_CFG_REG = 0;
2624 UDC_TXDMA_CFG_REG = 0;
2625
2626 /* UDC_PULLUP_EN gates the chip clock */
2627 // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2628
2629 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2630 if (!udc)
2631 return -ENOMEM;
2632
2633 spin_lock_init (&udc->lock);
2634
2635 udc->gadget.ops = &omap_gadget_ops;
2636 udc->gadget.ep0 = &udc->ep[0].ep;
2637 INIT_LIST_HEAD(&udc->gadget.ep_list);
2638 INIT_LIST_HEAD(&udc->iso);
2639 udc->gadget.speed = USB_SPEED_UNKNOWN;
2640 udc->gadget.name = driver_name;
2641
2642 device_initialize(&udc->gadget.dev);
2643 strcpy (udc->gadget.dev.bus_id, "gadget");
2644 udc->gadget.dev.release = omap_udc_release;
2645 udc->gadget.dev.parent = &odev->dev;
2646 if (use_dma)
2647 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2648
2649 udc->transceiver = xceiv;
2650
2651 /* ep0 is special; put it right after the SETUP buffer */
2652 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2653 8 /* after SETUP */, 64 /* maxpacket */, 0);
2654 list_del_init(&udc->ep[0].ep.ep_list);
2655
2656 /* initially disable all non-ep0 endpoints */
2657 for (tmp = 1; tmp < 15; tmp++) {
2658 UDC_EP_RX_REG(tmp) = 0;
2659 UDC_EP_TX_REG(tmp) = 0;
2660 }
2661
2662 #define OMAP_BULK_EP(name,addr) \
2663 buf = omap_ep_setup(name "-bulk", addr, \
2664 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2665 #define OMAP_INT_EP(name,addr, maxp) \
2666 buf = omap_ep_setup(name "-int", addr, \
2667 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2668 #define OMAP_ISO_EP(name,addr, maxp) \
2669 buf = omap_ep_setup(name "-iso", addr, \
2670 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2671
2672 switch (fifo_mode) {
2673 case 0:
2674 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2675 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2676 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2677 break;
2678 case 1:
2679 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2680 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2681 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2682
2683 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2684 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2685 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2686
2687 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2688 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2689 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2690
2691 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2692 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2693 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2694
2695 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2696 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2697 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2698 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2699
2700 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2701 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2702 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2703 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2704
2705 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2706 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2707
2708 break;
2709
2710 #ifdef USE_ISO
2711 case 2: /* mixed iso/bulk */
2712 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2713 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2714 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2715 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2716
2717 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2718
2719 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2720 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2721 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2722 break;
2723 case 3: /* mixed bulk/iso */
2724 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2725 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2726 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2727
2728 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2729 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2730 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2731
2732 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2733 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2734 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2735 break;
2736 #endif
2737
2738 /* add more modes as needed */
2739
2740 default:
2741 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2742 return -ENODEV;
2743 }
2744 UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2745 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2746 return 0;
2747 }
2748
2749 static int __init omap_udc_probe(struct platform_device *pdev)
2750 {
2751 int status = -ENODEV;
2752 int hmc;
2753 struct otg_transceiver *xceiv = NULL;
2754 const char *type = NULL;
2755 struct omap_usb_config *config = pdev->dev.platform_data;
2756 struct clk *dc_clk;
2757 struct clk *hhc_clk;
2758
2759 /* NOTE: "knows" the order of the resources! */
2760 if (!request_mem_region(pdev->resource[0].start,
2761 pdev->resource[0].end - pdev->resource[0].start + 1,
2762 driver_name)) {
2763 DBG("request_mem_region failed\n");
2764 return -EBUSY;
2765 }
2766
2767 if (cpu_is_omap16xx()) {
2768 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2769 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2770 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2771 /* can't use omap_udc_enable_clock yet */
2772 clk_enable(dc_clk);
2773 clk_enable(hhc_clk);
2774 udelay(100);
2775 }
2776
2777 if (cpu_is_omap24xx()) {
2778 dc_clk = clk_get(&pdev->dev, "usb_fck");
2779 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2780 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2781 /* can't use omap_udc_enable_clock yet */
2782 clk_enable(dc_clk);
2783 clk_enable(hhc_clk);
2784 udelay(100);
2785 }
2786
2787 INFO("OMAP UDC rev %d.%d%s\n",
2788 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2789 config->otg ? ", Mini-AB" : "");
2790
2791 /* use the mode given to us by board init code */
2792 if (cpu_is_omap15xx()) {
2793 hmc = HMC_1510;
2794 type = "(unknown)";
2795
2796 if (machine_without_vbus_sense()) {
2797 /* just set up software VBUS detect, and then
2798 * later rig it so we always report VBUS.
2799 * FIXME without really sensing VBUS, we can't
2800 * know when to turn PULLUP_EN on/off; and that
2801 * means we always "need" the 48MHz clock.
2802 */
2803 u32 tmp = FUNC_MUX_CTRL_0_REG;
2804
2805 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2806 tmp |= VBUS_MODE_1510;
2807 tmp &= ~VBUS_CTRL_1510;
2808 FUNC_MUX_CTRL_0_REG = tmp;
2809 }
2810 } else {
2811 /* The transceiver may package some GPIO logic or handle
2812 * loopback and/or transceiverless setup; if we find one,
2813 * use it. Except for OTG, we don't _need_ to talk to one;
2814 * but not having one probably means no VBUS detection.
2815 */
2816 xceiv = otg_get_transceiver();
2817 if (xceiv)
2818 type = xceiv->label;
2819 else if (config->otg) {
2820 DBG("OTG requires external transceiver!\n");
2821 goto cleanup0;
2822 }
2823
2824 hmc = HMC_1610;
2825
2826 if (cpu_is_omap24xx()) {
2827 /* this could be transceiverless in one of the
2828 * "we don't need to know" modes.
2829 */
2830 type = "external";
2831 goto known;
2832 }
2833
2834 switch (hmc) {
2835 case 0: /* POWERUP DEFAULT == 0 */
2836 case 4:
2837 case 12:
2838 case 20:
2839 if (!cpu_is_omap1710()) {
2840 type = "integrated";
2841 break;
2842 }
2843 /* FALL THROUGH */
2844 case 3:
2845 case 11:
2846 case 16:
2847 case 19:
2848 case 25:
2849 if (!xceiv) {
2850 DBG("external transceiver not registered!\n");
2851 type = "unknown";
2852 }
2853 break;
2854 case 21: /* internal loopback */
2855 type = "loopback";
2856 break;
2857 case 14: /* transceiverless */
2858 if (cpu_is_omap1710())
2859 goto bad_on_1710;
2860 /* FALL THROUGH */
2861 case 13:
2862 case 15:
2863 type = "no";
2864 break;
2865
2866 default:
2867 bad_on_1710:
2868 ERR("unrecognized UDC HMC mode %d\n", hmc);
2869 goto cleanup0;
2870 }
2871 }
2872 known:
2873 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2874
2875 /* a "gadget" abstracts/virtualizes the controller */
2876 status = omap_udc_setup(pdev, xceiv);
2877 if (status) {
2878 goto cleanup0;
2879 }
2880 xceiv = NULL;
2881 // "udc" is now valid
2882 pullup_disable(udc);
2883 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2884 udc->gadget.is_otg = (config->otg != 0);
2885 #endif
2886
2887 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2888 if (UDC_REV_REG >= 0x61)
2889 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2890 else
2891 udc->clr_halt = UDC_RESET_EP;
2892
2893 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2894 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2895 IRQF_SAMPLE_RANDOM, driver_name, udc);
2896 if (status != 0) {
2897 ERR("can't get irq %d, err %d\n",
2898 (int) pdev->resource[1].start, status);
2899 goto cleanup1;
2900 }
2901
2902 /* USB "non-iso" IRQ (PIO for all but ep0) */
2903 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2904 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2905 if (status != 0) {
2906 ERR("can't get irq %d, err %d\n",
2907 (int) pdev->resource[2].start, status);
2908 goto cleanup2;
2909 }
2910 #ifdef USE_ISO
2911 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2912 IRQF_DISABLED, "omap_udc iso", udc);
2913 if (status != 0) {
2914 ERR("can't get irq %d, err %d\n",
2915 (int) pdev->resource[3].start, status);
2916 goto cleanup3;
2917 }
2918 #endif
2919 if (cpu_is_omap16xx()) {
2920 udc->dc_clk = dc_clk;
2921 udc->hhc_clk = hhc_clk;
2922 clk_disable(hhc_clk);
2923 clk_disable(dc_clk);
2924 }
2925
2926 if (cpu_is_omap24xx()) {
2927 udc->dc_clk = dc_clk;
2928 udc->hhc_clk = hhc_clk;
2929 /* FIXME OMAP2 don't release hhc & dc clock */
2930 #if 0
2931 clk_disable(hhc_clk);
2932 clk_disable(dc_clk);
2933 #endif
2934 }
2935
2936 create_proc_file();
2937 status = device_add(&udc->gadget.dev);
2938 if (!status)
2939 return status;
2940 /* If fail, fall through */
2941 #ifdef USE_ISO
2942 cleanup3:
2943 free_irq(pdev->resource[2].start, udc);
2944 #endif
2945
2946 cleanup2:
2947 free_irq(pdev->resource[1].start, udc);
2948
2949 cleanup1:
2950 kfree (udc);
2951 udc = NULL;
2952
2953 cleanup0:
2954 if (xceiv)
2955 put_device(xceiv->dev);
2956
2957 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2958 clk_disable(hhc_clk);
2959 clk_disable(dc_clk);
2960 clk_put(hhc_clk);
2961 clk_put(dc_clk);
2962 }
2963
2964 release_mem_region(pdev->resource[0].start,
2965 pdev->resource[0].end - pdev->resource[0].start + 1);
2966
2967 return status;
2968 }
2969
2970 static int __exit omap_udc_remove(struct platform_device *pdev)
2971 {
2972 DECLARE_COMPLETION_ONSTACK(done);
2973
2974 if (!udc)
2975 return -ENODEV;
2976 if (udc->driver)
2977 return -EBUSY;
2978
2979 udc->done = &done;
2980
2981 pullup_disable(udc);
2982 if (udc->transceiver) {
2983 put_device(udc->transceiver->dev);
2984 udc->transceiver = NULL;
2985 }
2986 UDC_SYSCON1_REG = 0;
2987
2988 remove_proc_file();
2989
2990 #ifdef USE_ISO
2991 free_irq(pdev->resource[3].start, udc);
2992 #endif
2993 free_irq(pdev->resource[2].start, udc);
2994 free_irq(pdev->resource[1].start, udc);
2995
2996 if (udc->dc_clk) {
2997 if (udc->clk_requested)
2998 omap_udc_enable_clock(0);
2999 clk_put(udc->hhc_clk);
3000 clk_put(udc->dc_clk);
3001 }
3002
3003 release_mem_region(pdev->resource[0].start,
3004 pdev->resource[0].end - pdev->resource[0].start + 1);
3005
3006 device_unregister(&udc->gadget.dev);
3007 wait_for_completion(&done);
3008
3009 return 0;
3010 }
3011
3012 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3013 * system is forced into deep sleep
3014 *
3015 * REVISIT we should probably reject suspend requests when there's a host
3016 * session active, rather than disconnecting, at least on boards that can
3017 * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to
3018 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3019 * may involve talking to an external transceiver (e.g. isp1301).
3020 */
3021
3022 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3023 {
3024 u32 devstat;
3025
3026 devstat = UDC_DEVSTAT_REG;
3027
3028 /* we're requesting 48 MHz clock if the pullup is enabled
3029 * (== we're attached to the host) and we're not suspended,
3030 * which would prevent entry to deep sleep...
3031 */
3032 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3033 WARN("session active; suspend requires disconnect\n");
3034 omap_pullup(&udc->gadget, 0);
3035 }
3036
3037 udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3038 udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3039 return 0;
3040 }
3041
3042 static int omap_udc_resume(struct platform_device *dev)
3043 {
3044 DBG("resume + wakeup/SRP\n");
3045 omap_pullup(&udc->gadget, 1);
3046
3047 /* maybe the host would enumerate us if we nudged it */
3048 msleep(100);
3049 return omap_wakeup(&udc->gadget);
3050 }
3051
3052 /*-------------------------------------------------------------------------*/
3053
3054 static struct platform_driver udc_driver = {
3055 .probe = omap_udc_probe,
3056 .remove = __exit_p(omap_udc_remove),
3057 .suspend = omap_udc_suspend,
3058 .resume = omap_udc_resume,
3059 .driver = {
3060 .owner = THIS_MODULE,
3061 .name = (char *) driver_name,
3062 },
3063 };
3064
3065 static int __init udc_init(void)
3066 {
3067 INFO("%s, version: " DRIVER_VERSION
3068 #ifdef USE_ISO
3069 " (iso)"
3070 #endif
3071 "%s\n", driver_desc,
3072 use_dma ? " (dma)" : "");
3073 return platform_driver_register(&udc_driver);
3074 }
3075 module_init(udc_init);
3076
3077 static void __exit udc_exit(void)
3078 {
3079 platform_driver_unregister(&udc_driver);
3080 }
3081 module_exit(udc_exit);
3082
3083 MODULE_DESCRIPTION(DRIVER_DESC);
3084 MODULE_LICENSE("GPL");
3085
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