drivers/video/vermilion/vermilion.h

   1 /*
   2  * Copyright (c) Intel Corp. 2007.
   3  * All Rights Reserved.
   4  *
   5  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   6  * develop this driver.
   7  *
   8  * This file is part of the Vermilion Range fb driver.
   9  * The Vermilion Range fb driver is free software;
  10  * you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * The Vermilion Range fb driver is distributed
  16  * in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this driver; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  24  *
  25  * Authors:
  26  *   Thomas Hellström <thomas-at-tungstengraphics-dot-com>
  27  */
  28
  29 #ifndef _VERMILION_H_
  30 #define _VERMILION_H_
  31
  32 #include <linux/kernel.h>
  33 #include <linux/version.h>
  34 #include <linux/pci.h>
  35 #include <asm/atomic.h>
  36 #include <linux/mutex.h>
  37
  38 #define VML_DEVICE_GPU 0x5002
  39 #define VML_DEVICE_VDC 0x5009
  40
  41 #define VML_VRAM_AREAS 3
  42 #define VML_MAX_XRES 1024
  43 #define VML_MAX_YRES 768
  44 #define VML_MAX_XRES_VIRTUAL 1040
  45
  46 /*
  47  * Display controller registers:
  48  */
  49
  50 /* Display controller 10-bit color representation */
  51
  52 #define VML_R_MASK                   0x3FF00000
  53 #define VML_R_SHIFT                  20
  54 #define VML_G_MASK                   0x000FFC00
  55 #define VML_G_SHIFT                  10
  56 #define VML_B_MASK                   0x000003FF
  57 #define VML_B_SHIFT                  0
  58
  59 /* Graphics plane control */
  60 #define VML_DSPCCNTR                 0x00072180
  61 #define VML_GFX_ENABLE               0x80000000
  62 #define VML_GFX_GAMMABYPASS          0x40000000
  63 #define VML_GFX_ARGB1555             0x0C000000
  64 #define VML_GFX_RGB0888              0x18000000
  65 #define VML_GFX_ARGB8888             0x1C000000
  66 #define VML_GFX_ALPHACONST           0x02000000
  67 #define VML_GFX_ALPHAMULT            0x01000000
  68 #define VML_GFX_CONST_ALPHA          0x000000FF
  69
  70 /* Graphics plane start address. Pixel aligned. */
  71 #define VML_DSPCADDR                 0x00072184
  72
  73 /* Graphics plane stride register. */
  74 #define VML_DSPCSTRIDE               0x00072188
  75
  76 /* Graphics plane position register. */
  77 #define VML_DSPCPOS                  0x0007218C
  78 #define VML_POS_YMASK                0x0FFF0000
  79 #define VML_POS_YSHIFT               16
  80 #define VML_POS_XMASK                0x00000FFF
  81 #define VML_POS_XSHIFT               0
  82
  83 /* Graphics plane height and width */
  84 #define VML_DSPCSIZE                 0x00072190
  85 #define VML_SIZE_HMASK               0x0FFF0000
  86 #define VML_SIZE_HSHIFT              16
  87 #define VML_SISE_WMASK               0x00000FFF
  88 #define VML_SIZE_WSHIFT              0
  89
  90 /* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
  91 #define VML_DSPCGAMLUT               0x00072200
  92
  93 /* Pixel video output configuration register */
  94 #define VML_PVOCONFIG                0x00061140
  95 #define VML_CONFIG_BASE              0x80000000
  96 #define VML_CONFIG_PIXEL_SWAP        0x04000000
  97 #define VML_CONFIG_DE_INV            0x01000000
  98 #define VML_CONFIG_HREF_INV          0x00400000
  99 #define VML_CONFIG_VREF_INV          0x00100000
 100 #define VML_CONFIG_CLK_INV           0x00040000
 101 #define VML_CONFIG_CLK_DIV2          0x00010000
 102 #define VML_CONFIG_ESTRB_INV         0x00008000
 103
 104 /* Pipe A Horizontal total register */
 105 #define VML_HTOTAL_A                 0x00060000
 106 #define VML_HTOTAL_MASK              0x1FFF0000
 107 #define VML_HTOTAL_SHIFT             16
 108 #define VML_HTOTAL_VAL               8192
 109 #define VML_HACTIVE_MASK             0x000007FF
 110 #define VML_HACTIVE_SHIFT            0
 111 #define VML_HACTIVE_VAL              4096
 112
 113 /* Pipe A Horizontal Blank register */
 114 #define VML_HBLANK_A                 0x00060004
 115 #define VML_HBLANK_END_MASK          0x1FFF0000
 116 #define VML_HBLANK_END_SHIFT         16
 117 #define VML_HBLANK_END_VAL           8192
 118 #define VML_HBLANK_START_MASK        0x00001FFF
 119 #define VML_HBLANK_START_SHIFT       0
 120 #define VML_HBLANK_START_VAL         8192
 121
 122 /* Pipe A Horizontal Sync register */
 123 #define VML_HSYNC_A                  0x00060008
 124 #define VML_HSYNC_END_MASK           0x1FFF0000
 125 #define VML_HSYNC_END_SHIFT          16
 126 #define VML_HSYNC_END_VAL            8192
 127 #define VML_HSYNC_START_MASK         0x00001FFF
 128 #define VML_HSYNC_START_SHIFT        0
 129 #define VML_HSYNC_START_VAL          8192
 130
 131 /* Pipe A Vertical total register */
 132 #define VML_VTOTAL_A                 0x0006000C
 133 #define VML_VTOTAL_MASK              0x1FFF0000
 134 #define VML_VTOTAL_SHIFT             16
 135 #define VML_VTOTAL_VAL               8192
 136 #define VML_VACTIVE_MASK             0x000007FF
 137 #define VML_VACTIVE_SHIFT            0
 138 #define VML_VACTIVE_VAL              4096
 139
 140 /* Pipe A Vertical Blank register */
 141 #define VML_VBLANK_A                 0x00060010
 142 #define VML_VBLANK_END_MASK          0x1FFF0000
 143 #define VML_VBLANK_END_SHIFT         16
 144 #define VML_VBLANK_END_VAL           8192
 145 #define VML_VBLANK_START_MASK        0x00001FFF
 146 #define VML_VBLANK_START_SHIFT       0
 147 #define VML_VBLANK_START_VAL         8192
 148
 149 /* Pipe A Vertical Sync register */
 150 #define VML_VSYNC_A                  0x00060014
 151 #define VML_VSYNC_END_MASK           0x1FFF0000
 152 #define VML_VSYNC_END_SHIFT          16
 153 #define VML_VSYNC_END_VAL            8192
 154 #define VML_VSYNC_START_MASK         0x00001FFF
 155 #define VML_VSYNC_START_SHIFT        0
 156 #define VML_VSYNC_START_VAL          8192
 157
 158 /* Pipe A Source Image size (minus one - equal to active size)
 159  * Programmable while pipe is enabled.
 160  */
 161 #define VML_PIPEASRC                 0x0006001C
 162 #define VML_PIPEASRC_HMASK           0x0FFF0000
 163 #define VML_PIPEASRC_HSHIFT          16
 164 #define VML_PIPEASRC_VMASK           0x00000FFF
 165 #define VML_PIPEASRC_VSHIFT          0
 166
 167 /* Pipe A Border Color Pattern register (10 bit color) */
 168 #define VML_BCLRPAT_A                0x00060020
 169
 170 /* Pipe A Canvas Color register  (10 bit color) */
 171 #define VML_CANVSCLR_A               0x00060024
 172
 173 /* Pipe A Configuration register */
 174 #define VML_PIPEACONF                0x00070008
 175 #define VML_PIPE_BASE                0x00000000
 176 #define VML_PIPE_ENABLE              0x80000000
 177 #define VML_PIPE_FORCE_BORDER        0x02000000
 178 #define VML_PIPE_PLANES_OFF          0x00080000
 179 #define VML_PIPE_ARGB_OUTPUT_MODE    0x00040000
 180
 181 /* Pipe A FIFO setting */
 182 #define VML_DSPARB                   0x00070030
 183 #define VML_FIFO_DEFAULT             0x00001D9C
 184
 185 /* MDVO rcomp status & pads control register */
 186 #define VML_RCOMPSTAT                0x00070048
 187 #define VML_MDVO_VDC_I_RCOMP         0x80000000
 188 #define VML_MDVO_POWERSAVE_OFF       0x00000008
 189 #define VML_MDVO_PAD_ENABLE          0x00000004
 190 #define VML_MDVO_PULLDOWN_ENABLE     0x00000001
 191
 192 struct vml_par {
 193         struct pci_dev *vdc;
 194         u64 vdc_mem_base;
 195         u64 vdc_mem_size;
 196         char __iomem *vdc_mem;
 197
 198         struct pci_dev *gpu;
 199         u64 gpu_mem_base;
 200         u64 gpu_mem_size;
 201         char __iomem *gpu_mem;
 202
 203         atomic_t refcount;
 204 };
 205
 206 struct vram_area {
 207         unsigned long logical;
 208         unsigned long phys;
 209         unsigned long size;
 210         unsigned order;
 211 };
 212
 213 struct vml_info {
 214         struct fb_info info;
 215         struct vml_par *par;
 216         struct list_head head;
 217         struct vram_area vram[VML_VRAM_AREAS];
 218         u64 vram_start;
 219         u64 vram_contig_size;
 220         u32 num_areas;
 221         void __iomem *vram_logical;
 222         u32 pseudo_palette[16];
 223         u32 stride;
 224         u32 bytes_per_pixel;
 225         atomic_t vmas;
 226         int cur_blank_mode;
 227         int pipe_disabled;
 228 };
 229
 230 /*
 231  * Subsystem
 232  */
 233
 234 struct vml_sys {
 235         char *name;
 236
 237         /*
 238          * Save / Restore;
 239          */
 240
 241         int (*save) (struct vml_sys * sys);
 242         int (*restore) (struct vml_sys * sys);
 243
 244         /*
 245          * PLL programming;
 246          */
 247
 248         int (*set_clock) (struct vml_sys * sys, int clock);
 249         int (*nearest_clock) (const struct vml_sys * sys, int clock);
 250 };
 251
 252 extern int vmlfb_register_subsys(struct vml_sys *sys);
 253 extern void vmlfb_unregister_subsys(struct vml_sys *sys);
 254
 255 #define VML_READ32(_par, _offset) \
 256         (ioread32((_par)->vdc_mem + (_offset)))
 257 #define VML_WRITE32(_par, _offset, _value)                              \
 258         iowrite32(_value, (_par)->vdc_mem + (_offset))
 259
 260 #endif