raid5: fix unending write sequence
[pv_ops_mirror.git] / include / asm-parisc / tlb.h
blob33107a248e1f76b991129adeaa30d69bcd4d4f1d
1 #ifndef _PARISC_TLB_H
2 #define _PARISC_TLB_H
4 #define tlb_flush(tlb) \
5 do { if ((tlb)->fullmm) \
6 flush_tlb_mm((tlb)->mm);\
7 } while (0)
9 #define tlb_start_vma(tlb, vma) \
10 do { if (!(tlb)->fullmm) \
11 flush_cache_range(vma, vma->vm_start, vma->vm_end); \
12 } while (0)
14 #define tlb_end_vma(tlb, vma) \
15 do { if (!(tlb)->fullmm) \
16 flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
17 } while (0)
19 #define __tlb_remove_tlb_entry(tlb, pte, address) \
20 do { } while (0)
22 #include <asm-generic/tlb.h>
24 #define __pmd_free_tlb(tlb, pmd) pmd_free(pmd)
25 #define __pte_free_tlb(tlb, pte) pte_free(pte)
27 #endif