2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/kallsyms.h>
27 /* The Mellanox Tavor device gives false positive parity errors
28 * Mark this device with a broken_parity_status, to allow
29 * PCI scanning code to "skip" this now blacklisted device.
31 static void __devinit
quirk_mellanox_tavor(struct pci_dev
*dev
)
33 dev
->broken_parity_status
= 1; /* This device gives false positives */
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR
,quirk_mellanox_tavor
);
36 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
,quirk_mellanox_tavor
);
38 /* Deal with broken BIOS'es that neglect to enable passive release,
39 which can cause problems in combination with the 82441FX/PPro MTRRs */
40 static void quirk_passive_release(struct pci_dev
*dev
)
42 struct pci_dev
*d
= NULL
;
45 /* We have to make sure a particular bit is set in the PIIX3
46 ISA bridge, so we have to go out and find it. */
47 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
48 pci_read_config_byte(d
, 0x82, &dlc
);
50 dev_err(&d
->dev
, "PIIX3: Enabling Passive Release\n");
52 pci_write_config_byte(d
, 0x82, dlc
);
56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
57 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
59 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
60 but VIA don't answer queries. If you happen to have good contacts at VIA
61 ask them for me please -- Alan
63 This appears to be BIOS not version dependent. So presumably there is a
65 int isa_dma_bridge_buggy
;
66 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
68 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
70 if (!isa_dma_bridge_buggy
) {
71 isa_dma_bridge_buggy
=1;
72 dev_info(&dev
->dev
, "Activating ISA DMA hang workarounds\n");
76 * Its not totally clear which chipsets are the problematic ones
77 * We know 82C586 and 82C596 variants are affected.
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
85 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
88 EXPORT_SYMBOL(pci_pci_problems
);
91 * Chipsets where PCI->PCI transfers vanish or hang
93 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
95 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
96 dev_info(&dev
->dev
, "Disabling direct PCI/PCI transfers\n");
97 pci_pci_problems
|= PCIPCI_FAIL
;
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
103 static void __devinit
quirk_nopciamd(struct pci_dev
*dev
)
106 pci_read_config_byte(dev
, 0x08, &rev
);
109 dev_info(&dev
->dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
110 pci_pci_problems
|= PCIAGP_FAIL
;
113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
116 * Triton requires workarounds to be used by the drivers
118 static void __devinit
quirk_triton(struct pci_dev
*dev
)
120 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
121 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
122 pci_pci_problems
|= PCIPCI_TRITON
;
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
131 * VIA Apollo KT133 needs PCI latency patch
132 * Made according to a windows driver based patch by George E. Breese
133 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
134 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
135 * the info on which Mr Breese based his work.
137 * Updated based on further information from the site and also on
138 * information provided by VIA
140 static void quirk_vialatency(struct pci_dev
*dev
)
144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */
147 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
150 /* Check for buggy part revisions */
151 if (p
->revision
< 0x40 || p
->revision
> 0x42)
154 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
155 if (p
==NULL
) /* No problem parts */
157 /* Check for buggy part revisions */
158 if (p
->revision
< 0x10 || p
->revision
> 0x12)
163 * Ok we have the problem. Now set the PCI master grant to
164 * occur every master grant. The apparent bug is that under high
165 * PCI load (quite common in Linux of course) you can get data
166 * loss when the CPU is held off the bus for 3 bus master requests
167 * This happens to include the IDE controllers....
169 * VIA only apply this fix when an SB Live! is present but under
170 * both Linux and Windows this isnt enough, and we have seen
171 * corruption without SB Live! but with things like 3 UDMA IDE
172 * controllers. So we ignore that bit of the VIA recommendation..
175 pci_read_config_byte(dev
, 0x76, &busarb
);
176 /* Set bit 4 and bi 5 of byte 76 to 0x01
177 "Master priority rotation on every PCI master grant */
180 pci_write_config_byte(dev
, 0x76, busarb
);
181 dev_info(&dev
->dev
, "Applying VIA southbridge workaround\n");
185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
188 /* Must restore this on a resume from RAM */
189 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
190 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
191 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
194 * VIA Apollo VP3 needs ETBF on BT848/878
196 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
198 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
199 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
200 pci_pci_problems
|= PCIPCI_VIAETBF
;
203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
205 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
207 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
208 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
209 pci_pci_problems
|= PCIPCI_VSFX
;
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
215 * Ali Magik requires workarounds to be used by the drivers
216 * that DMA to AGP space. Latency must be set to 0xA and triton
217 * workaround applied too
218 * [Info kindly provided by ALi]
220 static void __init
quirk_alimagik(struct pci_dev
*dev
)
222 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
223 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
224 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
231 * Natoma has some interesting boundary conditions with Zoran stuff
234 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
236 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
237 dev_info(&dev
->dev
, "Limiting direct PCI/PCI transfers\n");
238 pci_pci_problems
|= PCIPCI_NATOMA
;
241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
249 * This chip can cause PCI parity errors if config register 0xA0 is read
250 * while DMAs are occurring.
252 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
254 dev
->cfg_size
= 0xA0;
256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
259 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
260 * If it's needed, re-allocate the region.
262 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
264 struct resource
*r
= &dev
->resource
[0];
266 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
274 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
275 unsigned size
, int nr
, const char *name
)
279 struct pci_bus_region bus_region
;
280 struct resource
*res
= dev
->resource
+ nr
;
282 res
->name
= pci_name(dev
);
284 res
->end
= region
+ size
- 1;
285 res
->flags
= IORESOURCE_IO
;
287 /* Convert from PCI bus to resource space. */
288 bus_region
.start
= res
->start
;
289 bus_region
.end
= res
->end
;
290 pcibios_bus_to_resource(dev
, res
, &bus_region
);
292 pci_claim_resource(dev
, nr
);
293 dev_info(&dev
->dev
, "quirk: region %04x-%04x claimed by %s\n", region
, region
+ size
- 1, name
);
298 * ATI Northbridge setups MCE the processor if you even
299 * read somewhere between 0x3b0->0x3bb or read 0x3d3
301 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
303 dev_info(&dev
->dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
304 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
305 request_region(0x3b0, 0x0C, "RadeonIGP");
306 request_region(0x3d3, 0x01, "RadeonIGP");
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
311 * Let's make the southbridge information explicit instead
312 * of having to worry about people probing the ACPI areas,
313 * for example.. (Yes, it happens, and if you read the wrong
314 * ACPI register it will put the machine to sleep with no
315 * way of waking it up again. Bummer).
317 * ALI M7101: Two IO regions pointed to by words at
318 * 0xE0 (64 bytes of ACPI registers)
319 * 0xE2 (32 bytes of SMB registers)
321 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
325 pci_read_config_word(dev
, 0xE0, ®ion
);
326 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
327 pci_read_config_word(dev
, 0xE2, ®ion
);
328 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
332 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
335 u32 mask
, size
, base
;
337 pci_read_config_dword(dev
, port
, &devres
);
338 if ((devres
& enable
) != enable
)
340 mask
= (devres
>> 16) & 15;
341 base
= devres
& 0xffff;
344 unsigned bit
= size
>> 1;
345 if ((bit
& mask
) == bit
)
350 * For now we only print it out. Eventually we'll want to
351 * reserve it (at least if it's in the 0x1000+ range), but
352 * let's get enough confirmation reports first.
355 dev_info(&dev
->dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
358 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
361 u32 mask
, size
, base
;
363 pci_read_config_dword(dev
, port
, &devres
);
364 if ((devres
& enable
) != enable
)
366 base
= devres
& 0xffff0000;
367 mask
= (devres
& 0x3f) << 16;
370 unsigned bit
= size
>> 1;
371 if ((bit
& mask
) == bit
)
376 * For now we only print it out. Eventually we'll want to
377 * reserve it, but let's get enough confirmation reports first.
380 dev_info(&dev
->dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
384 * PIIX4 ACPI: Two IO regions pointed to by longwords at
385 * 0x40 (64 bytes of ACPI registers)
386 * 0x90 (16 bytes of SMB registers)
387 * and a few strange programmable PIIX4 device resources.
389 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
393 pci_read_config_dword(dev
, 0x40, ®ion
);
394 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
395 pci_read_config_dword(dev
, 0x90, ®ion
);
396 quirk_io_region(dev
, region
, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
398 /* Device resource A has enables for some of the other ones */
399 pci_read_config_dword(dev
, 0x5c, &res_a
);
401 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
402 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
404 /* Device resource D is just bitfields for static resources */
406 /* Device 12 enabled? */
407 if (res_a
& (1 << 29)) {
408 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
409 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
411 /* Device 13 enabled? */
412 if (res_a
& (1 << 30)) {
413 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
414 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
416 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
417 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
423 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
424 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
425 * 0x58 (64 bytes of GPIO I/O space)
427 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
431 pci_read_config_dword(dev
, 0x40, ®ion
);
432 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH4 ACPI/GPIO/TCO");
434 pci_read_config_dword(dev
, 0x58, ®ion
);
435 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH4 GPIO");
437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
448 static void __devinit
quirk_ich6_lpc_acpi(struct pci_dev
*dev
)
452 pci_read_config_dword(dev
, 0x40, ®ion
);
453 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH6 ACPI/GPIO/TCO");
455 pci_read_config_dword(dev
, 0x48, ®ion
);
456 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH6 GPIO");
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc_acpi
);
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc_acpi
);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich6_lpc_acpi
);
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich6_lpc_acpi
);
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich6_lpc_acpi
);
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich6_lpc_acpi
);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich6_lpc_acpi
);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich6_lpc_acpi
);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich6_lpc_acpi
);
467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich6_lpc_acpi
);
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich6_lpc_acpi
);
469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich6_lpc_acpi
);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich6_lpc_acpi
);
471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich6_lpc_acpi
);
474 * VIA ACPI: One IO region pointed to by longword at
475 * 0x48 or 0x20 (256 bytes of ACPI registers)
477 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
481 if (dev
->revision
& 0x10) {
482 pci_read_config_dword(dev
, 0x48, ®ion
);
483 region
&= PCI_BASE_ADDRESS_IO_MASK
;
484 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
490 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
491 * 0x48 (256 bytes of ACPI registers)
492 * 0x70 (128 bytes of hardware monitoring register)
493 * 0x90 (16 bytes of SMB registers)
495 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
500 quirk_vt82c586_acpi(dev
);
502 pci_read_config_word(dev
, 0x70, &hm
);
503 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
504 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c686 HW-mon");
506 pci_read_config_dword(dev
, 0x90, &smb
);
507 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
508 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c686 SMB");
510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
513 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
514 * 0x88 (128 bytes of power management registers)
515 * 0xd0 (16 bytes of SMB registers)
517 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
521 pci_read_config_word(dev
, 0x88, &pm
);
522 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
523 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
525 pci_read_config_word(dev
, 0xd0, &smb
);
526 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
527 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
532 #ifdef CONFIG_X86_IO_APIC
534 #include <asm/io_apic.h>
537 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
538 * devices to the external APIC.
540 * TODO: When we have device-specific interrupt routers,
541 * this code will go away from quirks.
543 static void quirk_via_ioapic(struct pci_dev
*dev
)
548 tmp
= 0; /* nothing routed to external APIC */
550 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
552 dev_info(&dev
->dev
, "%sbling VIA external APIC routing\n",
553 tmp
== 0 ? "Disa" : "Ena");
555 /* Offset 0x58: External APIC IRQ output control */
556 pci_write_config_byte (dev
, 0x58, tmp
);
558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
559 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
562 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
563 * This leads to doubled level interrupt rates.
564 * Set this bit to get rid of cycle wastage.
565 * Otherwise uncritical.
567 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
570 #define BYPASS_APIC_DEASSERT 8
572 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
573 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
574 dev_info(&dev
->dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
575 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
579 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
582 * The AMD io apic can hang the box when an apic irq is masked.
583 * We check all revs >= B0 (yet not in the pre production!) as the bug
584 * is currently marked NoFix
586 * We have multiple reports of hangs with this chipset that went away with
587 * noapic specified. For the moment we assume it's the erratum. We may be wrong
588 * of course. However the advice is demonstrably good even if so..
590 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
592 if (dev
->revision
>= 0x02) {
593 dev_warn(&dev
->dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
594 dev_warn(&dev
->dev
, " : booting with the \"noapic\" option\n");
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
599 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
601 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
606 #define AMD8131_revA0 0x01
607 #define AMD8131_revB0 0x11
608 #define AMD8131_MISC 0x40
609 #define AMD8131_NIOAMODE_BIT 0
610 static void quirk_amd_8131_ioapic(struct pci_dev
*dev
)
617 if (dev
->revision
== AMD8131_revA0
|| dev
->revision
== AMD8131_revB0
) {
618 dev_info(&dev
->dev
, "Fixing up AMD8131 IOAPIC mode\n");
619 pci_read_config_byte( dev
, AMD8131_MISC
, &tmp
);
620 tmp
&= ~(1 << AMD8131_NIOAMODE_BIT
);
621 pci_write_config_byte( dev
, AMD8131_MISC
, tmp
);
624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
625 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
626 #endif /* CONFIG_X86_IO_APIC */
629 * Some settings of MMRBC can lead to data corruption so block changes.
630 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
632 static void __init
quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
634 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
635 dev_info(&dev
->dev
, "AMD8131 rev %x detected; "
636 "disabling PCI-X MMRBC\n", dev
->revision
);
637 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
643 * FIXME: it is questionable that quirk_via_acpi
644 * is needed. It shows up as an ISA bridge, and does not
645 * support the PCI_INTERRUPT_LINE register at all. Therefore
646 * it seems like setting the pci_dev's 'irq' to the
647 * value of the ACPI SCI interrupt is only done for convenience.
650 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
653 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
656 pci_read_config_byte(d
, 0x42, &irq
);
658 if (irq
&& (irq
!= 2))
661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
662 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
666 * VIA bridges which have VLink
669 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
671 static void quirk_via_bridge(struct pci_dev
*dev
)
673 /* See what bridge we have and find the device ranges */
674 switch (dev
->device
) {
675 case PCI_DEVICE_ID_VIA_82C686
:
676 /* The VT82C686 is special, it attaches to PCI and can have
677 any device number. All its subdevices are functions of
678 that single device. */
679 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
680 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
682 case PCI_DEVICE_ID_VIA_8237
:
683 case PCI_DEVICE_ID_VIA_8237A
:
684 via_vlink_dev_lo
= 15;
686 case PCI_DEVICE_ID_VIA_8235
:
687 via_vlink_dev_lo
= 16;
689 case PCI_DEVICE_ID_VIA_8231
:
690 case PCI_DEVICE_ID_VIA_8233_0
:
691 case PCI_DEVICE_ID_VIA_8233A
:
692 case PCI_DEVICE_ID_VIA_8233C_0
:
693 via_vlink_dev_lo
= 17;
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
707 * quirk_via_vlink - VIA VLink IRQ number update
710 * If the device we are dealing with is on a PIC IRQ we need to
711 * ensure that the IRQ line register which usually is not relevant
712 * for PCI cards, is actually written so that interrupts get sent
713 * to the right place.
714 * We only do this on systems where a VIA south bridge was detected,
715 * and only for VIA devices on the motherboard (see quirk_via_bridge
719 static void quirk_via_vlink(struct pci_dev
*dev
)
723 /* Check if we have VLink at all */
724 if (via_vlink_dev_lo
== -1)
729 /* Don't quirk interrupts outside the legacy IRQ range */
730 if (!new_irq
|| new_irq
> 15)
733 /* Internal device ? */
734 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
735 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
738 /* This is an internal VLink device on a PIC interrupt. The BIOS
739 ought to have set this but may not have, so we redo it */
741 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
742 if (new_irq
!= irq
) {
743 dev_info(&dev
->dev
, "VIA VLink IRQ fixup, from %d to %d\n",
745 udelay(15); /* unknown if delay really needed */
746 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
749 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
752 * VIA VT82C598 has its device ID settable and many BIOSes
753 * set it to the ID of VT82C597 for backward compatibility.
754 * We need to switch it off to be able to recognize the real
757 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
759 pci_write_config_byte(dev
, 0xfc, 0);
760 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
765 * CardBus controllers have a legacy base address that enables them
766 * to respond as i82365 pcmcia controllers. We don't want them to
767 * do this even if the Linux CardBus driver is not loaded, because
768 * the Linux i82365 driver does not (and should not) handle CardBus.
770 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
772 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
774 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
776 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
777 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
780 * Following the PCI ordering rules is optional on the AMD762. I'm not
781 * sure what the designers were smoking but let's not inhale...
783 * To be fair to AMD, it follows the spec by default, its BIOS people
786 static void quirk_amd_ordering(struct pci_dev
*dev
)
789 pci_read_config_dword(dev
, 0x4C, &pcic
);
792 dev_warn(&dev
->dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
793 pci_write_config_dword(dev
, 0x4C, pcic
);
794 pci_read_config_dword(dev
, 0x84, &pcic
);
795 pcic
|= (1<<23); /* Required in this mode */
796 pci_write_config_dword(dev
, 0x84, pcic
);
799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
800 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
803 * DreamWorks provided workaround for Dunord I-3000 problem
805 * This card decodes and responds to addresses not apparently
806 * assigned to it. We force a larger allocation to ensure that
807 * nothing gets put too close to it.
809 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
811 struct resource
*r
= &dev
->resource
[1];
815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
818 * i82380FB mobile docking controller: its PCI-to-PCI bridge
819 * is subtractive decoding (transparent), and does indicate this
820 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
823 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
825 dev
->transparent
= 1;
827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
831 * Common misconfiguration of the MediaGX/Geode PCI master that will
832 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
833 * datasheets found at http://www.national.com/ds/GX for info on what
834 * these bits do. <christer@weinigel.se>
836 static void quirk_mediagx_master(struct pci_dev
*dev
)
839 pci_read_config_byte(dev
, 0x41, ®
);
842 dev_info(&dev
->dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
843 pci_write_config_byte(dev
, 0x41, reg
);
846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
847 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
850 * Ensure C0 rev restreaming is off. This is normally done by
851 * the BIOS but in the odd case it is not the results are corruption
852 * hence the presence of a Linux check
854 static void quirk_disable_pxb(struct pci_dev
*pdev
)
858 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
860 pci_read_config_word(pdev
, 0x40, &config
);
861 if (config
& (1<<6)) {
863 pci_write_config_word(pdev
, 0x40, config
);
864 dev_info(&pdev
->dev
, "C0 revision 450NX. Disabling PCI restreaming\n");
867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
868 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
870 static void __devinit
quirk_amd_ide_mode(struct pci_dev
*pdev
)
872 /* set sb600/sb700/sb800 sata to ahci mode */
875 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
877 pci_read_config_byte(pdev
, 0x40, &tmp
);
878 pci_write_config_byte(pdev
, 0x40, tmp
|1);
879 pci_write_config_byte(pdev
, 0x9, 1);
880 pci_write_config_byte(pdev
, 0xa, 6);
881 pci_write_config_byte(pdev
, 0x40, tmp
);
883 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
884 dev_info(&pdev
->dev
, "set SATA to AHCI mode\n");
887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
888 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
890 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
893 * Serverworks CSB5 IDE does not fully support native mode
895 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
898 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
902 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
903 /* PCI layer will sort out resources */
906 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
909 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
911 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
915 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
917 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
918 dev_info(&pdev
->dev
, "IDE mode mismatch; forcing legacy mode\n");
921 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
924 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
926 /* This was originally an Alpha specific thing, but it really fits here.
927 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
929 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
931 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
937 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
938 * is not activated. The myth is that Asus said that they do not want the
939 * users to be irritated by just another PCI Device in the Win98 device
940 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
941 * package 2.7.0 for details)
943 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
944 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
945 * becomes necessary to do this tweak in two steps -- the chosen trigger
946 * is either the Host bridge (preferred) or on-board VGA controller.
948 * Note that we used to unhide the SMBus that way on Toshiba laptops
949 * (Satellite A40 and Tecra M2) but then found that the thermal management
950 * was done by SMM code, which could cause unsynchronized concurrent
951 * accesses to the SMBus registers, with potentially bad effects. Thus you
952 * should be very careful when adding new entries: if SMM is accessing the
953 * Intel SMBus, this is a very good reason to leave it hidden.
955 static int asus_hides_smbus
;
957 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
959 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
960 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
961 switch(dev
->subsystem_device
) {
962 case 0x8025: /* P4B-LX */
963 case 0x8070: /* P4B */
964 case 0x8088: /* P4B533 */
965 case 0x1626: /* L3C notebook */
966 asus_hides_smbus
= 1;
968 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
969 switch(dev
->subsystem_device
) {
970 case 0x80b1: /* P4GE-V */
971 case 0x80b2: /* P4PE */
972 case 0x8093: /* P4B533-V */
973 asus_hides_smbus
= 1;
975 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
976 switch(dev
->subsystem_device
) {
977 case 0x8030: /* P4T533 */
978 asus_hides_smbus
= 1;
980 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
981 switch (dev
->subsystem_device
) {
982 case 0x8070: /* P4G8X Deluxe */
983 asus_hides_smbus
= 1;
985 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
986 switch (dev
->subsystem_device
) {
987 case 0x80c9: /* PU-DLS */
988 asus_hides_smbus
= 1;
990 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
991 switch (dev
->subsystem_device
) {
992 case 0x1751: /* M2N notebook */
993 case 0x1821: /* M5N notebook */
994 asus_hides_smbus
= 1;
996 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
997 switch (dev
->subsystem_device
) {
998 case 0x184b: /* W1N notebook */
999 case 0x186a: /* M6Ne notebook */
1000 asus_hides_smbus
= 1;
1002 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1003 switch (dev
->subsystem_device
) {
1004 case 0x80f2: /* P4P800-X */
1005 asus_hides_smbus
= 1;
1007 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1008 switch (dev
->subsystem_device
) {
1009 case 0x1882: /* M6V notebook */
1010 case 0x1977: /* A6VA notebook */
1011 asus_hides_smbus
= 1;
1013 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1014 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1015 switch(dev
->subsystem_device
) {
1016 case 0x088C: /* HP Compaq nc8000 */
1017 case 0x0890: /* HP Compaq nc6000 */
1018 asus_hides_smbus
= 1;
1020 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1021 switch (dev
->subsystem_device
) {
1022 case 0x12bc: /* HP D330L */
1023 case 0x12bd: /* HP D530 */
1024 asus_hides_smbus
= 1;
1026 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1027 switch (dev
->subsystem_device
) {
1028 case 0x12bf: /* HP xw4100 */
1029 asus_hides_smbus
= 1;
1031 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1032 switch (dev
->subsystem_device
) {
1033 case 0x099c: /* HP Compaq nx6110 */
1034 asus_hides_smbus
= 1;
1036 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1037 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1038 switch(dev
->subsystem_device
) {
1039 case 0xC00C: /* Samsung P35 notebook */
1040 asus_hides_smbus
= 1;
1042 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1043 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1044 switch(dev
->subsystem_device
) {
1045 case 0x0058: /* Compaq Evo N620c */
1046 asus_hides_smbus
= 1;
1048 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1049 switch(dev
->subsystem_device
) {
1050 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1051 /* Motherboard doesn't have Host bridge
1052 * subvendor/subdevice IDs, therefore checking
1053 * its on-board VGA controller */
1054 asus_hides_smbus
= 1;
1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1071 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1075 if (likely(!asus_hides_smbus
))
1078 pci_read_config_word(dev
, 0xF2, &val
);
1080 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1081 pci_read_config_word(dev
, 0xF2, &val
);
1083 dev_info(&dev
->dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
1085 dev_info(&dev
->dev
, "Enabled i801 SMBus device\n");
1088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1095 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1096 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1097 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1098 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1099 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1100 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1101 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1103 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1108 if (likely(!asus_hides_smbus
))
1110 pci_read_config_dword(dev
, 0xF0, &rcba
);
1111 base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1112 if (base
== NULL
) return;
1113 val
=readl(base
+ 0x3418); /* read the Function Disable register, dword mode only */
1114 writel(val
& 0xFFFFFFF7, base
+ 0x3418); /* enable the SMBus device */
1116 dev_info(&dev
->dev
, "Enabled ICH6/i801 SMBus device\n");
1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1119 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1122 * SiS 96x south bridge: BIOS typically hides SMBus device...
1124 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1127 pci_read_config_byte(dev
, 0x77, &val
);
1129 dev_info(&dev
->dev
, "Enabling SiS 96x SMBus\n");
1130 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1137 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1138 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1139 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1140 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1143 * ... This is further complicated by the fact that some SiS96x south
1144 * bridges pretend to be 85C503/5513 instead. In that case see if we
1145 * spotted a compatible north bridge to make sure.
1146 * (pci_find_device doesn't work yet)
1148 * We can also enable the sis96x bit in the discovery register..
1150 #define SIS_DETECT_REGISTER 0x40
1152 static void quirk_sis_503(struct pci_dev
*dev
)
1157 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1158 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1159 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1160 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1161 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1166 * Ok, it now shows up as a 96x.. run the 96x quirk by
1167 * hand in case it has already been processed.
1168 * (depends on link order, which is apparently not guaranteed)
1170 dev
->device
= devid
;
1171 quirk_sis_96x_smbus(dev
);
1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1174 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1178 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1179 * and MC97 modem controller are disabled when a second PCI soundcard is
1180 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1183 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1186 int asus_hides_ac97
= 0;
1188 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1189 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1190 asus_hides_ac97
= 1;
1193 if (!asus_hides_ac97
)
1196 pci_read_config_byte(dev
, 0x50, &val
);
1198 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1199 pci_read_config_byte(dev
, 0x50, &val
);
1201 dev_info(&dev
->dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val
);
1203 dev_info(&dev
->dev
, "Enabled onboard AC97/MC97 devices\n");
1206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1207 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1209 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1212 * If we are using libata we can drive this chip properly but must
1213 * do this early on to make the additional device appear during
1216 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1218 u32 conf1
, conf5
, class;
1221 /* Only poke fn 0 */
1222 if (PCI_FUNC(pdev
->devfn
))
1225 pci_read_config_dword(pdev
, 0x40, &conf1
);
1226 pci_read_config_dword(pdev
, 0x80, &conf5
);
1228 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1229 conf5
&= ~(1 << 24); /* Clear bit 24 */
1231 switch (pdev
->device
) {
1232 case PCI_DEVICE_ID_JMICRON_JMB360
:
1233 /* The controller should be in single function ahci mode */
1234 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1237 case PCI_DEVICE_ID_JMICRON_JMB365
:
1238 case PCI_DEVICE_ID_JMICRON_JMB366
:
1239 /* Redirect IDE second PATA port to the right spot */
1242 case PCI_DEVICE_ID_JMICRON_JMB361
:
1243 case PCI_DEVICE_ID_JMICRON_JMB363
:
1244 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1245 /* Set the class codes correctly and then direct IDE 0 */
1246 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1249 case PCI_DEVICE_ID_JMICRON_JMB368
:
1250 /* The controller should be in single function IDE mode */
1251 conf1
|= 0x00C00000; /* Set 22, 23 */
1255 pci_write_config_dword(pdev
, 0x40, conf1
);
1256 pci_write_config_dword(pdev
, 0x80, conf5
);
1258 /* Update pdev accordingly */
1259 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1260 pdev
->hdr_type
= hdr
& 0x7f;
1261 pdev
->multifunction
= !!(hdr
& 0x80);
1263 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1264 pdev
->class = class >> 8;
1266 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1267 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1268 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1269 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1270 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1271 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1272 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1273 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1274 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1275 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1276 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1277 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1281 #ifdef CONFIG_X86_IO_APIC
1282 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1286 if ((pdev
->class >> 8) != 0xff00)
1289 /* the first BAR is the location of the IO APIC...we must
1290 * not touch this (and it's already covered by the fixmap), so
1291 * forcibly insert it into the resource tree */
1292 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1293 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1295 /* The next five BARs all seem to be rubbish, so just clean
1297 for (i
=1; i
< 6; i
++) {
1298 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1306 EXPORT_SYMBOL(pcie_mch_quirk
);
1308 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1314 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1318 * It's possible for the MSI to get corrupted if shpc and acpi
1319 * are used together on certain PXH-based systems.
1321 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1325 dev_warn(&dev
->dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1327 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1328 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1329 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1330 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1331 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1334 * Some Intel PCI Express chipsets have trouble with downstream
1335 * device power management.
1337 static void quirk_intel_pcie_pm(struct pci_dev
* dev
)
1339 pci_pm_d3_delay
= 120;
1343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1351 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1352 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1353 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1354 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1366 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1367 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1368 * Re-allocate the region if needed...
1370 static void __init
quirk_tc86c001_ide(struct pci_dev
*dev
)
1372 struct resource
*r
= &dev
->resource
[0];
1374 if (r
->start
& 0x8) {
1379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
1380 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
1381 quirk_tc86c001_ide
);
1383 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1385 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1386 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1389 * These Netmos parts are multiport serial devices with optional
1390 * parallel ports. Even when parallel ports are present, they
1391 * are identified as class SERIAL, which means the serial driver
1392 * will claim them. To prevent this, mark them as class OTHER.
1393 * These combo devices should be claimed by parport_serial.
1395 * The subdevice ID is of the form 0x00PS, where <P> is the number
1396 * of parallel ports and <S> is the number of serial ports.
1398 switch (dev
->device
) {
1399 case PCI_DEVICE_ID_NETMOS_9735
:
1400 case PCI_DEVICE_ID_NETMOS_9745
:
1401 case PCI_DEVICE_ID_NETMOS_9835
:
1402 case PCI_DEVICE_ID_NETMOS_9845
:
1403 case PCI_DEVICE_ID_NETMOS_9855
:
1404 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1406 dev_info(&dev
->dev
, "Netmos %04x (%u parallel, "
1407 "%u serial); changing class SERIAL to OTHER "
1408 "(use parport_serial)\n",
1409 dev
->device
, num_parallel
, num_serial
);
1410 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1411 (dev
->class & 0xff);
1415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1417 static void __devinit
quirk_e100_interrupt(struct pci_dev
*dev
)
1424 switch (dev
->device
) {
1425 /* PCI IDs taken from drivers/net/e100.c */
1427 case 0x1030 ... 0x1034:
1428 case 0x1038 ... 0x103E:
1429 case 0x1050 ... 0x1057:
1431 case 0x1064 ... 0x106B:
1432 case 0x1091 ... 0x1095:
1445 * Some firmware hands off the e100 with interrupts enabled,
1446 * which can cause a flood of interrupts if packets are
1447 * received before the driver attaches to the device. So
1448 * disable all e100 interrupts here. The driver will
1449 * re-enable them when it's ready.
1451 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1453 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
1457 * Check that the device is in the D0 power state. If it's not,
1458 * there is no point to look any further.
1460 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1462 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
1463 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
1467 /* Convert from PCI bus to resource space. */
1468 csr
= ioremap(pci_resource_start(dev
, 0), 8);
1470 dev_warn(&dev
->dev
, "Can't map e100 registers\n");
1474 cmd_hi
= readb(csr
+ 3);
1476 dev_warn(&dev
->dev
, "Firmware left e100 interrupts enabled; "
1483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_e100_interrupt
);
1485 static void __devinit
fixup_rev1_53c810(struct pci_dev
* dev
)
1487 /* rev 1 ncr53c810 chips don't set the class at all which means
1488 * they don't get their resources remapped. Fix that here.
1491 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1492 dev_info(&dev
->dev
, "NCR 53c810 rev 1 detected; setting PCI class\n");
1493 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1498 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
, struct pci_fixup
*end
)
1501 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
1502 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
1504 dev_dbg(&dev
->dev
, "calling quirk 0x%p", f
->hook
);
1505 print_fn_descriptor_symbol(": %s()\n",
1506 (unsigned long) f
->hook
);
1514 extern struct pci_fixup __start_pci_fixups_early
[];
1515 extern struct pci_fixup __end_pci_fixups_early
[];
1516 extern struct pci_fixup __start_pci_fixups_header
[];
1517 extern struct pci_fixup __end_pci_fixups_header
[];
1518 extern struct pci_fixup __start_pci_fixups_final
[];
1519 extern struct pci_fixup __end_pci_fixups_final
[];
1520 extern struct pci_fixup __start_pci_fixups_enable
[];
1521 extern struct pci_fixup __end_pci_fixups_enable
[];
1522 extern struct pci_fixup __start_pci_fixups_resume
[];
1523 extern struct pci_fixup __end_pci_fixups_resume
[];
1526 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
1528 struct pci_fixup
*start
, *end
;
1531 case pci_fixup_early
:
1532 start
= __start_pci_fixups_early
;
1533 end
= __end_pci_fixups_early
;
1536 case pci_fixup_header
:
1537 start
= __start_pci_fixups_header
;
1538 end
= __end_pci_fixups_header
;
1541 case pci_fixup_final
:
1542 start
= __start_pci_fixups_final
;
1543 end
= __end_pci_fixups_final
;
1546 case pci_fixup_enable
:
1547 start
= __start_pci_fixups_enable
;
1548 end
= __end_pci_fixups_enable
;
1551 case pci_fixup_resume
:
1552 start
= __start_pci_fixups_resume
;
1553 end
= __end_pci_fixups_resume
;
1557 /* stupid compiler warning, you would think with an enum... */
1560 pci_do_fixups(dev
, start
, end
);
1562 EXPORT_SYMBOL(pci_fixup_device
);
1564 /* Enable 1k I/O space granularity on the Intel P64H2 */
1565 static void __devinit
quirk_p64h2_1k_io(struct pci_dev
*dev
)
1568 u8 io_base_lo
, io_limit_lo
;
1569 unsigned long base
, limit
;
1570 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1572 pci_read_config_word(dev
, 0x40, &en1k
);
1575 dev_info(&dev
->dev
, "Enable I/O Space to 1KB granularity\n");
1577 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
1578 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
1579 base
= (io_base_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1580 limit
= (io_limit_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1582 if (base
<= limit
) {
1584 res
->end
= limit
+ 0x3ff;
1588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
1590 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1591 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1592 * in drivers/pci/setup-bus.c
1594 static void __devinit
quirk_p64h2_1k_io_fix_iobl(struct pci_dev
*dev
)
1596 u16 en1k
, iobl_adr
, iobl_adr_1k
;
1597 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1599 pci_read_config_word(dev
, 0x40, &en1k
);
1602 pci_read_config_word(dev
, PCI_IO_BASE
, &iobl_adr
);
1604 iobl_adr_1k
= iobl_adr
| (res
->start
>> 8) | (res
->end
& 0xfc00);
1606 if (iobl_adr
!= iobl_adr_1k
) {
1607 dev_info(&dev
->dev
, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1608 iobl_adr
,iobl_adr_1k
);
1609 pci_write_config_word(dev
, PCI_IO_BASE
, iobl_adr_1k
);
1613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io_fix_iobl
);
1615 /* Under some circumstances, AER is not linked with extended capabilities.
1616 * Force it to be linked by setting the corresponding control bit in the
1619 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
1622 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
1624 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
1626 "Linking AER extended capability\n");
1630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1631 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1632 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1633 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1635 static void __devinit
quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
1638 * Disable PCI Bus Parking and PCI Master read caching on CX700
1639 * which causes unspecified timing errors with a VT6212L on the PCI
1640 * bus leading to USB2.0 packet loss. The defaults are that these
1641 * features are turned off but some BIOSes turn them on.
1645 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
1647 /* Turn off PCI Bus Parking */
1648 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
1650 /* Turn off PCI Master read caching */
1651 pci_write_config_byte(dev
, 0x72, 0x0);
1652 pci_write_config_byte(dev
, 0x75, 0x1);
1653 pci_write_config_byte(dev
, 0x77, 0x0);
1656 "Disabling VIA CX700 PCI parking/caching\n");
1660 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
1662 #ifdef CONFIG_PCI_MSI
1663 /* Some chipsets do not support MSI. We cannot easily rely on setting
1664 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1665 * some other busses controlled by the chipset even if Linux is not
1666 * aware of it. Instead of setting the flag on all busses in the
1667 * machine, simply disable MSI globally.
1669 static void __init
quirk_disable_all_msi(struct pci_dev
*dev
)
1672 dev_warn(&dev
->dev
, "MSI quirk detected; MSI disabled\n");
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
1679 /* Disable MSI on chipsets that are known to not support it */
1680 static void __devinit
quirk_disable_msi(struct pci_dev
*dev
)
1682 if (dev
->subordinate
) {
1683 dev_warn(&dev
->dev
, "MSI quirk detected; "
1684 "subordinate MSI disabled\n");
1685 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
1690 /* Go through the list of Hypertransport capabilities and
1691 * return 1 if a HT MSI capability is found and enabled */
1692 static int __devinit
msi_ht_cap_enabled(struct pci_dev
*dev
)
1696 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
1697 while (pos
&& ttl
--) {
1700 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1703 dev_info(&dev
->dev
, "Found %s HT MSI Mapping\n",
1704 flags
& HT_MSI_FLAGS_ENABLE
?
1705 "enabled" : "disabled");
1706 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
1709 pos
= pci_find_next_ht_capability(dev
, pos
,
1710 HT_CAPTYPE_MSI_MAPPING
);
1715 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1716 static void __devinit
quirk_msi_ht_cap(struct pci_dev
*dev
)
1718 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
1719 dev_warn(&dev
->dev
, "MSI quirk detected; "
1720 "subordinate MSI disabled\n");
1721 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1724 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
1728 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1729 * MSI are supported if the MSI capability set in any of these mappings.
1731 static void __devinit
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
1733 struct pci_dev
*pdev
;
1735 if (!dev
->subordinate
)
1738 /* check HT MSI cap on this chipset and the root one.
1739 * a single one having MSI is enough to be sure that MSI are supported.
1741 pdev
= pci_get_slot(dev
->bus
, 0);
1744 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
1745 dev_warn(&dev
->dev
, "MSI quirk detected; "
1746 "subordinate MSI disabled\n");
1747 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1752 quirk_nvidia_ck804_msi_ht_cap
);
1754 /* Force enable MSI mapping capability on HT bridges */
1755 static void __devinit
ht_enable_msi_mapping(struct pci_dev
*dev
)
1759 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
1760 while (pos
&& ttl
--) {
1763 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1765 dev_info(&dev
->dev
, "Enabling HT MSI Mapping\n");
1767 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1768 flags
| HT_MSI_FLAGS_ENABLE
);
1770 pos
= pci_find_next_ht_capability(dev
, pos
,
1771 HT_CAPTYPE_MSI_MAPPING
);
1774 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
1775 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
1776 ht_enable_msi_mapping
);
1778 static void __devinit
nv_msi_ht_cap_quirk(struct pci_dev
*dev
)
1780 struct pci_dev
*host_bridge
;
1784 * HT MSI mapping should be disabled on devices that are below
1785 * a non-Hypertransport host bridge. Locate the host bridge...
1787 host_bridge
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1788 if (host_bridge
== NULL
) {
1790 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1794 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
1796 /* Host bridge is to HT */
1797 ht_enable_msi_mapping(dev
);
1801 /* Host bridge is not to HT, disable HT MSI mapping on this device */
1802 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
1803 while (pos
&& ttl
--) {
1806 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1808 dev_info(&dev
->dev
, "Disabling HT MSI mapping");
1809 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1810 flags
& ~HT_MSI_FLAGS_ENABLE
);
1812 pos
= pci_find_next_ht_capability(dev
, pos
,
1813 HT_CAPTYPE_MSI_MAPPING
);
1816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk
);
1818 static void __devinit
quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
1820 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
1822 static void __devinit
quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
1826 /* SB700 MSI issue will be fixed at HW level from revision A21,
1827 * we need check PCI REVISION ID of SMBus controller to get SB700
1830 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
1835 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
1836 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1840 PCI_DEVICE_ID_TIGON3_5780
,
1841 quirk_msi_intx_disable_bug
);
1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1843 PCI_DEVICE_ID_TIGON3_5780S
,
1844 quirk_msi_intx_disable_bug
);
1845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1846 PCI_DEVICE_ID_TIGON3_5714
,
1847 quirk_msi_intx_disable_bug
);
1848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1849 PCI_DEVICE_ID_TIGON3_5714S
,
1850 quirk_msi_intx_disable_bug
);
1851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1852 PCI_DEVICE_ID_TIGON3_5715
,
1853 quirk_msi_intx_disable_bug
);
1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
1855 PCI_DEVICE_ID_TIGON3_5715S
,
1856 quirk_msi_intx_disable_bug
);
1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
1859 quirk_msi_intx_disable_ati_bug
);
1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
1861 quirk_msi_intx_disable_ati_bug
);
1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
1863 quirk_msi_intx_disable_ati_bug
);
1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
1865 quirk_msi_intx_disable_ati_bug
);
1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
1867 quirk_msi_intx_disable_ati_bug
);
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
1870 quirk_msi_intx_disable_bug
);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
1872 quirk_msi_intx_disable_bug
);
1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
1874 quirk_msi_intx_disable_bug
);
1876 #endif /* CONFIG_PCI_MSI */