2 * General Purpose functions for the global management of the
3 * 8260 Communication Processor Module.
4 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
5 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
8 * 2006 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 * Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
19 * In addition to the individual control of the communication
20 * channels, there are a few functions that globally affect the
21 * communication processor.
23 * Buffer descriptors must be allocated from the dual ported memory
24 * space. The allocator for that is here. When the communication
25 * process is reset, we reclaim the memory available. There is
26 * currently no deallocator for this memory.
28 #include <linux/errno.h>
29 #include <linux/sched.h>
30 #include <linux/kernel.h>
31 #include <linux/param.h>
32 #include <linux/string.h>
34 #include <linux/interrupt.h>
35 #include <linux/module.h>
40 #include <asm/mpc8260.h>
42 #include <asm/pgtable.h>
44 #include <asm/rheap.h>
45 #include <asm/fs_pd.h>
47 #include <sysdev/fsl_soc.h>
49 cpm_cpm2_t __iomem
*cpmp
; /* Pointer to comm processor space */
51 /* We allocate this here because it is used almost exclusively for
52 * the communication processor devices.
54 cpm2_map_t __iomem
*cpm2_immr
;
56 #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
57 of space for CPM as it is larger
60 void __init
cpm2_reset(void)
62 #ifdef CONFIG_PPC_85xx
63 cpm2_immr
= ioremap(CPM_MAP_ADDR
, CPM_MAP_SIZE
);
65 cpm2_immr
= ioremap(get_immrbase(), CPM_MAP_SIZE
);
68 /* Reclaim the DP memory for our use.
72 /* Tell everyone where the comm processor resides.
74 cpmp
= &cpm2_immr
->im_cpm
;
76 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
79 cpm_command(CPM_CR_RST
, 0);
83 static DEFINE_SPINLOCK(cmd_lock
);
85 #define MAX_CR_CMD_LOOPS 10000
87 int cpm_command(u32 command
, u8 opcode
)
92 spin_lock_irqsave(&cmd_lock
, flags
);
95 out_be32(&cpmp
->cp_cpcr
, command
| opcode
| CPM_CR_FLG
);
96 for (i
= 0; i
< MAX_CR_CMD_LOOPS
; i
++)
97 if ((in_be32(&cpmp
->cp_cpcr
) & CPM_CR_FLG
) == 0)
100 printk(KERN_ERR
"%s(): Not able to issue CPM command\n", __func__
);
103 spin_unlock_irqrestore(&cmd_lock
, flags
);
106 EXPORT_SYMBOL(cpm_command
);
108 /* Set a baud rate generator. This needs lots of work. There are
109 * eight BRGs, which can be connected to the CPM channels or output
110 * as clocks. The BRGs are in two different block of internal
111 * memory mapped space.
112 * The baud rate clock is the system clock divided by something.
113 * It was set up long ago during the initial boot phase and is
115 * Baud rate clocks are zero-based in the driver code (as that maps
116 * to port numbers). Documentation uses 1-based numbering.
118 #define BRG_INT_CLK (get_brgfreq())
119 #define BRG_UART_CLK (BRG_INT_CLK/16)
121 /* This function is used by UARTS, or anything else that uses a 16x
125 cpm_setbrg(uint brg
, uint rate
)
129 /* This is good enough to get SMCs running.....
132 bp
= cpm2_map_size(im_brgc1
, 16);
134 bp
= cpm2_map_size(im_brgc5
, 16);
138 out_be32(bp
, (((BRG_UART_CLK
/ rate
) - 1) << 1) | CPM_BRG_EN
);
143 /* This function is used to set high speed synchronous baud rate
147 cpm2_fastbrg(uint brg
, uint rate
, int div16
)
153 bp
= cpm2_map_size(im_brgc1
, 16);
155 bp
= cpm2_map_size(im_brgc5
, 16);
159 val
= ((BRG_INT_CLK
/ rate
) << 1) | CPM_BRG_EN
;
161 val
|= CPM_BRG_DIV16
;
167 int cpm2_clk_setup(enum cpm_clk_target target
, int clock
, int mode
)
172 cpmux_t __iomem
*im_cpmux
;
177 {CPM_CLK_FCC1
, CPM_BRG5
, 0},
178 {CPM_CLK_FCC1
, CPM_BRG6
, 1},
179 {CPM_CLK_FCC1
, CPM_BRG7
, 2},
180 {CPM_CLK_FCC1
, CPM_BRG8
, 3},
181 {CPM_CLK_FCC1
, CPM_CLK9
, 4},
182 {CPM_CLK_FCC1
, CPM_CLK10
, 5},
183 {CPM_CLK_FCC1
, CPM_CLK11
, 6},
184 {CPM_CLK_FCC1
, CPM_CLK12
, 7},
185 {CPM_CLK_FCC2
, CPM_BRG5
, 0},
186 {CPM_CLK_FCC2
, CPM_BRG6
, 1},
187 {CPM_CLK_FCC2
, CPM_BRG7
, 2},
188 {CPM_CLK_FCC2
, CPM_BRG8
, 3},
189 {CPM_CLK_FCC2
, CPM_CLK13
, 4},
190 {CPM_CLK_FCC2
, CPM_CLK14
, 5},
191 {CPM_CLK_FCC2
, CPM_CLK15
, 6},
192 {CPM_CLK_FCC2
, CPM_CLK16
, 7},
193 {CPM_CLK_FCC3
, CPM_BRG5
, 0},
194 {CPM_CLK_FCC3
, CPM_BRG6
, 1},
195 {CPM_CLK_FCC3
, CPM_BRG7
, 2},
196 {CPM_CLK_FCC3
, CPM_BRG8
, 3},
197 {CPM_CLK_FCC3
, CPM_CLK13
, 4},
198 {CPM_CLK_FCC3
, CPM_CLK14
, 5},
199 {CPM_CLK_FCC3
, CPM_CLK15
, 6},
200 {CPM_CLK_FCC3
, CPM_CLK16
, 7},
201 {CPM_CLK_SCC1
, CPM_BRG1
, 0},
202 {CPM_CLK_SCC1
, CPM_BRG2
, 1},
203 {CPM_CLK_SCC1
, CPM_BRG3
, 2},
204 {CPM_CLK_SCC1
, CPM_BRG4
, 3},
205 {CPM_CLK_SCC1
, CPM_CLK11
, 4},
206 {CPM_CLK_SCC1
, CPM_CLK12
, 5},
207 {CPM_CLK_SCC1
, CPM_CLK3
, 6},
208 {CPM_CLK_SCC1
, CPM_CLK4
, 7},
209 {CPM_CLK_SCC2
, CPM_BRG1
, 0},
210 {CPM_CLK_SCC2
, CPM_BRG2
, 1},
211 {CPM_CLK_SCC2
, CPM_BRG3
, 2},
212 {CPM_CLK_SCC2
, CPM_BRG4
, 3},
213 {CPM_CLK_SCC2
, CPM_CLK11
, 4},
214 {CPM_CLK_SCC2
, CPM_CLK12
, 5},
215 {CPM_CLK_SCC2
, CPM_CLK3
, 6},
216 {CPM_CLK_SCC2
, CPM_CLK4
, 7},
217 {CPM_CLK_SCC3
, CPM_BRG1
, 0},
218 {CPM_CLK_SCC3
, CPM_BRG2
, 1},
219 {CPM_CLK_SCC3
, CPM_BRG3
, 2},
220 {CPM_CLK_SCC3
, CPM_BRG4
, 3},
221 {CPM_CLK_SCC3
, CPM_CLK5
, 4},
222 {CPM_CLK_SCC3
, CPM_CLK6
, 5},
223 {CPM_CLK_SCC3
, CPM_CLK7
, 6},
224 {CPM_CLK_SCC3
, CPM_CLK8
, 7},
225 {CPM_CLK_SCC4
, CPM_BRG1
, 0},
226 {CPM_CLK_SCC4
, CPM_BRG2
, 1},
227 {CPM_CLK_SCC4
, CPM_BRG3
, 2},
228 {CPM_CLK_SCC4
, CPM_BRG4
, 3},
229 {CPM_CLK_SCC4
, CPM_CLK5
, 4},
230 {CPM_CLK_SCC4
, CPM_CLK6
, 5},
231 {CPM_CLK_SCC4
, CPM_CLK7
, 6},
232 {CPM_CLK_SCC4
, CPM_CLK8
, 7},
235 im_cpmux
= cpm2_map(im_cpmux
);
239 reg
= &im_cpmux
->cmx_scr
;
243 reg
= &im_cpmux
->cmx_scr
;
247 reg
= &im_cpmux
->cmx_scr
;
251 reg
= &im_cpmux
->cmx_scr
;
255 reg
= &im_cpmux
->cmx_fcr
;
259 reg
= &im_cpmux
->cmx_fcr
;
263 reg
= &im_cpmux
->cmx_fcr
;
267 printk(KERN_ERR
"cpm2_clock_setup: invalid clock target\n");
271 if (mode
== CPM_CLK_RX
)
274 for (i
= 0; i
< ARRAY_SIZE(clk_map
); i
++) {
275 if (clk_map
[i
][0] == target
&& clk_map
[i
][1] == clock
) {
276 bits
= clk_map
[i
][2];
280 if (i
== ARRAY_SIZE(clk_map
))
286 out_be32(reg
, (in_be32(reg
) & ~mask
) | bits
);
288 cpm2_unmap(im_cpmux
);
292 int cpm2_smc_clk_setup(enum cpm_clk_target target
, int clock
)
297 cpmux_t __iomem
*im_cpmux
;
302 {CPM_CLK_SMC1
, CPM_BRG1
, 0},
303 {CPM_CLK_SMC1
, CPM_BRG7
, 1},
304 {CPM_CLK_SMC1
, CPM_CLK7
, 2},
305 {CPM_CLK_SMC1
, CPM_CLK9
, 3},
306 {CPM_CLK_SMC2
, CPM_BRG2
, 0},
307 {CPM_CLK_SMC2
, CPM_BRG8
, 1},
308 {CPM_CLK_SMC2
, CPM_CLK4
, 2},
309 {CPM_CLK_SMC2
, CPM_CLK15
, 3},
312 im_cpmux
= cpm2_map(im_cpmux
);
316 reg
= &im_cpmux
->cmx_smr
;
321 reg
= &im_cpmux
->cmx_smr
;
326 printk(KERN_ERR
"cpm2_smc_clock_setup: invalid clock target\n");
330 for (i
= 0; i
< ARRAY_SIZE(clk_map
); i
++) {
331 if (clk_map
[i
][0] == target
&& clk_map
[i
][1] == clock
) {
332 bits
= clk_map
[i
][2];
336 if (i
== ARRAY_SIZE(clk_map
))
342 out_8(reg
, (in_8(reg
) & ~mask
) | bits
);
344 cpm2_unmap(im_cpmux
);
348 struct cpm2_ioports
{
349 u32 dir
, par
, sor
, odr
, dat
;
353 void cpm2_set_pin(int port
, int pin
, int flags
)
355 struct cpm2_ioports __iomem
*iop
=
356 (struct cpm2_ioports __iomem
*)&cpm2_immr
->im_ioport
;
358 pin
= 1 << (31 - pin
);
360 if (flags
& CPM_PIN_OUTPUT
)
361 setbits32(&iop
[port
].dir
, pin
);
363 clrbits32(&iop
[port
].dir
, pin
);
365 if (!(flags
& CPM_PIN_GPIO
))
366 setbits32(&iop
[port
].par
, pin
);
368 clrbits32(&iop
[port
].par
, pin
);
370 if (flags
& CPM_PIN_SECONDARY
)
371 setbits32(&iop
[port
].sor
, pin
);
373 clrbits32(&iop
[port
].sor
, pin
);
375 if (flags
& CPM_PIN_OPENDRAIN
)
376 setbits32(&iop
[port
].odr
, pin
);
378 clrbits32(&iop
[port
].odr
, pin
);