ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / arch / powerpc / sysdev / qe_lib / qe.c
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1 /*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
8 * Description:
9 * General Purpose functions for the global management of the
10 * QUICC Engine (QE).
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/param.h>
21 #include <linux/string.h>
22 #include <linux/mm.h>
23 #include <linux/interrupt.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <linux/delay.h>
27 #include <linux/ioport.h>
28 #include <linux/crc32.h>
29 #include <asm/irq.h>
30 #include <asm/page.h>
31 #include <asm/pgtable.h>
32 #include <asm/immap_qe.h>
33 #include <asm/qe.h>
34 #include <asm/prom.h>
35 #include <asm/rheap.h>
37 static void qe_snums_init(void);
38 static void qe_muram_init(void);
39 static int qe_sdma_init(void);
41 static DEFINE_SPINLOCK(qe_lock);
43 /* QE snum state */
44 enum qe_snum_state {
45 QE_SNUM_STATE_USED,
46 QE_SNUM_STATE_FREE
49 /* QE snum */
50 struct qe_snum {
51 u8 num;
52 enum qe_snum_state state;
55 /* We allocate this here because it is used almost exclusively for
56 * the communication processor devices.
58 struct qe_immap __iomem *qe_immr;
59 EXPORT_SYMBOL(qe_immr);
61 static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
63 static phys_addr_t qebase = -1;
65 phys_addr_t get_qe_base(void)
67 struct device_node *qe;
68 unsigned int size;
69 const u32 *prop;
71 if (qebase != -1)
72 return qebase;
74 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
75 if (!qe) {
76 qe = of_find_node_by_type(NULL, "qe");
77 if (!qe)
78 return qebase;
81 prop = of_get_property(qe, "reg", &size);
82 if (prop && size >= sizeof(*prop))
83 qebase = of_translate_address(qe, prop);
84 of_node_put(qe);
86 return qebase;
89 EXPORT_SYMBOL(get_qe_base);
91 void qe_reset(void)
93 if (qe_immr == NULL)
94 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
96 qe_snums_init();
98 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
99 QE_CR_PROTOCOL_UNSPECIFIED, 0);
101 /* Reclaim the MURAM memory for our use. */
102 qe_muram_init();
104 if (qe_sdma_init())
105 panic("sdma init failed!");
108 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
110 unsigned long flags;
111 u8 mcn_shift = 0, dev_shift = 0;
113 spin_lock_irqsave(&qe_lock, flags);
114 if (cmd == QE_RESET) {
115 out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
116 } else {
117 if (cmd == QE_ASSIGN_PAGE) {
118 /* Here device is the SNUM, not sub-block */
119 dev_shift = QE_CR_SNUM_SHIFT;
120 } else if (cmd == QE_ASSIGN_RISC) {
121 /* Here device is the SNUM, and mcnProtocol is
122 * e_QeCmdRiscAssignment value */
123 dev_shift = QE_CR_SNUM_SHIFT;
124 mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
125 } else {
126 if (device == QE_CR_SUBBLOCK_USB)
127 mcn_shift = QE_CR_MCN_USB_SHIFT;
128 else
129 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
132 out_be32(&qe_immr->cp.cecdr, cmd_input);
133 out_be32(&qe_immr->cp.cecr,
134 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
135 mcn_protocol << mcn_shift));
138 /* wait for the QE_CR_FLG to clear */
139 while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG)
140 cpu_relax();
141 spin_unlock_irqrestore(&qe_lock, flags);
143 return 0;
145 EXPORT_SYMBOL(qe_issue_cmd);
147 /* Set a baud rate generator. This needs lots of work. There are
148 * 16 BRGs, which can be connected to the QE channels or output
149 * as clocks. The BRGs are in two different block of internal
150 * memory mapped space.
151 * The BRG clock is the QE clock divided by 2.
152 * It was set up long ago during the initial boot phase and is
153 * is given to us.
154 * Baud rate clocks are zero-based in the driver code (as that maps
155 * to port numbers). Documentation uses 1-based numbering.
157 static unsigned int brg_clk = 0;
159 unsigned int qe_get_brg_clk(void)
161 struct device_node *qe;
162 unsigned int size;
163 const u32 *prop;
165 if (brg_clk)
166 return brg_clk;
168 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
169 if (!qe) {
170 qe = of_find_node_by_type(NULL, "qe");
171 if (!qe)
172 return brg_clk;
175 prop = of_get_property(qe, "brg-frequency", &size);
176 if (prop && size == sizeof(*prop))
177 brg_clk = *prop;
179 of_node_put(qe);
181 return brg_clk;
183 EXPORT_SYMBOL(qe_get_brg_clk);
185 /* Program the BRG to the given sampling rate and multiplier
187 * @brg: the BRG, QE_BRG1 - QE_BRG16
188 * @rate: the desired sampling rate
189 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
190 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
191 * then 'multiplier' should be 8.
193 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
195 u32 divisor, tempval;
196 u32 div16 = 0;
198 if ((brg < QE_BRG1) || (brg > QE_BRG16))
199 return -EINVAL;
201 divisor = qe_get_brg_clk() / (rate * multiplier);
203 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
204 div16 = QE_BRGC_DIV16;
205 divisor /= 16;
208 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
209 that the BRG divisor must be even if you're not using divide-by-16
210 mode. */
211 if (!div16 && (divisor & 1))
212 divisor++;
214 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
215 QE_BRGC_ENABLE | div16;
217 out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
219 return 0;
221 EXPORT_SYMBOL(qe_setbrg);
223 /* Convert a string to a QE clock source enum
225 * This function takes a string, typically from a property in the device
226 * tree, and returns the corresponding "enum qe_clock" value.
228 enum qe_clock qe_clock_source(const char *source)
230 unsigned int i;
232 if (strcasecmp(source, "none") == 0)
233 return QE_CLK_NONE;
235 if (strncasecmp(source, "brg", 3) == 0) {
236 i = simple_strtoul(source + 3, NULL, 10);
237 if ((i >= 1) && (i <= 16))
238 return (QE_BRG1 - 1) + i;
239 else
240 return QE_CLK_DUMMY;
243 if (strncasecmp(source, "clk", 3) == 0) {
244 i = simple_strtoul(source + 3, NULL, 10);
245 if ((i >= 1) && (i <= 24))
246 return (QE_CLK1 - 1) + i;
247 else
248 return QE_CLK_DUMMY;
251 return QE_CLK_DUMMY;
253 EXPORT_SYMBOL(qe_clock_source);
255 /* Initialize SNUMs (thread serial numbers) according to
256 * QE Module Control chapter, SNUM table
258 static void qe_snums_init(void)
260 int i;
261 static const u8 snum_init[] = {
262 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
263 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
264 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
265 0xD8, 0xD9, 0xE8, 0xE9,
268 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
269 snums[i].num = snum_init[i];
270 snums[i].state = QE_SNUM_STATE_FREE;
274 int qe_get_snum(void)
276 unsigned long flags;
277 int snum = -EBUSY;
278 int i;
280 spin_lock_irqsave(&qe_lock, flags);
281 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
282 if (snums[i].state == QE_SNUM_STATE_FREE) {
283 snums[i].state = QE_SNUM_STATE_USED;
284 snum = snums[i].num;
285 break;
288 spin_unlock_irqrestore(&qe_lock, flags);
290 return snum;
292 EXPORT_SYMBOL(qe_get_snum);
294 void qe_put_snum(u8 snum)
296 int i;
298 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
299 if (snums[i].num == snum) {
300 snums[i].state = QE_SNUM_STATE_FREE;
301 break;
305 EXPORT_SYMBOL(qe_put_snum);
307 static int qe_sdma_init(void)
309 struct sdma *sdma = &qe_immr->sdma;
310 unsigned long sdma_buf_offset;
312 if (!sdma)
313 return -ENODEV;
315 /* allocate 2 internal temporary buffers (512 bytes size each) for
316 * the SDMA */
317 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
318 if (IS_ERR_VALUE(sdma_buf_offset))
319 return -ENOMEM;
321 out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
322 out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
323 (0x1 << QE_SDMR_CEN_SHIFT)));
325 return 0;
329 * muram_alloc / muram_free bits.
331 static DEFINE_SPINLOCK(qe_muram_lock);
333 /* 16 blocks should be enough to satisfy all requests
334 * until the memory subsystem goes up... */
335 static rh_block_t qe_boot_muram_rh_block[16];
336 static rh_info_t qe_muram_info;
338 static void qe_muram_init(void)
340 struct device_node *np;
341 const u32 *address;
342 u64 size;
343 unsigned int flags;
345 /* initialize the info header */
346 rh_init(&qe_muram_info, 1,
347 sizeof(qe_boot_muram_rh_block) /
348 sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
350 /* Attach the usable muram area */
351 /* XXX: This is a subset of the available muram. It
352 * varies with the processor and the microcode patches activated.
354 np = of_find_compatible_node(NULL, NULL, "fsl,qe-muram-data");
355 if (!np) {
356 np = of_find_node_by_name(NULL, "data-only");
357 if (!np) {
358 WARN_ON(1);
359 return;
363 address = of_get_address(np, 0, &size, &flags);
364 WARN_ON(!address);
366 of_node_put(np);
367 if (address)
368 rh_attach_region(&qe_muram_info, *address, (int)size);
371 /* This function returns an index into the MURAM area.
373 unsigned long qe_muram_alloc(int size, int align)
375 unsigned long start;
376 unsigned long flags;
378 spin_lock_irqsave(&qe_muram_lock, flags);
379 start = rh_alloc_align(&qe_muram_info, size, align, "QE");
380 spin_unlock_irqrestore(&qe_muram_lock, flags);
382 return start;
384 EXPORT_SYMBOL(qe_muram_alloc);
386 int qe_muram_free(unsigned long offset)
388 int ret;
389 unsigned long flags;
391 spin_lock_irqsave(&qe_muram_lock, flags);
392 ret = rh_free(&qe_muram_info, offset);
393 spin_unlock_irqrestore(&qe_muram_lock, flags);
395 return ret;
397 EXPORT_SYMBOL(qe_muram_free);
399 /* not sure if this is ever needed */
400 unsigned long qe_muram_alloc_fixed(unsigned long offset, int size)
402 unsigned long start;
403 unsigned long flags;
405 spin_lock_irqsave(&qe_muram_lock, flags);
406 start = rh_alloc_fixed(&qe_muram_info, offset, size, "commproc");
407 spin_unlock_irqrestore(&qe_muram_lock, flags);
409 return start;
411 EXPORT_SYMBOL(qe_muram_alloc_fixed);
413 void qe_muram_dump(void)
415 rh_dump(&qe_muram_info);
417 EXPORT_SYMBOL(qe_muram_dump);
419 /* The maximum number of RISCs we support */
420 #define MAX_QE_RISC 2
422 /* Firmware information stored here for qe_get_firmware_info() */
423 static struct qe_firmware_info qe_firmware_info;
426 * Set to 1 if QE firmware has been uploaded, and therefore
427 * qe_firmware_info contains valid data.
429 static int qe_firmware_uploaded;
432 * Upload a QE microcode
434 * This function is a worker function for qe_upload_firmware(). It does
435 * the actual uploading of the microcode.
437 static void qe_upload_microcode(const void *base,
438 const struct qe_microcode *ucode)
440 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
441 unsigned int i;
443 if (ucode->major || ucode->minor || ucode->revision)
444 printk(KERN_INFO "qe-firmware: "
445 "uploading microcode '%s' version %u.%u.%u\n",
446 ucode->id, ucode->major, ucode->minor, ucode->revision);
447 else
448 printk(KERN_INFO "qe-firmware: "
449 "uploading microcode '%s'\n", ucode->id);
451 /* Use auto-increment */
452 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
453 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
455 for (i = 0; i < be32_to_cpu(ucode->count); i++)
456 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
460 * Upload a microcode to the I-RAM at a specific address.
462 * See Documentation/powerpc/qe-firmware.txt for information on QE microcode
463 * uploading.
465 * Currently, only version 1 is supported, so the 'version' field must be
466 * set to 1.
468 * The SOC model and revision are not validated, they are only displayed for
469 * informational purposes.
471 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
472 * all of the microcode structures, minus the CRC.
474 * 'length' is the size that the structure says it is, including the CRC.
476 int qe_upload_firmware(const struct qe_firmware *firmware)
478 unsigned int i;
479 unsigned int j;
480 u32 crc;
481 size_t calc_size = sizeof(struct qe_firmware);
482 size_t length;
483 const struct qe_header *hdr;
485 if (!firmware) {
486 printk(KERN_ERR "qe-firmware: invalid pointer\n");
487 return -EINVAL;
490 hdr = &firmware->header;
491 length = be32_to_cpu(hdr->length);
493 /* Check the magic */
494 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
495 (hdr->magic[2] != 'F')) {
496 printk(KERN_ERR "qe-firmware: not a microcode\n");
497 return -EPERM;
500 /* Check the version */
501 if (hdr->version != 1) {
502 printk(KERN_ERR "qe-firmware: unsupported version\n");
503 return -EPERM;
506 /* Validate some of the fields */
507 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
508 printk(KERN_ERR "qe-firmware: invalid data\n");
509 return -EINVAL;
512 /* Validate the length and check if there's a CRC */
513 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
515 for (i = 0; i < firmware->count; i++)
517 * For situations where the second RISC uses the same microcode
518 * as the first, the 'code_offset' and 'count' fields will be
519 * zero, so it's okay to add those.
521 calc_size += sizeof(__be32) *
522 be32_to_cpu(firmware->microcode[i].count);
524 /* Validate the length */
525 if (length != calc_size + sizeof(__be32)) {
526 printk(KERN_ERR "qe-firmware: invalid length\n");
527 return -EPERM;
530 /* Validate the CRC */
531 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
532 if (crc != crc32(0, firmware, calc_size)) {
533 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
534 return -EIO;
538 * If the microcode calls for it, split the I-RAM.
540 if (!firmware->split)
541 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
543 if (firmware->soc.model)
544 printk(KERN_INFO
545 "qe-firmware: firmware '%s' for %u V%u.%u\n",
546 firmware->id, be16_to_cpu(firmware->soc.model),
547 firmware->soc.major, firmware->soc.minor);
548 else
549 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
550 firmware->id);
553 * The QE only supports one microcode per RISC, so clear out all the
554 * saved microcode information and put in the new.
556 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
557 strcpy(qe_firmware_info.id, firmware->id);
558 qe_firmware_info.extended_modes = firmware->extended_modes;
559 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
560 sizeof(firmware->vtraps));
562 /* Loop through each microcode. */
563 for (i = 0; i < firmware->count; i++) {
564 const struct qe_microcode *ucode = &firmware->microcode[i];
566 /* Upload a microcode if it's present */
567 if (ucode->code_offset)
568 qe_upload_microcode(firmware, ucode);
570 /* Program the traps for this processor */
571 for (j = 0; j < 16; j++) {
572 u32 trap = be32_to_cpu(ucode->traps[j]);
574 if (trap)
575 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
578 /* Enable traps */
579 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
582 qe_firmware_uploaded = 1;
584 return 0;
586 EXPORT_SYMBOL(qe_upload_firmware);
589 * Get info on the currently-loaded firmware
591 * This function also checks the device tree to see if the boot loader has
592 * uploaded a firmware already.
594 struct qe_firmware_info *qe_get_firmware_info(void)
596 static int initialized;
597 struct property *prop;
598 struct device_node *qe;
599 struct device_node *fw = NULL;
600 const char *sprop;
601 unsigned int i;
604 * If we haven't checked yet, and a driver hasn't uploaded a firmware
605 * yet, then check the device tree for information.
607 if (qe_firmware_uploaded)
608 return &qe_firmware_info;
610 if (initialized)
611 return NULL;
613 initialized = 1;
616 * Newer device trees have an "fsl,qe" compatible property for the QE
617 * node, but we still need to support older device trees.
619 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
620 if (!qe) {
621 qe = of_find_node_by_type(NULL, "qe");
622 if (!qe)
623 return NULL;
626 /* Find the 'firmware' child node */
627 for_each_child_of_node(qe, fw) {
628 if (strcmp(fw->name, "firmware") == 0)
629 break;
632 of_node_put(qe);
634 /* Did we find the 'firmware' node? */
635 if (!fw)
636 return NULL;
638 qe_firmware_uploaded = 1;
640 /* Copy the data into qe_firmware_info*/
641 sprop = of_get_property(fw, "id", NULL);
642 if (sprop)
643 strncpy(qe_firmware_info.id, sprop,
644 sizeof(qe_firmware_info.id) - 1);
646 prop = of_find_property(fw, "extended-modes", NULL);
647 if (prop && (prop->length == sizeof(u64))) {
648 const u64 *iprop = prop->value;
650 qe_firmware_info.extended_modes = *iprop;
653 prop = of_find_property(fw, "virtual-traps", NULL);
654 if (prop && (prop->length == 32)) {
655 const u32 *iprop = prop->value;
657 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
658 qe_firmware_info.vtraps[i] = iprop[i];
661 of_node_put(fw);
663 return &qe_firmware_info;
665 EXPORT_SYMBOL(qe_get_firmware_info);