arch/ppc/platforms/4xx/bubinga.h

   1 /*
   2  * Bubinga board definitions
   3  *
   4  * Copyright (c) 2005 DENX Software Engineering
   5  * Stefan Roese <sr@denx.de>
   6  *
   7  * Based on original work by
   8  *      SAW (IBM)
   9  *      2003 (c) MontaVista Softare Inc.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  */
  17
  18 #ifdef __KERNEL__
  19 #ifndef __BUBINGA_H__
  20 #define __BUBINGA_H__
  21
  22 #include <platforms/4xx/ibm405ep.h>
  23 #include <asm/ppcboot.h>
  24
  25 /* Memory map for the Bubinga board.
  26  * Generic 4xx plus RTC.
  27  */
  28
  29 #define BUBINGA_RTC_PADDR       ((uint)0xf0000000)
  30 #define BUBINGA_RTC_VADDR       BUBINGA_RTC_PADDR
  31 #define BUBINGA_RTC_SIZE        ((uint)8*1024)
  32
  33 /* The UART clock is based off an internal clock -
  34  * define BASE_BAUD based on the internal clock and divider(s).
  35  * Since BASE_BAUD must be a constant, we will initialize it
  36  * using clock/divider values which OpenBIOS initializes
  37  * for typical configurations at various CPU speeds.
  38  * The base baud is calculated as (FWDA / EXT UART DIV / 16)
  39  */
  40 #define BASE_BAUD               0
  41
  42 /* Flash */
  43 #define PPC40x_FPGA_BASE        0xF0300000
  44 #define PPC40x_FPGA_REG_OFFS    1       /* offset to flash map reg */
  45 #define PPC40x_FLASH_ONBD_N(x)  (x & 0x02)
  46 #define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
  47 #define PPC40x_FLASH_LOW        0xFFF00000
  48 #define PPC40x_FLASH_HIGH       0xFFF80000
  49 #define PPC40x_FLASH_SIZE       0x80000
  50
  51 #define PPC4xx_MACHINE_NAME     "IBM Bubinga"
  52
  53 #endif /* __BUBINGA_H__ */
  54 #endif /* __KERNEL__ */