2 * Embedded Planet 405GP board
3 * http://www.embeddedplanet.com
5 * Author: Matthew Locke <mlocke@mvista.com>
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <asm/system.h>
15 #include <asm/pci-bridge.h>
16 #include <asm/machdep.h>
19 #include <asm/ibm_ocp_pci.h>
23 #define DBG(x...) printk(x)
35 } ep405_devtable
[] = {
37 {0x07, 0x0E, 25}, /* EP405PC: USB */
42 ppc405_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
46 /* AFAICT this is only called a few times during PCI setup, so
47 performance is not critical */
48 for (i
= 0; i
< ARRAY_SIZE(ep405_devtable
); i
++) {
49 if (idsel
== ep405_devtable
[i
].pci_idsel
)
50 return ep405_devtable
[i
].irq
;
56 ep405_setup_arch(void)
60 ibm_ocp_set_emac(0, 0);
62 if (__res
.bi_nvramsize
== 512*1024) {
63 /* FIXME: we should properly handle NVRTCs of different sizes */
64 TODC_INIT(TODC_TYPE_DS1557
, ep405_nvram
, ep405_nvram
, ep405_nvram
, 8);
69 bios_fixup(struct pci_controller
*hose
, struct pcil0_regs
*pcip
)
72 unsigned int bar_response
, bar
;
74 * Expected PCI mapping:
76 * PLB addr PCI memory addr
77 * --------------------- ---------------------
78 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
79 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
81 * PLB addr PCI io addr
82 * --------------------- ---------------------
83 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
87 /* Disable region zero first */
88 out_le32((void *) &(pcip
->pmm
[0].ma
), 0x00000000);
89 /* PLB starting addr, PCI: 0x80000000 */
90 out_le32((void *) &(pcip
->pmm
[0].la
), 0x80000000);
91 /* PCI start addr, 0x80000000 */
92 out_le32((void *) &(pcip
->pmm
[0].pcila
), PPC405_PCI_MEM_BASE
);
93 /* 512MB range of PLB to PCI */
94 out_le32((void *) &(pcip
->pmm
[0].pciha
), 0x00000000);
95 /* Enable no pre-fetch, enable region */
96 out_le32((void *) &(pcip
->pmm
[0].ma
), ((0xffffffff -
97 (PPC405_PCI_UPPER_MEM
-
98 PPC405_PCI_MEM_BASE
)) | 0x01));
100 /* Disable region one */
101 out_le32((void *) &(pcip
->pmm
[1].ma
), 0x00000000);
102 out_le32((void *) &(pcip
->pmm
[1].la
), 0x00000000);
103 out_le32((void *) &(pcip
->pmm
[1].pcila
), 0x00000000);
104 out_le32((void *) &(pcip
->pmm
[1].pciha
), 0x00000000);
105 out_le32((void *) &(pcip
->pmm
[1].ma
), 0x00000000);
106 out_le32((void *) &(pcip
->ptm1ms
), 0x00000000);
108 /* Disable region two */
109 out_le32((void *) &(pcip
->pmm
[2].ma
), 0x00000000);
110 out_le32((void *) &(pcip
->pmm
[2].la
), 0x00000000);
111 out_le32((void *) &(pcip
->pmm
[2].pcila
), 0x00000000);
112 out_le32((void *) &(pcip
->pmm
[2].pciha
), 0x00000000);
113 out_le32((void *) &(pcip
->pmm
[2].ma
), 0x00000000);
114 out_le32((void *) &(pcip
->ptm2ms
), 0x00000000);
116 /* Configure PTM (PCI->PLB) region 1 */
117 out_le32((void *) &(pcip
->ptm1la
), 0x00000000); /* PLB base address */
118 /* Disable PTM region 2 */
119 out_le32((void *) &(pcip
->ptm2ms
), 0x00000000);
121 /* Zero config bars */
122 for (bar
= PCI_BASE_ADDRESS_1
; bar
<= PCI_BASE_ADDRESS_2
; bar
+= 4) {
123 early_write_config_dword(hose
, hose
->first_busno
,
124 PCI_FUNC(hose
->first_busno
), bar
,
126 early_read_config_dword(hose
, hose
->first_busno
,
127 PCI_FUNC(hose
->first_busno
), bar
,
129 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
130 hose
->first_busno
, PCI_SLOT(hose
->first_busno
),
131 PCI_FUNC(hose
->first_busno
), bar
, bar_response
);
144 ep405_bcsr
= ioremap(EP405_BCSR_PADDR
, EP405_BCSR_SIZE
);
146 if (bip
->bi_nvramsize
> 0) {
147 ep405_nvram
= ioremap(EP405_NVRAM_PADDR
, bip
->bi_nvramsize
);
158 /* Workaround for a bug in the firmware it incorrectly sets
159 the IRQ polarities for XIRQ0 and XIRQ1 */
160 mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE
), 0xffffff80); /* set the polarity */
161 mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE
), 0x00000060); /* clear bogus interrupts */
163 /* Activate the XIRQs from the CPLD */
164 writeb(0xf0, ep405_bcsr
+10);
166 /* Set up IRQ routing */
167 for (i
= 0; i
< ARRAY_SIZE(ep405_devtable
); i
++) {
168 if ( (ep405_devtable
[i
].irq
>= 25)
169 && (ep405_devtable
[i
].irq
) <= 31) {
170 writeb(ep405_devtable
[i
].cpld_xirq_select
, ep405_bcsr
+5);
171 writeb(ep405_devtable
[i
].irq
- 25, ep405_bcsr
+6);
177 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
178 unsigned long r6
, unsigned long r7
)
180 ppc4xx_init(r3
, r4
, r5
, r6
, r7
);
182 ppc_md
.setup_arch
= ep405_setup_arch
;
183 ppc_md
.setup_io_mappings
= ep405_map_io
;
184 ppc_md
.init_IRQ
= ep405_init_IRQ
;
186 ppc_md
.nvram_read_val
= todc_direct_read_val
;
187 ppc_md
.nvram_write_val
= todc_direct_write_val
;
189 if (__res
.bi_nvramsize
== 512*1024) {
190 ppc_md
.time_init
= todc_time_init
;
191 ppc_md
.set_rtc_time
= todc_set_rtc_time
;
192 ppc_md
.get_rtc_time
= todc_get_rtc_time
;
194 printk("EP405: NVRTC size is not 512k (not a DS1557). Not sure what to do with it\n");