arch/ppc/platforms/4xx/luan.c

   1 /*
   2  * Luan board specific routines
   3  *
   4  * Matt Porter <mporter@kernel.crashing.org>
   5  *
   6  * Copyright 2004-2005 MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/types.h>
  22 #include <linux/major.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/console.h>
  25 #include <linux/delay.h>
  26 #include <linux/initrd.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/tty.h>
  30 #include <linux/serial.h>
  31 #include <linux/serial_core.h>
  32 #include <linux/serial_8250.h>
  33
  34 #include <asm/system.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/dma.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/ocp.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/time.h>
  43 #include <asm/todc.h>
  44 #include <asm/bootinfo.h>
  45 #include <asm/ppc4xx_pic.h>
  46 #include <asm/ppcboot.h>
  47
  48 #include <syslib/ibm44x_common.h>
  49 #include <syslib/ibm440gx_common.h>
  50 #include <syslib/ibm440sp_common.h>
  51
  52 extern bd_t __res;
  53
  54 static struct ibm44x_clocks clocks __initdata;
  55
  56 static void __init
  57 luan_calibrate_decr(void)
  58 {
  59         unsigned int freq;
  60
  61         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  62                 freq = LUAN_TMR_CLK;
  63         else
  64                 freq = clocks.cpu;
  65
  66         ibm44x_calibrate_decr(freq);
  67 }
  68
  69 static int
  70 luan_show_cpuinfo(struct seq_file *m)
  71 {
  72         seq_printf(m, "vendor\t\t: IBM\n");
  73         seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
  74
  75         return 0;
  76 }
  77
  78 static inline int
  79 luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  80 {
  81         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  82
  83         /* PCIX0 in adapter mode, no host interrupt routing */
  84
  85         /* PCIX1 */
  86         if (hose->index == 0) {
  87                 static char pci_irq_table[][4] =
  88                 /*
  89                  *      PCI IDSEL/INTPIN->INTLINE
  90                  *        A   B   C   D
  91                  */
  92                 {
  93                         { 49, 49, 49, 49 },     /* IDSEL 1 - PCIX1 Slot 0 */
  94                         { 49, 49, 49, 49 },     /* IDSEL 2 - PCIX1 Slot 1 */
  95                         { 49, 49, 49, 49 },     /* IDSEL 3 - PCIX1 Slot 2 */
  96                         { 49, 49, 49, 49 },     /* IDSEL 4 - PCIX1 Slot 3 */
  97                 };
  98                 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
  99                 return PCI_IRQ_TABLE_LOOKUP;
 100         /* PCIX2 */
 101         } else if (hose->index == 1) {
 102                 static char pci_irq_table[][4] =
 103                 /*
 104                  *      PCI IDSEL/INTPIN->INTLINE
 105                  *        A   B   C   D
 106                  */
 107                 {
 108                         { 50, 50, 50, 50 },     /* IDSEL 1 - PCIX2 Slot 0 */
 109                         { 50, 50, 50, 50 },     /* IDSEL 2 - PCIX2 Slot 1 */
 110                         { 50, 50, 50, 50 },     /* IDSEL 3 - PCIX2 Slot 2 */
 111                         { 50, 50, 50, 50 },     /* IDSEL 4 - PCIX2 Slot 3 */
 112                 };
 113                 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 114                 return PCI_IRQ_TABLE_LOOKUP;
 115         }
 116         return -1;
 117 }
 118
 119 static void __init luan_set_emacdata(void)
 120 {
 121         struct ocp_def *def;
 122         struct ocp_func_emac_data *emacdata;
 123
 124         /* Set phy_map, phy_mode, and mac_addr for the EMAC */
 125         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 126         emacdata = def->additions;
 127         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 128         emacdata->phy_mode = PHY_MODE_GMII;
 129         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 130 }
 131
 132 #define PCIX_READW(offset) \
 133         (readw((void *)((u32)pcix_reg_base+offset)))
 134
 135 #define PCIX_WRITEW(value, offset) \
 136         (writew(value, (void *)((u32)pcix_reg_base+offset)))
 137
 138 #define PCIX_WRITEL(value, offset) \
 139         (writel(value, (void *)((u32)pcix_reg_base+offset)))
 140
 141 static void __init
 142 luan_setup_pcix(void)
 143 {
 144         int i;
 145         void *pcix_reg_base;
 146
 147         for (i=0;i<3;i++) {
 148                 pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
 149
 150                 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 151                 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 152
 153                 /* Disable all windows */
 154                 PCIX_WRITEL(0, PCIX0_POM0SA);
 155                 PCIX_WRITEL(0, PCIX0_POM1SA);
 156                 PCIX_WRITEL(0, PCIX0_POM2SA);
 157                 PCIX_WRITEL(0, PCIX0_PIM0SA);
 158                 PCIX_WRITEL(0, PCIX0_PIM0SAH);
 159                 PCIX_WRITEL(0, PCIX0_PIM1SA);
 160                 PCIX_WRITEL(0, PCIX0_PIM2SA);
 161                 PCIX_WRITEL(0, PCIX0_PIM2SAH);
 162
 163                 /*
 164                  * Setup 512MB PLB->PCI outbound mem window
 165                  * (a_n000_0000->0_n000_0000)
 166                  * */
 167                 PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
 168                 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
 169                 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 170                 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
 171                 PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
 172
 173                 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 174                 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 175                 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 176                 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
 177                 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
 178
 179                 iounmap(pcix_reg_base);
 180         }
 181
 182         eieio();
 183 }
 184
 185 static void __init
 186 luan_setup_hose(struct pci_controller *hose,
 187                 int lower_mem,
 188                 int upper_mem,
 189                 int cfga,
 190                 int cfgd,
 191                 u64 pcix_io_base)
 192 {
 193         char name[20];
 194
 195         sprintf(name, "PCIX%d host bridge", hose->index);
 196
 197         hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
 198
 199         pci_init_resource(&hose->io_resource,
 200                         LUAN_PCIX_LOWER_IO,
 201                         LUAN_PCIX_UPPER_IO,
 202                         IORESOURCE_IO,
 203                         name);
 204
 205         pci_init_resource(&hose->mem_resources[0],
 206                         lower_mem,
 207                         upper_mem,
 208                         IORESOURCE_MEM,
 209                         name);
 210
 211         hose->io_space.start = LUAN_PCIX_LOWER_IO;
 212         hose->io_space.end = LUAN_PCIX_UPPER_IO;
 213         hose->mem_space.start = lower_mem;
 214         hose->mem_space.end = upper_mem;
 215         hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
 216         isa_io_base = (unsigned long) hose->io_base_virt;
 217
 218         setup_indirect_pci(hose, cfga, cfgd);
 219         hose->set_cfg_type = 1;
 220 }
 221
 222 static void __init
 223 luan_setup_hoses(void)
 224 {
 225         struct pci_controller *hose1, *hose2;
 226
 227         /* Configure windows on the PCI-X host bridge */
 228         luan_setup_pcix();
 229
 230         /* Allocate hoses for PCIX1 and PCIX2 */
 231         hose1 = pcibios_alloc_controller();
 232         if (!hose1)
 233                 return;
 234
 235         hose2 = pcibios_alloc_controller();
 236         if (!hose2) {
 237                 pcibios_free_controller(hose1);
 238                 return;
 239         }
 240
 241         /* Setup PCIX1 */
 242         hose1->first_busno = 0;
 243         hose1->last_busno = 0xff;
 244
 245         luan_setup_hose(hose1,
 246                         LUAN_PCIX1_LOWER_MEM,
 247                         LUAN_PCIX1_UPPER_MEM,
 248                         PCIX1_CFGA,
 249                         PCIX1_CFGD,
 250                         PCIX1_IO_BASE);
 251
 252         hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
 253
 254         /* Setup PCIX2 */
 255         hose2->first_busno = hose1->last_busno + 1;
 256         hose2->last_busno = 0xff;
 257
 258         luan_setup_hose(hose2,
 259                         LUAN_PCIX2_LOWER_MEM,
 260                         LUAN_PCIX2_UPPER_MEM,
 261                         PCIX2_CFGA,
 262                         PCIX2_CFGD,
 263                         PCIX2_IO_BASE);
 264
 265         hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
 266
 267         ppc_md.pci_swizzle = common_swizzle;
 268         ppc_md.pci_map_irq = luan_map_irq;
 269 }
 270
 271 TODC_ALLOC();
 272
 273 static void __init
 274 luan_early_serial_map(void)
 275 {
 276         struct uart_port port;
 277
 278         /* Setup ioremapped serial port access */
 279         memset(&port, 0, sizeof(port));
 280         port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
 281         port.irq = UART0_INT;
 282         port.uartclk = clocks.uart0;
 283         port.regshift = 0;
 284         port.iotype = UPIO_MEM;
 285         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 286         port.line = 0;
 287
 288         if (early_serial_setup(&port) != 0) {
 289                 printk("Early serial init of port 0 failed\n");
 290         }
 291
 292         port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
 293         port.irq = UART1_INT;
 294         port.uartclk = clocks.uart1;
 295         port.line = 1;
 296
 297         if (early_serial_setup(&port) != 0) {
 298                 printk("Early serial init of port 1 failed\n");
 299         }
 300
 301         port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
 302         port.irq = UART2_INT;
 303         port.uartclk = BASE_BAUD;
 304         port.line = 2;
 305
 306         if (early_serial_setup(&port) != 0) {
 307                 printk("Early serial init of port 2 failed\n");
 308         }
 309 }
 310
 311 static void __init
 312 luan_setup_arch(void)
 313 {
 314         luan_set_emacdata();
 315
 316 #if !defined(CONFIG_BDI_SWITCH)
 317         /*
 318          * The Abatron BDI JTAG debugger does not tolerate others
 319          * mucking with the debug registers.
 320          */
 321         mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
 322 #endif
 323
 324         /*
 325          * Determine various clocks.
 326          * To be completely correct we should get SysClk
 327          * from FPGA, because it can be changed by on-board switches
 328          * --ebs
 329          */
 330         /* 440GX and 440SP clocking is the same -mdp */
 331         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 332         ocp_sys_info.opb_bus_freq = clocks.opb;
 333
 334         /* init to some ~sane value until calibrate_delay() runs */
 335         loops_per_jiffy = 50000000/HZ;
 336
 337         /* Setup PCIXn host bridges */
 338         luan_setup_hoses();
 339
 340 #ifdef CONFIG_BLK_DEV_INITRD
 341         if (initrd_start)
 342                 ROOT_DEV = Root_RAM0;
 343         else
 344 #endif
 345 #ifdef CONFIG_ROOT_NFS
 346                 ROOT_DEV = Root_NFS;
 347 #else
 348                 ROOT_DEV = Root_HDA1;
 349 #endif
 350
 351         luan_early_serial_map();
 352
 353         /* Identify the system */
 354         printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
 355 }
 356
 357 void __init platform_init(unsigned long r3, unsigned long r4,
 358                 unsigned long r5, unsigned long r6, unsigned long r7)
 359 {
 360         ibm44x_platform_init(r3, r4, r5, r6, r7);
 361
 362         ppc_md.setup_arch = luan_setup_arch;
 363         ppc_md.show_cpuinfo = luan_show_cpuinfo;
 364         ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
 365         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 366
 367         ppc_md.calibrate_decr = luan_calibrate_decr;
 368 #ifdef CONFIG_KGDB
 369         ppc_md.early_serial_map = luan_early_serial_map;
 370 #endif
 371 }