arch/ppc/platforms/4xx/ocotea.c

   1 /*
   2  * Ocotea board specific routines
   3  *
   4  * Matt Porter <mporter@kernel.crashing.org>
   5  *
   6  * Copyright 2003-2005 MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/types.h>
  22 #include <linux/major.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/console.h>
  25 #include <linux/delay.h>
  26 #include <linux/initrd.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/tty.h>
  30 #include <linux/serial.h>
  31 #include <linux/serial_core.h>
  32 #include <linux/serial_8250.h>
  33
  34 #include <asm/system.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/dma.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/ocp.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/time.h>
  43 #include <asm/todc.h>
  44 #include <asm/bootinfo.h>
  45 #include <asm/ppc4xx_pic.h>
  46 #include <asm/ppcboot.h>
  47 #include <asm/tlbflush.h>
  48
  49 #include <syslib/gen550.h>
  50 #include <syslib/ibm440gx_common.h>
  51
  52 extern bd_t __res;
  53
  54 static struct ibm44x_clocks clocks __initdata;
  55
  56 static void __init
  57 ocotea_calibrate_decr(void)
  58 {
  59         unsigned int freq;
  60
  61         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  62                 freq = OCOTEA_TMR_CLK;
  63         else
  64                 freq = clocks.cpu;
  65
  66         ibm44x_calibrate_decr(freq);
  67 }
  68
  69 static int
  70 ocotea_show_cpuinfo(struct seq_file *m)
  71 {
  72         seq_printf(m, "vendor\t\t: IBM\n");
  73         seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
  74         ibm440gx_show_cpuinfo(m);
  75         return 0;
  76 }
  77
  78 static inline int
  79 ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  80 {
  81         static char pci_irq_table[][4] =
  82         /*
  83          *      PCI IDSEL/INTPIN->INTLINE
  84          *         A   B   C   D
  85          */
  86         {
  87                 { 23, 23, 23, 23 },     /* IDSEL 1 - PCI Slot 0 */
  88                 { 24, 24, 24, 24 },     /* IDSEL 2 - PCI Slot 1 */
  89                 { 25, 25, 25, 25 },     /* IDSEL 3 - PCI Slot 2 */
  90                 { 26, 26, 26, 26 },     /* IDSEL 4 - PCI Slot 3 */
  91         };
  92
  93         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
  94         return PCI_IRQ_TABLE_LOOKUP;
  95 }
  96
  97 static void __init ocotea_set_emacdata(void)
  98 {
  99         struct ocp_def *def;
 100         struct ocp_func_emac_data *emacdata;
 101         int i;
 102
 103         /*
 104          * Note: Current rev. board only operates in Group 4a
 105          * mode, so we always set EMAC0-1 for SMII and EMAC2-3
 106          * for RGMII (though these could run in RTBI just the same).
 107          *
 108          * The FPGA reg 3 information isn't even suitable for
 109          * determining the phy_mode, so if the board becomes
 110          * usable in !4a, it will be necessary to parse an environment
 111          * variable from the firmware or similar to properly configure
 112          * the phy_map/phy_mode.
 113          */
 114         /* Set phy_map, phy_mode, and mac_addr for each EMAC */
 115         for (i=0; i<4; i++) {
 116                 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
 117                 emacdata = def->additions;
 118                 if (i < 2) {
 119                         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 120                         emacdata->phy_mode = PHY_MODE_SMII;
 121                 }
 122                 else {
 123                         emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
 124                         emacdata->phy_mode = PHY_MODE_RGMII;
 125                 }
 126                 if (i == 0)
 127                         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 128                 else if (i == 1)
 129                         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 130                 else if (i == 2)
 131                         memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
 132                 else if (i == 3)
 133                         memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
 134         }
 135 }
 136
 137 #define PCIX_READW(offset) \
 138         (readw(pcix_reg_base+offset))
 139
 140 #define PCIX_WRITEW(value, offset) \
 141         (writew(value, pcix_reg_base+offset))
 142
 143 #define PCIX_WRITEL(value, offset) \
 144         (writel(value, pcix_reg_base+offset))
 145
 146 /*
 147  * FIXME: This is only here to "make it work".  This will move
 148  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 149  * configuration library. -Matt
 150  */
 151 static void __init
 152 ocotea_setup_pcix(void)
 153 {
 154         void *pcix_reg_base;
 155
 156         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 157
 158         /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 159         PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 160
 161         /* Disable all windows */
 162         PCIX_WRITEL(0, PCIX0_POM0SA);
 163         PCIX_WRITEL(0, PCIX0_POM1SA);
 164         PCIX_WRITEL(0, PCIX0_POM2SA);
 165         PCIX_WRITEL(0, PCIX0_PIM0SA);
 166         PCIX_WRITEL(0, PCIX0_PIM0SAH);
 167         PCIX_WRITEL(0, PCIX0_PIM1SA);
 168         PCIX_WRITEL(0, PCIX0_PIM2SA);
 169         PCIX_WRITEL(0, PCIX0_PIM2SAH);
 170
 171         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 172         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 173         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 174         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 175         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 176         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 177
 178         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 179         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 180         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 181         PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 182
 183         eieio();
 184 }
 185
 186 static void __init
 187 ocotea_setup_hose(void)
 188 {
 189         struct pci_controller *hose;
 190
 191         /* Configure windows on the PCI-X host bridge */
 192         ocotea_setup_pcix();
 193
 194         hose = pcibios_alloc_controller();
 195
 196         if (!hose)
 197                 return;
 198
 199         hose->first_busno = 0;
 200         hose->last_busno = 0xff;
 201
 202         hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
 203
 204         pci_init_resource(&hose->io_resource,
 205                         OCOTEA_PCI_LOWER_IO,
 206                         OCOTEA_PCI_UPPER_IO,
 207                         IORESOURCE_IO,
 208                         "PCI host bridge");
 209
 210         pci_init_resource(&hose->mem_resources[0],
 211                         OCOTEA_PCI_LOWER_MEM,
 212                         OCOTEA_PCI_UPPER_MEM,
 213                         IORESOURCE_MEM,
 214                         "PCI host bridge");
 215
 216         hose->io_space.start = OCOTEA_PCI_LOWER_IO;
 217         hose->io_space.end = OCOTEA_PCI_UPPER_IO;
 218         hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
 219         hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
 220         hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
 221         isa_io_base = (unsigned long) hose->io_base_virt;
 222
 223         setup_indirect_pci(hose,
 224                         OCOTEA_PCI_CFGA_PLB32,
 225                         OCOTEA_PCI_CFGD_PLB32);
 226         hose->set_cfg_type = 1;
 227
 228         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 229
 230         ppc_md.pci_swizzle = common_swizzle;
 231         ppc_md.pci_map_irq = ocotea_map_irq;
 232 }
 233
 234
 235 TODC_ALLOC();
 236
 237 static void __init
 238 ocotea_early_serial_map(void)
 239 {
 240         struct uart_port port;
 241
 242         /* Setup ioremapped serial port access */
 243         memset(&port, 0, sizeof(port));
 244         port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
 245         port.irq = UART0_INT;
 246         port.uartclk = clocks.uart0;
 247         port.regshift = 0;
 248         port.iotype = UPIO_MEM;
 249         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 250         port.line = 0;
 251
 252         if (early_serial_setup(&port) != 0) {
 253                 printk("Early serial init of port 0 failed\n");
 254         }
 255
 256 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 257         /* Configure debug serial access */
 258         gen550_init(0, &port);
 259
 260         /* Purge TLB entry added in head_44x.S for early serial access */
 261         _tlbie(UART0_IO_BASE, 0);
 262 #endif
 263
 264         port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
 265         port.irq = UART1_INT;
 266         port.uartclk = clocks.uart1;
 267         port.line = 1;
 268
 269         if (early_serial_setup(&port) != 0) {
 270                 printk("Early serial init of port 1 failed\n");
 271         }
 272
 273 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 274         /* Configure debug serial access */
 275         gen550_init(1, &port);
 276 #endif
 277 }
 278
 279 static void __init
 280 ocotea_setup_arch(void)
 281 {
 282         ocotea_set_emacdata();
 283
 284         ibm440gx_tah_enable();
 285
 286         /*
 287          * Determine various clocks.
 288          * To be completely correct we should get SysClk
 289          * from FPGA, because it can be changed by on-board switches
 290          * --ebs
 291          */
 292         ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200);
 293         ocp_sys_info.opb_bus_freq = clocks.opb;
 294
 295         /* Setup TODC access */
 296         TODC_INIT(TODC_TYPE_DS1743,
 297                         0,
 298                         0,
 299                         ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
 300                         8);
 301
 302         /* init to some ~sane value until calibrate_delay() runs */
 303         loops_per_jiffy = 50000000/HZ;
 304
 305         /* Setup PCI host bridge */
 306         ocotea_setup_hose();
 307
 308 #ifdef CONFIG_BLK_DEV_INITRD
 309         if (initrd_start)
 310                 ROOT_DEV = Root_RAM0;
 311         else
 312 #endif
 313 #ifdef CONFIG_ROOT_NFS
 314                 ROOT_DEV = Root_NFS;
 315 #else
 316                 ROOT_DEV = Root_HDA1;
 317 #endif
 318
 319         ocotea_early_serial_map();
 320
 321         /* Identify the system */
 322         printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
 323 }
 324
 325 static void __init ocotea_init(void)
 326 {
 327         ibm440gx_l2c_setup(&clocks);
 328 }
 329
 330 void __init platform_init(unsigned long r3, unsigned long r4,
 331                 unsigned long r5, unsigned long r6, unsigned long r7)
 332 {
 333         ibm440gx_platform_init(r3, r4, r5, r6, r7);
 334
 335         ppc_md.setup_arch = ocotea_setup_arch;
 336         ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
 337         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 338
 339         ppc_md.calibrate_decr = ocotea_calibrate_decr;
 340         ppc_md.time_init = todc_time_init;
 341         ppc_md.set_rtc_time = todc_set_rtc_time;
 342         ppc_md.get_rtc_time = todc_get_rtc_time;
 343
 344         ppc_md.nvram_read_val = todc_direct_read_val;
 345         ppc_md.nvram_write_val = todc_direct_write_val;
 346 #ifdef CONFIG_KGDB
 347         ppc_md.early_serial_map = ocotea_early_serial_map;
 348 #endif
 349         ppc_md.init = ocotea_init;
 350 }