arch/ppc/platforms/4xx/taishan.c

   1 /*
   2  * arch/ppc/platforms/4xx/taishan.c
   3  *
   4  * AMCC Taishan board specific routines
   5  *
   6  * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/types.h>
  22 #include <linux/major.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/console.h>
  25 #include <linux/delay.h>
  26 #include <linux/initrd.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/tty.h>
  30 #include <linux/serial.h>
  31 #include <linux/serial_core.h>
  32 #include <linux/serial_8250.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/mtd/partitions.h>
  35 #include <linux/mtd/nand.h>
  36 #include <linux/mtd/ndfc.h>
  37 #include <linux/mtd/physmap.h>
  38
  39 #include <asm/machdep.h>
  40 #include <asm/ocp.h>
  41 #include <asm/bootinfo.h>
  42 #include <asm/ppcboot.h>
  43
  44 #include <syslib/gen550.h>
  45 #include <syslib/ibm440gx_common.h>
  46
  47 extern bd_t __res;
  48
  49 static struct ibm44x_clocks clocks __initdata;
  50
  51 /*
  52  * NOR FLASH configuration (using mtd physmap driver)
  53  */
  54
  55 /* start will be added dynamically, end is always fixed */
  56 static struct resource taishan_nor_resource = {
  57         .start = TAISHAN_FLASH_ADDR,
  58         .end   = 0x1ffffffffULL,
  59         .flags = IORESOURCE_MEM,
  60 };
  61
  62 #define RW_PART0_OF     0
  63 #define RW_PART0_SZ     0x180000
  64 #define RW_PART1_SZ     0x200000
  65 /* Partition 2 will be autosized dynamically... */
  66 #define RW_PART3_SZ     0x80000
  67 #define RW_PART4_SZ     0x40000
  68
  69 static struct mtd_partition taishan_nor_parts[] = {
  70         {
  71                 .name = "kernel",
  72                 .offset = 0,
  73                 .size = RW_PART0_SZ
  74         },
  75         {
  76                 .name = "root",
  77                 .offset = MTDPART_OFS_APPEND,
  78                 .size = RW_PART1_SZ,
  79         },
  80         {
  81                 .name = "user",
  82                 .offset = MTDPART_OFS_APPEND,
  83 /*              .size = RW_PART2_SZ */ /* will be adjusted dynamically */
  84         },
  85         {
  86                 .name = "env",
  87                 .offset = MTDPART_OFS_APPEND,
  88                 .size = RW_PART3_SZ,
  89         },
  90         {
  91                 .name = "u-boot",
  92                 .offset = MTDPART_OFS_APPEND,
  93                 .size = RW_PART4_SZ,
  94         }
  95 };
  96
  97 static struct physmap_flash_data taishan_nor_data = {
  98         .width          = 4,
  99         .parts          = taishan_nor_parts,
 100         .nr_parts       = ARRAY_SIZE(taishan_nor_parts),
 101 };
 102
 103 static struct platform_device taishan_nor_device = {
 104         .name           = "physmap-flash",
 105         .id             = 0,
 106         .dev = {
 107                         .platform_data = &taishan_nor_data,
 108                 },
 109         .num_resources  = 1,
 110         .resource       = &taishan_nor_resource,
 111 };
 112
 113 static int taishan_setup_flash(void)
 114 {
 115         /*
 116          * Adjust partition 2 to flash size
 117          */
 118         taishan_nor_parts[2].size = __res.bi_flashsize -
 119                 RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
 120
 121         platform_device_register(&taishan_nor_device);
 122
 123         return 0;
 124 }
 125 arch_initcall(taishan_setup_flash);
 126
 127 static void __init
 128 taishan_calibrate_decr(void)
 129 {
 130         unsigned int freq;
 131
 132         if (mfspr(SPRN_CCR1) & CCR1_TCS)
 133                 freq = TAISHAN_TMR_CLK;
 134         else
 135                 freq = clocks.cpu;
 136
 137         ibm44x_calibrate_decr(freq);
 138 }
 139
 140 static int
 141 taishan_show_cpuinfo(struct seq_file *m)
 142 {
 143         seq_printf(m, "vendor\t\t: AMCC\n");
 144         seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
 145         ibm440gx_show_cpuinfo(m);
 146         return 0;
 147 }
 148
 149 static inline int
 150 taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 151 {
 152         static char pci_irq_table[][4] =
 153         /*
 154          *      PCI IDSEL/INTPIN->INTLINE
 155          *         A   B   C   D
 156          */
 157         {
 158                 { 23, 24, 25, 26 },     /* IDSEL 1 - PCI Slot 0 */
 159                 { 24, 25, 26, 23 },     /* IDSEL 2 - PCI Slot 1 */
 160         };
 161
 162         const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
 163         return PCI_IRQ_TABLE_LOOKUP;
 164 }
 165
 166 static void __init taishan_set_emacdata(void)
 167 {
 168         struct ocp_def *def;
 169         struct ocp_func_emac_data *emacdata;
 170         int i;
 171
 172         /* Set phy_map, phy_mode, and mac_addr for each EMAC */
 173         for (i=2; i<4; i++) {
 174                 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
 175                 emacdata = def->additions;
 176                 if (i < 2) {
 177                         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 178                         emacdata->phy_mode = PHY_MODE_SMII;
 179                 } else {
 180                         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 181                         emacdata->phy_mode = PHY_MODE_RGMII;
 182                 }
 183                 if (i == 0)
 184                         memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
 185                 else if (i == 1)
 186                         memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
 187                 else if (i == 2)
 188                         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 189                 else if (i == 3)
 190                         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 191         }
 192 }
 193
 194 #define PCIX_READW(offset) \
 195         (readw(pcix_reg_base+offset))
 196
 197 #define PCIX_WRITEW(value, offset) \
 198         (writew(value, pcix_reg_base+offset))
 199
 200 #define PCIX_WRITEL(value, offset) \
 201         (writel(value, pcix_reg_base+offset))
 202
 203 /*
 204  * FIXME: This is only here to "make it work".  This will move
 205  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 206  * configuration library. -Matt
 207  */
 208 static void __init
 209 taishan_setup_pcix(void)
 210 {
 211         void *pcix_reg_base;
 212
 213         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 214
 215         /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 216         PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 217
 218         /* Disable all windows */
 219         PCIX_WRITEL(0, PCIX0_POM0SA);
 220         PCIX_WRITEL(0, PCIX0_POM1SA);
 221         PCIX_WRITEL(0, PCIX0_POM2SA);
 222         PCIX_WRITEL(0, PCIX0_PIM0SA);
 223         PCIX_WRITEL(0, PCIX0_PIM0SAH);
 224         PCIX_WRITEL(0, PCIX0_PIM1SA);
 225         PCIX_WRITEL(0, PCIX0_PIM2SA);
 226         PCIX_WRITEL(0, PCIX0_PIM2SAH);
 227
 228         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 229         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 230         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 231         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 232         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 233         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 234
 235         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 236         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 237         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 238         PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 239         PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
 240
 241         iounmap(pcix_reg_base);
 242
 243         eieio();
 244 }
 245
 246 static void __init
 247 taishan_setup_hose(void)
 248 {
 249         struct pci_controller *hose;
 250
 251         /* Configure windows on the PCI-X host bridge */
 252         taishan_setup_pcix();
 253
 254         hose = pcibios_alloc_controller();
 255
 256         if (!hose)
 257                 return;
 258
 259         hose->first_busno = 0;
 260         hose->last_busno = 0xff;
 261
 262         hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
 263
 264         pci_init_resource(&hose->io_resource,
 265                         TAISHAN_PCI_LOWER_IO,
 266                         TAISHAN_PCI_UPPER_IO,
 267                         IORESOURCE_IO,
 268                         "PCI host bridge");
 269
 270         pci_init_resource(&hose->mem_resources[0],
 271                         TAISHAN_PCI_LOWER_MEM,
 272                         TAISHAN_PCI_UPPER_MEM,
 273                         IORESOURCE_MEM,
 274                         "PCI host bridge");
 275
 276         hose->io_space.start = TAISHAN_PCI_LOWER_IO;
 277         hose->io_space.end = TAISHAN_PCI_UPPER_IO;
 278         hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
 279         hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
 280         hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
 281         isa_io_base = (unsigned long) hose->io_base_virt;
 282
 283         setup_indirect_pci(hose,
 284                         TAISHAN_PCI_CFGA_PLB32,
 285                         TAISHAN_PCI_CFGD_PLB32);
 286         hose->set_cfg_type = 1;
 287
 288         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 289
 290         ppc_md.pci_swizzle = common_swizzle;
 291         ppc_md.pci_map_irq = taishan_map_irq;
 292 }
 293
 294
 295 static void __init
 296 taishan_early_serial_map(void)
 297 {
 298         struct uart_port port;
 299
 300         /* Setup ioremapped serial port access */
 301         memset(&port, 0, sizeof(port));
 302         port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
 303         port.irq = UART0_INT;
 304         port.uartclk = clocks.uart0;
 305         port.regshift = 0;
 306         port.iotype = UPIO_MEM;
 307         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 308         port.line = 0;
 309
 310         if (early_serial_setup(&port) != 0)
 311                 printk("Early serial init of port 0 failed\n");
 312
 313 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 314         /* Configure debug serial access */
 315         gen550_init(0, &port);
 316
 317         /* Purge TLB entry added in head_44x.S for early serial access */
 318         _tlbie(UART0_IO_BASE, 0);
 319 #endif
 320
 321         port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
 322         port.irq = UART1_INT;
 323         port.uartclk = clocks.uart1;
 324         port.line = 1;
 325
 326         if (early_serial_setup(&port) != 0)
 327                 printk("Early serial init of port 1 failed\n");
 328
 329 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 330         /* Configure debug serial access */
 331         gen550_init(1, &port);
 332 #endif
 333 }
 334
 335 static void __init
 336 taishan_setup_arch(void)
 337 {
 338         taishan_set_emacdata();
 339
 340         ibm440gx_tah_enable();
 341
 342         /*
 343          * Determine various clocks.
 344          * To be completely correct we should get SysClk
 345          * from FPGA, because it can be changed by on-board switches
 346          * --ebs
 347          */
 348         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 349         ocp_sys_info.opb_bus_freq = clocks.opb;
 350
 351         /* init to some ~sane value until calibrate_delay() runs */
 352         loops_per_jiffy = 50000000/HZ;
 353
 354         /* Setup PCI host bridge */
 355         taishan_setup_hose();
 356
 357 #ifdef CONFIG_BLK_DEV_INITRD
 358         if (initrd_start)
 359                 ROOT_DEV = Root_RAM0;
 360         else
 361 #endif
 362 #ifdef CONFIG_ROOT_NFS
 363                 ROOT_DEV = Root_NFS;
 364 #else
 365                 ROOT_DEV = Root_HDA1;
 366 #endif
 367
 368         taishan_early_serial_map();
 369
 370         /* Identify the system */
 371         printk("AMCC PowerPC 440GX Taishan Platform\n");
 372 }
 373
 374 static void __init taishan_init(void)
 375 {
 376         ibm440gx_l2c_setup(&clocks);
 377 }
 378
 379 void __init platform_init(unsigned long r3, unsigned long r4,
 380                 unsigned long r5, unsigned long r6, unsigned long r7)
 381 {
 382         ibm44x_platform_init(r3, r4, r5, r6, r7);
 383
 384         ppc_md.setup_arch = taishan_setup_arch;
 385         ppc_md.show_cpuinfo = taishan_show_cpuinfo;
 386         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 387
 388         ppc_md.calibrate_decr = taishan_calibrate_decr;
 389
 390 #ifdef CONFIG_KGDB
 391         ppc_md.early_serial_map = taishan_early_serial_map;
 392 #endif
 393         ppc_md.init = taishan_init;
 394 }
 395