arch/ppc/platforms/chestnut.c

   1 /*
   2  * Board setup routines for IBM Chestnut
   3  *
   4  * Author: <source@mvista.com>
   5  *
   6  * <2004> (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/stddef.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/kdev_t.h>
  18 #include <linux/major.h>
  19 #include <linux/blkdev.h>
  20 #include <linux/console.h>
  21 #include <linux/root_dev.h>
  22 #include <linux/initrd.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/serial.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/serial_8250.h>
  28 #include <linux/mtd/physmap.h>
  29 #include <asm/system.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/page.h>
  32 #include <asm/time.h>
  33 #include <asm/dma.h>
  34 #include <asm/io.h>
  35 #include <asm/hw_irq.h>
  36 #include <asm/machdep.h>
  37 #include <asm/kgdb.h>
  38 #include <asm/bootinfo.h>
  39 #include <asm/mv64x60.h>
  40 #include <platforms/chestnut.h>
  41
  42 static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
  43 static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
  44
  45 static mv64x60_handle_t bh;
  46
  47 extern void gen550_progress(char *, unsigned short);
  48 extern void gen550_init(int, struct uart_port *);
  49 extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
  50
  51 #define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
  52                                 BIT(MV64x60_CPU2DEV_1_WIN) | \
  53                                 BIT(MV64x60_CPU2DEV_2_WIN) | \
  54                                 BIT(MV64x60_CPU2DEV_3_WIN) | \
  55                                 BIT(MV64x60_CPU2BOOT_WIN))
  56 /**************************************************************************
  57  * FUNCTION: chestnut_calibrate_decr
  58  *
  59  * DESCRIPTION: initialize decrementer interrupt frequency (used as system
  60  *              timer)
  61  *
  62  ****/
  63 static void __init
  64 chestnut_calibrate_decr(void)
  65 {
  66         ulong freq;
  67
  68         freq = CHESTNUT_BUS_SPEED / 4;
  69
  70         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
  71                 freq/1000000, freq%1000000);
  72
  73         tb_ticks_per_jiffy = freq / HZ;
  74         tb_to_us = mulhwu_scale_factor(freq, 1000000);
  75 }
  76
  77 static int
  78 chestnut_show_cpuinfo(struct seq_file *m)
  79 {
  80         seq_printf(m, "vendor\t\t: IBM\n");
  81         seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
  82
  83         return 0;
  84 }
  85
  86 /**************************************************************************
  87  * FUNCTION: chestnut_find_end_of_memory
  88  *
  89  * DESCRIPTION: ppc_md memory size callback
  90  *
  91  ****/
  92 unsigned long __init
  93 chestnut_find_end_of_memory(void)
  94 {
  95         static int  mem_size = 0;
  96
  97         if (mem_size == 0) {
  98                 mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
  99                                 MV64x60_TYPE_MV64460);
 100         }
 101         return mem_size;
 102 }
 103
 104 #if defined(CONFIG_SERIAL_8250)
 105 static void __init
 106 chestnut_early_serial_map(void)
 107 {
 108         struct uart_port port;
 109
 110         /* Setup serial port access */
 111         memset(&port, 0, sizeof(port));
 112         port.uartclk = BASE_BAUD * 16;
 113         port.irq = UART0_INT;
 114         port.flags = STD_COM_FLAGS | UPF_IOREMAP;
 115         port.iotype = UPIO_MEM;
 116         port.mapbase = CHESTNUT_UART0_IO_BASE;
 117         port.regshift = 0;
 118
 119         if (early_serial_setup(&port) != 0)
 120                 printk("Early serial init of port 0 failed\n");
 121
 122         /* Assume early_serial_setup() doesn't modify serial_req */
 123         port.line = 1;
 124         port.irq = UART1_INT;
 125         port.mapbase = CHESTNUT_UART1_IO_BASE;
 126
 127         if (early_serial_setup(&port) != 0)
 128                 printk("Early serial init of port 1 failed\n");
 129 }
 130 #endif
 131
 132 /**************************************************************************
 133  * FUNCTION: chestnut_map_irq
 134  *
 135  * DESCRIPTION: 0 return since PCI IRQs not needed
 136  *
 137  ****/
 138 static int __init
 139 chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 140 {
 141         static char pci_irq_table[][4] = {
 142                 {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
 143                  CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
 144                 {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
 145                  CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
 146                 {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
 147                  CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
 148                 {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
 149                  CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
 150         };
 151         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 152
 153         return PCI_IRQ_TABLE_LOOKUP;
 154 }
 155
 156
 157 /**************************************************************************
 158  * FUNCTION: chestnut_setup_bridge
 159  *
 160  * DESCRIPTION: initalize board-specific settings on the MV64360
 161  *
 162  ****/
 163 static void __init
 164 chestnut_setup_bridge(void)
 165 {
 166         struct mv64x60_setup_info       si;
 167         int i;
 168
 169         if ( ppc_md.progress )
 170                 ppc_md.progress("chestnut_setup_bridge: enter", 0);
 171
 172         memset(&si, 0, sizeof(si));
 173
 174         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 175
 176         /* setup only PCI bus 0 (bus 1 not used) */
 177         si.pci_0.enable_bus = 1;
 178         si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
 179         si.pci_0.pci_io.pci_base_hi = 0;
 180         si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
 181         si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
 182         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 183         si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
 184         si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
 185         si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
 186         si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
 187         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 188         si.pci_0.pci_cmd_bits = 0;
 189         si.pci_0.latency_timer = 0x80;
 190
 191         for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
 192 #if defined(CONFIG_NOT_COHERENT_CACHE)
 193                 si.cpu_prot_options[i] = 0;
 194                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 195                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 196                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 197
 198                 si.pci_1.acc_cntl_options[i] =
 199                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 200                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 201                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 202                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 203 #else
 204                 si.cpu_prot_options[i] = 0;
 205                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 206                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 207                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 208
 209                 si.pci_1.acc_cntl_options[i] =
 210                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 211                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 212                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 213                     MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 214 #endif
 215         }
 216
 217         /* Lookup host bridge - on CPU 0 - no SMP support */
 218         if (mv64x60_init(&bh, &si)) {
 219                 printk("\n\nPCI Bridge initialization failed!\n");
 220         }
 221
 222         pci_dram_offset = 0;
 223         ppc_md.pci_swizzle = common_swizzle;
 224         ppc_md.pci_map_irq = chestnut_map_irq;
 225         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 226
 227         mv64x60_set_bus(&bh, 0, 0);
 228         bh.hose_a->first_busno = 0;
 229         bh.hose_a->last_busno = 0xff;
 230         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 231 }
 232
 233 void __init
 234 chestnut_setup_peripherals(void)
 235 {
 236         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 237                         CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
 238         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 239
 240         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 241                         CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
 242         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 243
 244         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 245                         CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
 246         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 247         cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
 248
 249         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 250                         CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
 251         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 252
 253         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 254                         CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
 255         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 256
 257         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 258                         CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 259         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 260
 261 #ifdef CONFIG_NOT_COHERENT_CACHE
 262         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
 263 #else
 264         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 265 #endif
 266         sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 267         memset(sram_base, 0, MV64360_SRAM_SIZE);
 268
 269         /*
 270          * Configure MPP pins for PCI DMA
 271          *
 272          * PCI Slot     GNT pin         REQ pin
 273          *      0       MPP16           MPP17
 274          *      1       MPP18           MPP19
 275          *      2       MPP20           MPP21
 276          *      3       MPP22           MPP23
 277          */
 278         mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
 279                         (0x1 << 0)  |   /* MPPSel16 PCI0_GNT[0] */
 280                         (0x1 << 4)  |   /* MPPSel17 PCI0_REQ[0] */
 281                         (0x1 << 8)  |   /* MPPSel18 PCI0_GNT[1] */
 282                         (0x1 << 12) |   /* MPPSel19 PCI0_REQ[1] */
 283                         (0x1 << 16) |   /* MPPSel20 PCI0_GNT[2] */
 284                         (0x1 << 20) |   /* MPPSel21 PCI0_REQ[2] */
 285                         (0x1 << 24) |   /* MPPSel22 PCI0_GNT[3] */
 286                         (0x1 << 28));   /* MPPSel23 PCI0_REQ[3] */
 287         /*
 288          * Set unused MPP pins for output, as per schematic note
 289          *
 290          * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
 291          *              MPP09, MPP10, MPP13, MPP14, MPP15
 292          */
 293         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
 294                         (0xf << 4)  |   /* MPPSel01 GPIO[1] */
 295                         (0xf << 8)  |   /* MPPSel02 GPIO[2] */
 296                         (0xf << 16) |   /* MPPSel04 GPIO[4] */
 297                         (0xf << 20) |   /* MPPSel05 GPIO[5] */
 298                         (0xf << 24));   /* MPPSel06 GPIO[6] */
 299         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
 300                         (0xf << 4)  |   /* MPPSel09 GPIO[9] */
 301                         (0xf << 8)  |   /* MPPSel10 GPIO[10] */
 302                         (0xf << 20) |   /* MPPSel13 GPIO[13] */
 303                         (0xf << 24) |   /* MPPSel14 GPIO[14] */
 304                         (0xf << 28));   /* MPPSel15 GPIO[15] */
 305         mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
 306                         BIT(1)  | BIT(2)  | BIT(4)  | BIT(5)  | BIT(6)  |
 307                         BIT(9)  | BIT(10) | BIT(13) | BIT(14) | BIT(15));
 308
 309         /*
 310          * Configure the following MPP pins to indicate a level
 311          * triggered interrupt
 312          *
 313          * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
 314          * MPP25 - UART A  (high)
 315          * MPP26 - UART B  (high)
 316          * MPP28 - PCI Slot 3 (low)
 317          * MPP29 - PCI Slot 2 (low)
 318          * MPP30 - PCI Slot 1 (low)
 319          * MPP31 - PCI Slot 0 (low)
 320          */
 321         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
 322                         BIT(3) | BIT(2) | BIT(1) | BIT(0)        | /* MPP 24 */
 323                         BIT(7) | BIT(6) | BIT(5) | BIT(4)        | /* MPP 25 */
 324                         BIT(11) | BIT(10) | BIT(9) | BIT(8)      | /* MPP 26 */
 325                         BIT(19) | BIT(18) | BIT(17) | BIT(16)    | /* MPP 28 */
 326                         BIT(23) | BIT(22) | BIT(21) | BIT(20)    | /* MPP 29 */
 327                         BIT(27) | BIT(26) | BIT(25) | BIT(24)    | /* MPP 30 */
 328                         BIT(31) | BIT(30) | BIT(29) | BIT(28));    /* MPP 31 */
 329
 330         /*
 331          * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
 332          * 31 (low) interrupt polarity input signal and level triggered
 333          */
 334         mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
 335         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
 336                         BIT(28) | BIT(29) | BIT(30) | BIT(31));
 337         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
 338                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 339                         BIT(31));
 340
 341         /* Config GPP interrupt controller to respond to level trigger */
 342         mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
 343
 344         /*
 345          * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
 346          */
 347         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
 348                         ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 349                           BIT(31)));
 350         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
 351                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 352                         BIT(31));
 353
 354         /*
 355          * Dismiss and then enable interrupt on CPU #0 high cause register
 356          * BIT27 summarizes GPP interrupts 24-31
 357          */
 358         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
 359
 360         if (ppc_md.progress)
 361                 ppc_md.progress("chestnut_setup_bridge: exit", 0);
 362 }
 363
 364 /**************************************************************************
 365  * FUNCTION: chestnut_setup_arch
 366  *
 367  * DESCRIPTION: ppc_md machine configuration callback
 368  *
 369  ****/
 370 static void __init
 371 chestnut_setup_arch(void)
 372 {
 373         if (ppc_md.progress)
 374                 ppc_md.progress("chestnut_setup_arch: enter", 0);
 375
 376         /* init to some ~sane value until calibrate_delay() runs */
 377         loops_per_jiffy = 50000000 / HZ;
 378
 379         /* if the time base value is greater than bus freq/4 (the TB and
 380         * decrementer tick rate) + signed integer rollover value, we
 381         * can spend a fair amount of time waiting for the rollover to
 382         * happen.  To get around this, initialize the time base register
 383         * to a "safe" value.
 384         */
 385         set_tb(0, 0);
 386
 387 #ifdef CONFIG_BLK_DEV_INITRD
 388         if (initrd_start)
 389                 ROOT_DEV = Root_RAM0;
 390         else
 391 #endif
 392 #ifdef CONFIG_ROOT_NFS
 393                 ROOT_DEV = Root_NFS;
 394 #else
 395                 ROOT_DEV = Root_SDA2;
 396 #endif
 397
 398         /*
 399         * Set up the L2CR register.
 400         */
 401         _set_L2CR(_get_L2CR() | L2CR_L2E);
 402
 403         chestnut_setup_bridge();
 404         chestnut_setup_peripherals();
 405
 406 #ifdef CONFIG_DUMMY_CONSOLE
 407         conswitchp = &dummy_con;
 408 #endif
 409
 410 #if defined(CONFIG_SERIAL_8250)
 411         chestnut_early_serial_map();
 412 #endif
 413
 414         /* Identify the system */
 415         printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
 416         printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
 417                 " (source@mvista.com)\n");
 418
 419         if (ppc_md.progress)
 420                 ppc_md.progress("chestnut_setup_arch: exit", 0);
 421 }
 422
 423 #ifdef CONFIG_MTD_PHYSMAP
 424 static struct mtd_partition ptbl;
 425
 426 static int __init
 427 chestnut_setup_mtd(void)
 428 {
 429         memset(&ptbl, 0, sizeof(ptbl));
 430
 431         ptbl.name = "User FS";
 432         ptbl.size = CHESTNUT_32BIT_SIZE;
 433
 434         physmap_map.size = CHESTNUT_32BIT_SIZE;
 435         physmap_set_partitions(&ptbl, 1);
 436         return 0;
 437 }
 438
 439 arch_initcall(chestnut_setup_mtd);
 440 #endif
 441
 442 /**************************************************************************
 443  * FUNCTION: chestnut_restart
 444  *
 445  * DESCRIPTION: ppc_md machine reset callback
 446  *              reset the board via the CPLD command register
 447  *
 448  ****/
 449 static void
 450 chestnut_restart(char *cmd)
 451 {
 452         volatile ulong i = 10000000;
 453
 454         local_irq_disable();
 455
 456         /*
 457          * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
 458          *
 459          * MPP24 - board reset
 460          */
 461         writeb(0x1, cpld_base + 3);
 462
 463         /* GPP pin tied to MPP earlier */
 464         mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
 465
 466         while (i-- > 0);
 467         panic("restart failed\n");
 468 }
 469
 470 static void
 471 chestnut_halt(void)
 472 {
 473         local_irq_disable();
 474         for (;;);
 475         /* NOTREACHED */
 476 }
 477
 478 static void
 479 chestnut_power_off(void)
 480 {
 481         chestnut_halt();
 482         /* NOTREACHED */
 483 }
 484
 485 /**************************************************************************
 486  * FUNCTION: chestnut_map_io
 487  *
 488  * DESCRIPTION: configure fixed memory-mapped IO
 489  *
 490  ****/
 491 static void __init
 492 chestnut_map_io(void)
 493 {
 494 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 495         io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
 496                 _PAGE_IO);
 497 #endif
 498 }
 499
 500 /**************************************************************************
 501  * FUNCTION: chestnut_set_bat
 502  *
 503  * DESCRIPTION: configures a (temporary) bat mapping for early access to
 504  *              device I/O
 505  *
 506  ****/
 507 static __inline__ void
 508 chestnut_set_bat(void)
 509 {
 510         mb();
 511         mtspr(SPRN_DBAT3U, 0xf0001ffe);
 512         mtspr(SPRN_DBAT3L, 0xf000002a);
 513         mb();
 514 }
 515
 516 /**************************************************************************
 517  * FUNCTION: platform_init
 518  *
 519  * DESCRIPTION: main entry point for configuring board-specific machine
 520  *              callbacks
 521  *
 522  ****/
 523 void __init
 524 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 525               unsigned long r6, unsigned long r7)
 526 {
 527         parse_bootinfo(find_bootinfo());
 528
 529         /* Copy the kernel command line arguments to a safe place. */
 530
 531         if (r6) {
 532                 *(char *) (r7 + KERNELBASE) = 0;
 533                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 534         }
 535
 536         isa_mem_base = 0;
 537
 538         ppc_md.setup_arch = chestnut_setup_arch;
 539         ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
 540         ppc_md.init_IRQ = mv64360_init_irq;
 541         ppc_md.get_irq = mv64360_get_irq;
 542         ppc_md.init = NULL;
 543
 544         ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
 545         ppc_md.setup_io_mappings  = chestnut_map_io;
 546
 547         ppc_md.restart = chestnut_restart;
 548         ppc_md.power_off = chestnut_power_off;
 549         ppc_md.halt = chestnut_halt;
 550
 551         ppc_md.time_init = NULL;
 552         ppc_md.set_rtc_time = NULL;
 553         ppc_md.get_rtc_time = NULL;
 554         ppc_md.calibrate_decr = chestnut_calibrate_decr;
 555
 556         ppc_md.nvram_read_val = NULL;
 557         ppc_md.nvram_write_val = NULL;
 558
 559         ppc_md.heartbeat = NULL;
 560
 561         bh.p_base = CONFIG_MV64X60_NEW_BASE;
 562
 563         chestnut_set_bat();
 564
 565 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 566         ppc_md.progress = gen550_progress;
 567 #endif
 568 #if defined(CONFIG_KGDB)
 569         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 570 #endif
 571
 572         if (ppc_md.progress)
 573                 ppc_md.progress("chestnut_init(): exit", 0);
 574 }