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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / char / drm / i915_irq.c
blob023ce66ef3ab2f8858b3946f9777484836c8a799
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33
34 #define USER_INT_FLAG (1<<1)
35 #define VSYNC_PIPEB_FLAG (1<<5)
36 #define VSYNC_PIPEA_FLAG (1<<7)
37
38 #define MAX_NOPID ((u32)~0)
39
40 /**
41 * i915_get_pipe - return the the pipe associated with a given plane
42 * @dev: DRM device
43 * @plane: plane to look for
44 *
45 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
46 * rather than a pipe number, since they may not always be equal. This routine
47 * maps the given @plane back to a pipe number.
48 */
49 static int
50 i915_get_pipe(struct drm_device *dev, int plane)
51 {
52 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
53 u32 dspcntr;
54
55 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
56
57 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
58 }
59
60 /**
61 * i915_get_plane - return the the plane associated with a given pipe
62 * @dev: DRM device
63 * @pipe: pipe to look for
64 *
65 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
66 * rather than a plane number, since they may not always be equal. This routine
67 * maps the given @pipe back to a plane number.
68 */
69 static int
70 i915_get_plane(struct drm_device *dev, int pipe)
71 {
72 if (i915_get_pipe(dev, 0) == pipe)
73 return 0;
74 return 1;
75 }
76
77 /**
78 * i915_pipe_enabled - check if a pipe is enabled
79 * @dev: DRM device
80 * @pipe: pipe to check
81 *
82 * Reading certain registers when the pipe is disabled can hang the chip.
83 * Use this routine to make sure the PLL is running and the pipe is active
84 * before reading such registers if unsure.
85 */
86 static int
87 i915_pipe_enabled(struct drm_device *dev, int pipe)
88 {
89 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
90 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
91
92 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
93 return 1;
94
95 return 0;
96 }
97
98 /**
99 * Emit a synchronous flip.
100 *
101 * This function must be called with the drawable spinlock held.
102 */
103 static void
104 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
105 int plane)
106 {
107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
108 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
109 u16 x1, y1, x2, y2;
110 int pf_planes = 1 << plane;
111
112 /* If the window is visible on the other plane, we have to flip on that
113 * plane as well.
114 */
115 if (plane == 1) {
116 x1 = sarea_priv->planeA_x;
117 y1 = sarea_priv->planeA_y;
118 x2 = x1 + sarea_priv->planeA_w;
119 y2 = y1 + sarea_priv->planeA_h;
120 } else {
121 x1 = sarea_priv->planeB_x;
122 y1 = sarea_priv->planeB_y;
123 x2 = x1 + sarea_priv->planeB_w;
124 y2 = y1 + sarea_priv->planeB_h;
125 }
126
127 if (x2 > 0 && y2 > 0) {
128 int i, num_rects = drw->num_rects;
129 struct drm_clip_rect *rect = drw->rects;
130
131 for (i = 0; i < num_rects; i++)
132 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
133 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
134 pf_planes = 0x3;
135
136 break;
137 }
138 }
139
140 i915_dispatch_flip(dev, pf_planes, 1);
141 }
142
143 /**
144 * Emit blits for scheduled buffer swaps.
145 *
146 * This function will be called with the HW lock held.
147 */
148 static void i915_vblank_tasklet(struct drm_device *dev)
149 {
150 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
151 struct list_head *list, *tmp, hits, *hit;
152 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
153 unsigned counter[2];
154 struct drm_drawable_info *drw;
155 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
156 u32 cpp = dev_priv->cpp, offsets[3];
157 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
158 XY_SRC_COPY_BLT_WRITE_ALPHA |
159 XY_SRC_COPY_BLT_WRITE_RGB)
160 : XY_SRC_COPY_BLT_CMD;
161 u32 src_pitch = sarea_priv->pitch * cpp;
162 u32 dst_pitch = sarea_priv->pitch * cpp;
163 /* COPY rop (0xcc), map cpp to magic color depth constants */
164 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
165 RING_LOCALS;
166
167 if (sarea_priv->front_tiled) {
168 cmd |= XY_SRC_COPY_BLT_DST_TILED;
169 dst_pitch >>= 2;
170 }
171 if (sarea_priv->back_tiled) {
172 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
173 src_pitch >>= 2;
174 }
175
176 counter[0] = drm_vblank_count(dev, 0);
177 counter[1] = drm_vblank_count(dev, 1);
178
179 DRM_DEBUG("\n");
180
181 INIT_LIST_HEAD(&hits);
182
183 nhits = nrects = 0;
184
185 /* No irqsave/restore necessary. This tasklet may be run in an
186 * interrupt context or normal context, but we don't have to worry
187 * about getting interrupted by something acquiring the lock, because
188 * we are the interrupt context thing that acquires the lock.
189 */
190 spin_lock(&dev_priv->swaps_lock);
191
192 /* Find buffer swaps scheduled for this vertical blank */
193 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
194 drm_i915_vbl_swap_t *vbl_swap =
195 list_entry(list, drm_i915_vbl_swap_t, head);
196 int pipe = i915_get_pipe(dev, vbl_swap->plane);
197
198 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
199 continue;
200
201 list_del(list);
202 dev_priv->swaps_pending--;
203 drm_vblank_put(dev, pipe);
204
205 spin_unlock(&dev_priv->swaps_lock);
206 spin_lock(&dev->drw_lock);
207
208 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
209
210 if (!drw) {
211 spin_unlock(&dev->drw_lock);
212 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
213 spin_lock(&dev_priv->swaps_lock);
214 continue;
215 }
216
217 list_for_each(hit, &hits) {
218 drm_i915_vbl_swap_t *swap_cmp =
219 list_entry(hit, drm_i915_vbl_swap_t, head);
220 struct drm_drawable_info *drw_cmp =
221 drm_get_drawable_info(dev, swap_cmp->drw_id);
222
223 if (drw_cmp &&
224 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
225 list_add_tail(list, hit);
226 break;
227 }
228 }
229
230 spin_unlock(&dev->drw_lock);
231
232 /* List of hits was empty, or we reached the end of it */
233 if (hit == &hits)
234 list_add_tail(list, hits.prev);
235
236 nhits++;
237
238 spin_lock(&dev_priv->swaps_lock);
239 }
240
241 spin_unlock(&dev_priv->swaps_lock);
242
243 if (nhits == 0)
244 return;
245
246 i915_kernel_lost_context(dev);
247
248 upper[0] = upper[1] = 0;
249 slice[0] = max(sarea_priv->planeA_h / nhits, 1);
250 slice[1] = max(sarea_priv->planeB_h / nhits, 1);
251 lower[0] = sarea_priv->planeA_y + slice[0];
252 lower[1] = sarea_priv->planeB_y + slice[0];
253
254 offsets[0] = sarea_priv->front_offset;
255 offsets[1] = sarea_priv->back_offset;
256 offsets[2] = sarea_priv->third_offset;
257 num_pages = sarea_priv->third_handle ? 3 : 2;
258
259 spin_lock(&dev->drw_lock);
260
261 /* Emit blits for buffer swaps, partitioning both outputs into as many
262 * slices as there are buffer swaps scheduled in order to avoid tearing
263 * (based on the assumption that a single buffer swap would always
264 * complete before scanout starts).
265 */
266 for (i = 0; i++ < nhits;
267 upper[0] = lower[0], lower[0] += slice[0],
268 upper[1] = lower[1], lower[1] += slice[1]) {
269 int init_drawrect = 1;
270
271 if (i == nhits)
272 lower[0] = lower[1] = sarea_priv->height;
273
274 list_for_each(hit, &hits) {
275 drm_i915_vbl_swap_t *swap_hit =
276 list_entry(hit, drm_i915_vbl_swap_t, head);
277 struct drm_clip_rect *rect;
278 int num_rects, plane, front, back;
279 unsigned short top, bottom;
280
281 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
282
283 if (!drw)
284 continue;
285
286 plane = swap_hit->plane;
287
288 if (swap_hit->flip) {
289 i915_dispatch_vsync_flip(dev, drw, plane);
290 continue;
291 }
292
293 if (init_drawrect) {
294 int width = sarea_priv->width;
295 int height = sarea_priv->height;
296 if (IS_I965G(dev)) {
297 BEGIN_LP_RING(4);
298
299 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
300 OUT_RING(0);
301 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
302 OUT_RING(0);
303
304 ADVANCE_LP_RING();
305 } else {
306 BEGIN_LP_RING(6);
307
308 OUT_RING(GFX_OP_DRAWRECT_INFO);
309 OUT_RING(0);
310 OUT_RING(0);
311 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
312 OUT_RING(0);
313 OUT_RING(0);
314
315 ADVANCE_LP_RING();
316 }
317
318 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
319
320 init_drawrect = 0;
321 }
322
323 rect = drw->rects;
324 top = upper[plane];
325 bottom = lower[plane];
326
327 front = (dev_priv->sarea_priv->pf_current_page >>
328 (2 * plane)) & 0x3;
329 back = (front + 1) % num_pages;
330
331 for (num_rects = drw->num_rects; num_rects--; rect++) {
332 int y1 = max(rect->y1, top);
333 int y2 = min(rect->y2, bottom);
334
335 if (y1 >= y2)
336 continue;
337
338 BEGIN_LP_RING(8);
339
340 OUT_RING(cmd);
341 OUT_RING(ropcpp | dst_pitch);
342 OUT_RING((y1 << 16) | rect->x1);
343 OUT_RING((y2 << 16) | rect->x2);
344 OUT_RING(offsets[front]);
345 OUT_RING((y1 << 16) | rect->x1);
346 OUT_RING(src_pitch);
347 OUT_RING(offsets[back]);
348
349 ADVANCE_LP_RING();
350 }
351 }
352 }
353
354 spin_unlock(&dev->drw_lock);
355
356 list_for_each_safe(hit, tmp, &hits) {
357 drm_i915_vbl_swap_t *swap_hit =
358 list_entry(hit, drm_i915_vbl_swap_t, head);
359
360 list_del(hit);
361
362 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
363 }
364 }
365
366 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
367 {
368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
369 unsigned long high_frame;
370 unsigned long low_frame;
371 u32 high1, high2, low, count;
372 int pipe;
373
374 pipe = i915_get_pipe(dev, plane);
375 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
376 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
377
378 if (!i915_pipe_enabled(dev, pipe)) {
379 printk(KERN_ERR "trying to get vblank count for disabled "
380 "pipe %d\n", pipe);
381 return 0;
382 }
383
384 /*
385 * High & low register fields aren't synchronized, so make sure
386 * we get a low value that's stable across two reads of the high
387 * register.
388 */
389 do {
390 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
391 PIPE_FRAME_HIGH_SHIFT);
392 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
393 PIPE_FRAME_LOW_SHIFT);
394 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
395 PIPE_FRAME_HIGH_SHIFT);
396 } while (high1 != high2);
397
398 count = (high1 << 8) | low;
399
400 /* count may be reset by other driver(e.g. 2D driver),
401 we have no way to know if it is wrapped or resetted
402 when count is zero. do a rough guess.
403 */
404 if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
405 dev->last_vblank[pipe] = 0;
406
407 return count;
408 }
409
410 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
411 {
412 struct drm_device *dev = (struct drm_device *) arg;
413 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
414 u32 iir;
415 u32 pipea_stats, pipeb_stats;
416 int vblank = 0;
417
418 iir = I915_READ(I915REG_INT_IDENTITY_R);
419 if (iir == 0) {
420 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
421 iir,
422 I915_READ(I915REG_INT_MASK_R),
423 I915_READ(I915REG_INT_ENABLE_R),
424 I915_READ(I915REG_PIPEASTAT),
425 I915_READ(I915REG_PIPEBSTAT));
426 return IRQ_NONE;
427 }
428
429 /*
430 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
431 * we may get extra interrupts.
432 */
433 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
434 pipea_stats = I915_READ(I915REG_PIPEASTAT);
435 if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
436 I915_VBLANK_INTERRUPT_STATUS))
437 {
438 vblank++;
439 drm_handle_vblank(dev, i915_get_plane(dev, 0));
440 }
441 I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
442 }
443 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
444 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
445 if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
446 I915_VBLANK_INTERRUPT_STATUS))
447 {
448 vblank++;
449 drm_handle_vblank(dev, i915_get_plane(dev, 1));
450 }
451 I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
452 }
453
454 if (dev_priv->sarea_priv)
455 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
456
457 I915_WRITE(I915REG_INT_IDENTITY_R, iir);
458 (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */
459
460 if (iir & I915_USER_INTERRUPT) {
461 DRM_WAKEUP(&dev_priv->irq_queue);
462 }
463 if (vblank) {
464 if (dev_priv->swaps_pending > 0)
465 drm_locked_tasklet(dev, i915_vblank_tasklet);
466 }
467
468 return IRQ_HANDLED;
469 }
470
471 static int i915_emit_irq(struct drm_device *dev)
472 {
473 drm_i915_private_t *dev_priv = dev->dev_private;
474 RING_LOCALS;
475
476 i915_kernel_lost_context(dev);
477
478 DRM_DEBUG("\n");
479
480 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
481
482 if (dev_priv->counter > 0x7FFFFFFFUL)
483 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
484
485 BEGIN_LP_RING(6);
486 OUT_RING(CMD_STORE_DWORD_IDX);
487 OUT_RING(20);
488 OUT_RING(dev_priv->counter);
489 OUT_RING(0);
490 OUT_RING(0);
491 OUT_RING(GFX_OP_USER_INTERRUPT);
492 ADVANCE_LP_RING();
493
494 return dev_priv->counter;
495 }
496
497 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
498 {
499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
500 int ret = 0;
501
502 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
503 READ_BREADCRUMB(dev_priv));
504
505 if (READ_BREADCRUMB(dev_priv) >= irq_nr)
506 return 0;
507
508 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
509
510 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
511 READ_BREADCRUMB(dev_priv) >= irq_nr);
512
513 if (ret == -EBUSY) {
514 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
515 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
516 }
517
518 if (dev_priv->sarea_priv)
519 dev_priv->sarea_priv->last_dispatch =
520 READ_BREADCRUMB(dev_priv);
521 return ret;
522 }
523
524 /* Needs the lock as it touches the ring.
525 */
526 int i915_irq_emit(struct drm_device *dev, void *data,
527 struct drm_file *file_priv)
528 {
529 drm_i915_private_t *dev_priv = dev->dev_private;
530 drm_i915_irq_emit_t *emit = data;
531 int result;
532
533 LOCK_TEST_WITH_RETURN(dev, file_priv);
534
535 if (!dev_priv) {
536 DRM_ERROR("called with no initialization\n");
537 return -EINVAL;
538 }
539
540 result = i915_emit_irq(dev);
541
542 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
543 DRM_ERROR("copy_to_user\n");
544 return -EFAULT;
545 }
546
547 return 0;
548 }
549
550 /* Doesn't need the hardware lock.
551 */
552 int i915_irq_wait(struct drm_device *dev, void *data,
553 struct drm_file *file_priv)
554 {
555 drm_i915_private_t *dev_priv = dev->dev_private;
556 drm_i915_irq_wait_t *irqwait = data;
557
558 if (!dev_priv) {
559 DRM_ERROR("called with no initialization\n");
560 return -EINVAL;
561 }
562
563 return i915_wait_irq(dev, irqwait->irq_seq);
564 }
565
566 int i915_enable_vblank(struct drm_device *dev, int plane)
567 {
568 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
569 int pipe = i915_get_pipe(dev, plane);
570 u32 pipestat_reg = 0;
571 u32 pipestat;
572
573 switch (pipe) {
574 case 0:
575 pipestat_reg = I915REG_PIPEASTAT;
576 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
577 break;
578 case 1:
579 pipestat_reg = I915REG_PIPEBSTAT;
580 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
581 break;
582 default:
583 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
584 pipe);
585 break;
586 }
587
588 if (pipestat_reg)
589 {
590 pipestat = I915_READ (pipestat_reg);
591 /*
592 * Older chips didn't have the start vblank interrupt,
593 * but
594 */
595 if (IS_I965G (dev))
596 pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
597 else
598 pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
599 /*
600 * Clear any pending status
601 */
602 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
603 I915_VBLANK_INTERRUPT_STATUS);
604 I915_WRITE(pipestat_reg, pipestat);
605 }
606 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
607
608 return 0;
609 }
610
611 void i915_disable_vblank(struct drm_device *dev, int plane)
612 {
613 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
614 int pipe = i915_get_pipe(dev, plane);
615 u32 pipestat_reg = 0;
616 u32 pipestat;
617
618 switch (pipe) {
619 case 0:
620 pipestat_reg = I915REG_PIPEASTAT;
621 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
622 break;
623 case 1:
624 pipestat_reg = I915REG_PIPEBSTAT;
625 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
626 break;
627 default:
628 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
629 pipe);
630 break;
631 }
632
633 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
634 if (pipestat_reg)
635 {
636 pipestat = I915_READ (pipestat_reg);
637 pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
638 I915_VBLANK_INTERRUPT_ENABLE);
639 /*
640 * Clear any pending status
641 */
642 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
643 I915_VBLANK_INTERRUPT_STATUS);
644 I915_WRITE(pipestat_reg, pipestat);
645 }
646 }
647
648 static void i915_enable_interrupt (struct drm_device *dev)
649 {
650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
651
652 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
653
654 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
655 dev_priv->irq_enabled = 1;
656 }
657
658 /* Set the vblank monitor pipe
659 */
660 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
661 struct drm_file *file_priv)
662 {
663 drm_i915_private_t *dev_priv = dev->dev_private;
664 drm_i915_vblank_pipe_t *pipe = data;
665
666 if (!dev_priv) {
667 DRM_ERROR("called with no initialization\n");
668 return -EINVAL;
669 }
670
671 if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
672 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
673 return -EINVAL;
674 }
675
676 dev_priv->vblank_pipe = pipe->pipe;
677
678 return 0;
679 }
680
681 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
682 struct drm_file *file_priv)
683 {
684 drm_i915_private_t *dev_priv = dev->dev_private;
685 drm_i915_vblank_pipe_t *pipe = data;
686 u16 flag;
687
688 if (!dev_priv) {
689 DRM_ERROR("called with no initialization\n");
690 return -EINVAL;
691 }
692
693 flag = I915_READ(I915REG_INT_ENABLE_R);
694 pipe->pipe = 0;
695 if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
696 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
697 if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
698 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
699
700 return 0;
701 }
702
703 /**
704 * Schedule buffer swap at given vertical blank.
705 */
706 int i915_vblank_swap(struct drm_device *dev, void *data,
707 struct drm_file *file_priv)
708 {
709 drm_i915_private_t *dev_priv = dev->dev_private;
710 drm_i915_vblank_swap_t *swap = data;
711 drm_i915_vbl_swap_t *vbl_swap;
712 unsigned int pipe, seqtype, curseq, plane;
713 unsigned long irqflags;
714 struct list_head *list;
715 int ret;
716
717 if (!dev_priv) {
718 DRM_ERROR("%s called with no initialization\n", __func__);
719 return -EINVAL;
720 }
721
722 if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {
723 DRM_DEBUG("Rotation not supported\n");
724 return -EINVAL;
725 }
726
727 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
728 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
729 _DRM_VBLANK_FLIP)) {
730 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
731 return -EINVAL;
732 }
733
734 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
735 pipe = i915_get_pipe(dev, plane);
736
737 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
738
739 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
740 DRM_ERROR("Invalid pipe %d\n", pipe);
741 return -EINVAL;
742 }
743
744 spin_lock_irqsave(&dev->drw_lock, irqflags);
745
746 /* It makes no sense to schedule a swap for a drawable that doesn't have
747 * valid information at this point. E.g. this could mean that the X
748 * server is too old to push drawable information to the DRM, in which
749 * case all such swaps would become ineffective.
750 */
751 if (!drm_get_drawable_info(dev, swap->drawable)) {
752 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
753 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
754 return -EINVAL;
755 }
756
757 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
758
759 drm_update_vblank_count(dev, pipe);
760 curseq = drm_vblank_count(dev, pipe);
761
762 if (seqtype == _DRM_VBLANK_RELATIVE)
763 swap->sequence += curseq;
764
765 if ((curseq - swap->sequence) <= (1<<23)) {
766 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
767 swap->sequence = curseq + 1;
768 } else {
769 DRM_DEBUG("Missed target sequence\n");
770 return -EINVAL;
771 }
772 }
773
774 if (swap->seqtype & _DRM_VBLANK_FLIP) {
775 swap->sequence--;
776
777 if ((curseq - swap->sequence) <= (1<<23)) {
778 struct drm_drawable_info *drw;
779
780 LOCK_TEST_WITH_RETURN(dev, file_priv);
781
782 spin_lock_irqsave(&dev->drw_lock, irqflags);
783
784 drw = drm_get_drawable_info(dev, swap->drawable);
785
786 if (!drw) {
787 spin_unlock_irqrestore(&dev->drw_lock,
788 irqflags);
789 DRM_DEBUG("Invalid drawable ID %d\n",
790 swap->drawable);
791 return -EINVAL;
792 }
793
794 i915_dispatch_vsync_flip(dev, drw, plane);
795
796 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
797
798 return 0;
799 }
800 }
801
802 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
803
804 list_for_each(list, &dev_priv->vbl_swaps.head) {
805 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
806
807 if (vbl_swap->drw_id == swap->drawable &&
808 vbl_swap->plane == plane &&
809 vbl_swap->sequence == swap->sequence) {
810 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
811 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
812 DRM_DEBUG("Already scheduled\n");
813 return 0;
814 }
815 }
816
817 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
818
819 if (dev_priv->swaps_pending >= 100) {
820 DRM_DEBUG("Too many swaps queued\n");
821 return -EBUSY;
822 }
823
824 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
825
826 if (!vbl_swap) {
827 DRM_ERROR("Failed to allocate memory to queue swap\n");
828 return -ENOMEM;
829 }
830
831 DRM_DEBUG("\n");
832
833 ret = drm_vblank_get(dev, pipe);
834 if (ret) {
835 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
836 return ret;
837 }
838
839 vbl_swap->drw_id = swap->drawable;
840 vbl_swap->plane = plane;
841 vbl_swap->sequence = swap->sequence;
842 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
843
844 if (vbl_swap->flip)
845 swap->sequence++;
846
847 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
848
849 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
850 dev_priv->swaps_pending++;
851
852 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
853
854 return 0;
855 }
856
857 /* drm_dma.h hooks
858 */
859 void i915_driver_irq_preinstall(struct drm_device * dev)
860 {
861 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
862
863 I915_WRITE16(I915REG_HWSTAM, 0xeffe);
864 I915_WRITE16(I915REG_INT_MASK_R, 0x0);
865 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
866 }
867
868 int i915_driver_irq_postinstall(struct drm_device * dev)
869 {
870 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
871 int ret, num_pipes = 2;
872
873 spin_lock_init(&dev_priv->swaps_lock);
874 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
875 dev_priv->swaps_pending = 0;
876
877 dev_priv->user_irq_refcount = 0;
878 dev_priv->irq_enable_reg = 0;
879
880 ret = drm_vblank_init(dev, num_pipes);
881 if (ret)
882 return ret;
883
884 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
885
886 i915_enable_interrupt(dev);
887 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
888
889 /*
890 * Initialize the hardware status page IRQ location.
891 */
892
893 I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
894 return 0;
895 }
896
897 void i915_driver_irq_uninstall(struct drm_device * dev)
898 {
899 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
900 u32 temp;
901
902 if (!dev_priv)
903 return;
904
905 dev_priv->irq_enabled = 0;
906 I915_WRITE(I915REG_HWSTAM, 0xffffffff);
907 I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
908 I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
909
910 temp = I915_READ(I915REG_PIPEASTAT);
911 I915_WRITE(I915REG_PIPEASTAT, temp);
912 temp = I915_READ(I915REG_PIPEBSTAT);
913 I915_WRITE(I915REG_PIPEBSTAT, temp);
914 temp = I915_READ(I915REG_INT_IDENTITY_R);
915 I915_WRITE(I915REG_INT_IDENTITY_R, temp);
916 }
Mirror for ia64_pv_ops.git