drivers/char/drm/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel Dänzer <michel@daenzer.net>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37
  38 static void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
  39 {
  40         drm_radeon_private_t *dev_priv = dev->dev_private;
  41
  42         if (state)
  43                 dev_priv->irq_enable_reg |= mask;
  44         else
  45                 dev_priv->irq_enable_reg &= ~mask;
  46
  47         RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  48 }
  49
  50 int radeon_enable_vblank(struct drm_device *dev, int crtc)
  51 {
  52         switch (crtc) {
  53         case 0:
  54                 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
  55                 break;
  56         case 1:
  57                 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
  58                 break;
  59         default:
  60                 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  61                           crtc);
  62                 return EINVAL;
  63         }
  64
  65         return 0;
  66 }
  67
  68 void radeon_disable_vblank(struct drm_device *dev, int crtc)
  69 {
  70         switch (crtc) {
  71         case 0:
  72                 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
  73                 break;
  74         case 1:
  75                 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
  76                 break;
  77         default:
  78                 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  79                           crtc);
  80                 break;
  81         }
  82 }
  83
  84 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv)
  85 {
  86         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) &
  87                 (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
  88                  RADEON_CRTC2_VBLANK_STAT);
  89
  90         if (irqs)
  91                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
  92
  93         return irqs;
  94 }
  95
  96 /* Interrupts - Used for device synchronization and flushing in the
  97  * following circumstances:
  98  *
  99  * - Exclusive FB access with hw idle:
 100  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 101  *
 102  * - Frame throttling, NV_fence:
 103  *    - Drop marker irq's into command stream ahead of time.
 104  *    - Wait on irq's with lock *not held*
 105  *    - Check each for termination condition
 106  *
 107  * - Internally in cp_getbuffer, etc:
 108  *    - as above, but wait with lock held???
 109  *
 110  * NOTE: These functions are misleadingly named -- the irq's aren't
 111  * tied to dma at all, this is just a hangover from dri prehistory.
 112  */
 113
 114 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 115 {
 116         struct drm_device *dev = (struct drm_device *) arg;
 117         drm_radeon_private_t *dev_priv =
 118             (drm_radeon_private_t *) dev->dev_private;
 119         u32 stat;
 120
 121         /* Only consider the bits we're interested in - others could be used
 122          * outside the DRM
 123          */
 124         stat = radeon_acknowledge_irqs(dev_priv);
 125         if (!stat)
 126                 return IRQ_NONE;
 127
 128         stat &= dev_priv->irq_enable_reg;
 129
 130         /* SW interrupt */
 131         if (stat & RADEON_SW_INT_TEST)
 132                 DRM_WAKEUP(&dev_priv->swi_queue);
 133
 134         /* VBLANK interrupt */
 135         if (stat & RADEON_CRTC_VBLANK_STAT)
 136                 drm_handle_vblank(dev, 0);
 137         if (stat & RADEON_CRTC2_VBLANK_STAT)
 138                 drm_handle_vblank(dev, 1);
 139
 140         return IRQ_HANDLED;
 141 }
 142
 143 static int radeon_emit_irq(struct drm_device * dev)
 144 {
 145         drm_radeon_private_t *dev_priv = dev->dev_private;
 146         unsigned int ret;
 147         RING_LOCALS;
 148
 149         atomic_inc(&dev_priv->swi_emitted);
 150         ret = atomic_read(&dev_priv->swi_emitted);
 151
 152         BEGIN_RING(4);
 153         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 154         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 155         ADVANCE_RING();
 156         COMMIT_RING();
 157
 158         return ret;
 159 }
 160
 161 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 162 {
 163         drm_radeon_private_t *dev_priv =
 164             (drm_radeon_private_t *) dev->dev_private;
 165         int ret = 0;
 166
 167         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 168                 return 0;
 169
 170         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 171
 172         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 173                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 174
 175         return ret;
 176 }
 177
 178 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 179 {
 180         drm_radeon_private_t *dev_priv = dev->dev_private;
 181         u32 crtc_cnt_reg, crtc_status_reg;
 182
 183         if (!dev_priv) {
 184                 DRM_ERROR("called with no initialization\n");
 185                 return -EINVAL;
 186         }
 187
 188         if (crtc == 0) {
 189                 crtc_cnt_reg = RADEON_CRTC_CRNT_FRAME;
 190                 crtc_status_reg = RADEON_CRTC_STATUS;
 191         } else if (crtc == 1) {
 192                 crtc_cnt_reg = RADEON_CRTC2_CRNT_FRAME;
 193                 crtc_status_reg = RADEON_CRTC2_STATUS;
 194         } else {
 195                 return -EINVAL;
 196         }
 197
 198         return RADEON_READ(crtc_cnt_reg) + (RADEON_READ(crtc_status_reg) & 1);
 199 }
 200
 201 /* Needs the lock as it touches the ring.
 202  */
 203 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 204 {
 205         drm_radeon_private_t *dev_priv = dev->dev_private;
 206         drm_radeon_irq_emit_t *emit = data;
 207         int result;
 208
 209         LOCK_TEST_WITH_RETURN(dev, file_priv);
 210
 211         if (!dev_priv) {
 212                 DRM_ERROR("called with no initialization\n");
 213                 return -EINVAL;
 214         }
 215
 216         result = radeon_emit_irq(dev);
 217
 218         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 219                 DRM_ERROR("copy_to_user\n");
 220                 return -EFAULT;
 221         }
 222
 223         return 0;
 224 }
 225
 226 /* Doesn't need the hardware lock.
 227  */
 228 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 229 {
 230         drm_radeon_private_t *dev_priv = dev->dev_private;
 231         drm_radeon_irq_wait_t *irqwait = data;
 232
 233         if (!dev_priv) {
 234                 DRM_ERROR("called with no initialization\n");
 235                 return -EINVAL;
 236         }
 237
 238         return radeon_wait_irq(dev, irqwait->irq_seq);
 239 }
 240
 241 /* drm_dma.h hooks
 242 */
 243 void radeon_driver_irq_preinstall(struct drm_device * dev)
 244 {
 245         drm_radeon_private_t *dev_priv =
 246             (drm_radeon_private_t *) dev->dev_private;
 247
 248         /* Disable *all* interrupts */
 249         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 250
 251         /* Clear bits if they're already high */
 252         radeon_acknowledge_irqs(dev_priv);
 253 }
 254
 255 int radeon_driver_irq_postinstall(struct drm_device * dev)
 256 {
 257         drm_radeon_private_t *dev_priv =
 258             (drm_radeon_private_t *) dev->dev_private;
 259         int ret;
 260
 261         atomic_set(&dev_priv->swi_emitted, 0);
 262         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 263
 264         ret = drm_vblank_init(dev, 2);
 265         if (ret)
 266                 return ret;
 267
 268         dev->max_vblank_count = 0x001fffff;
 269
 270         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 271
 272         return 0;
 273 }
 274
 275 void radeon_driver_irq_uninstall(struct drm_device * dev)
 276 {
 277         drm_radeon_private_t *dev_priv =
 278             (drm_radeon_private_t *) dev->dev_private;
 279         if (!dev_priv)
 280                 return;
 281
 282         dev_priv->irq_enabled = 0;
 283
 284         /* Disable *all* interrupts */
 285         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 286 }
 287
 288
 289 int radeon_vblank_crtc_get(struct drm_device *dev)
 290 {
 291         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 292         u32 flag;
 293         u32 value;
 294
 295         flag = RADEON_READ(RADEON_GEN_INT_CNTL);
 296         value = 0;
 297
 298         if (flag & RADEON_CRTC_VBLANK_MASK)
 299                 value |= DRM_RADEON_VBLANK_CRTC1;
 300
 301         if (flag & RADEON_CRTC2_VBLANK_MASK)
 302                 value |= DRM_RADEON_VBLANK_CRTC2;
 303         return value;
 304 }
 305
 306 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 307 {
 308         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 309         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 310                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 311                 return -EINVAL;
 312         }
 313         dev_priv->vblank_crtc = (unsigned int)value;
 314         return 0;
 315 }