drivers/ide/pci/sc1200.c

   1 /*
   2  * Copyright (C) 2000-2002              Mark Lord <mlord@pobox.com>
   3  * Copyright (C)      2007              Bartlomiej Zolnierkiewicz
   4  *
   5  * May be copied or modified under the terms of the GNU General Public License
   6  *
   7  * Development of this chipset driver was funded
   8  * by the nice folks at National Semiconductor.
   9  *
  10  * Documentation:
  11  *      Available from National Semiconductor
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/hdreg.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/ide.h>
  21 #include <linux/pm.h>
  22
  23 #include <asm/io.h>
  24
  25 #define SC1200_REV_A    0x00
  26 #define SC1200_REV_B1   0x01
  27 #define SC1200_REV_B3   0x02
  28 #define SC1200_REV_C1   0x03
  29 #define SC1200_REV_D1   0x04
  30
  31 #define PCI_CLK_33      0x00
  32 #define PCI_CLK_48      0x01
  33 #define PCI_CLK_66      0x02
  34 #define PCI_CLK_33A     0x03
  35
  36 static unsigned short sc1200_get_pci_clock (void)
  37 {
  38         unsigned char chip_id, silicon_revision;
  39         unsigned int pci_clock;
  40         /*
  41          * Check the silicon revision, as not all versions of the chip
  42          * have the register with the fast PCI bus timings.
  43          */
  44         chip_id = inb (0x903c);
  45         silicon_revision = inb (0x903d);
  46
  47         // Read the fast pci clock frequency
  48         if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
  49                 pci_clock = PCI_CLK_33;
  50         } else {
  51                 // check clock generator configuration (cfcc)
  52                 // the clock is in bits 8 and 9 of this word
  53
  54                 pci_clock = inw (0x901e);
  55                 pci_clock >>= 8;
  56                 pci_clock &= 0x03;
  57                 if (pci_clock == PCI_CLK_33A)
  58                         pci_clock = PCI_CLK_33;
  59         }
  60         return pci_clock;
  61 }
  62
  63 /*
  64  * Here are the standard PIO mode 0-4 timings for each "format".
  65  * Format-0 uses fast data reg timings, with slower command reg timings.
  66  * Format-1 uses fast timings for all registers, but won't work with all drives.
  67  */
  68 static const unsigned int sc1200_pio_timings[4][5] =
  69         {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},  // format0  33Mhz
  70          {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},  // format1, 33Mhz
  71          {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},  // format1, 48Mhz
  72          {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
  73
  74 /*
  75  * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
  76  */
  77 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
  78
  79 static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
  80 {
  81         ide_hwif_t *hwif = drive->hwif;
  82         struct pci_dev *pdev = to_pci_dev(hwif->dev);
  83         unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
  84
  85         pci_read_config_dword(pdev, basereg + 4, &format);
  86         format = (format >> 31) & 1;
  87         if (format)
  88                 format += sc1200_get_pci_clock();
  89         pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
  90                                sc1200_pio_timings[format][pio]);
  91 }
  92
  93 /*
  94  *      The SC1200 specifies that two drives sharing a cable cannot mix
  95  *      UDMA/MDMA.  It has to be one or the other, for the pair, though
  96  *      different timings can still be chosen for each drive.  We could
  97  *      set the appropriate timing bits on the fly, but that might be
  98  *      a bit confusing.  So, for now we statically handle this requirement
  99  *      by looking at our mate drive to see what it is capable of, before
 100  *      choosing a mode for our own drive.
 101  */
 102 static u8 sc1200_udma_filter(ide_drive_t *drive)
 103 {
 104         ide_hwif_t *hwif = drive->hwif;
 105         ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
 106         struct hd_driveid *mateid = mate->id;
 107         u8 mask = hwif->ultra_mask;
 108
 109         if (mate->present == 0)
 110                 goto out;
 111
 112         if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
 113                 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
 114                         goto out;
 115                 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
 116                         mask = 0;
 117         }
 118 out:
 119         return mask;
 120 }
 121
 122 static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
 123 {
 124         ide_hwif_t              *hwif = HWIF(drive);
 125         struct pci_dev          *dev = to_pci_dev(hwif->dev);
 126         int                     unit = drive->select.b.unit;
 127         unsigned int            reg, timings;
 128         unsigned short          pci_clock;
 129         unsigned int            basereg = hwif->channel ? 0x50 : 0x40;
 130
 131         static const u32 udma_timing[3][3] = {
 132                 { 0x00921250, 0x00911140, 0x00911030 },
 133                 { 0x00932470, 0x00922260, 0x00922140 },
 134                 { 0x009436a1, 0x00933481, 0x00923261 },
 135         };
 136
 137         static const u32 mwdma_timing[3][3] = {
 138                 { 0x00077771, 0x00012121, 0x00002020 },
 139                 { 0x000bbbb2, 0x00024241, 0x00013131 },
 140                 { 0x000ffff3, 0x00035352, 0x00015151 },
 141         };
 142
 143         pci_clock = sc1200_get_pci_clock();
 144
 145         /*
 146          * Note that each DMA mode has several timings associated with it.
 147          * The correct timing depends on the fast PCI clock freq.
 148          */
 149
 150         if (mode >= XFER_UDMA_0)
 151                 timings =  udma_timing[pci_clock][mode - XFER_UDMA_0];
 152         else
 153                 timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
 154
 155         if (unit == 0) {                        /* are we configuring drive0? */
 156                 pci_read_config_dword(dev, basereg + 4, &reg);
 157                 timings |= reg & 0x80000000;    /* preserve PIO format bit */
 158                 pci_write_config_dword(dev, basereg + 4, timings);
 159         } else
 160                 pci_write_config_dword(dev, basereg + 12, timings);
 161 }
 162
 163 /*  Replacement for the standard ide_dma_end action in
 164  *  dma_proc.
 165  *
 166  *  returns 1 on error, 0 otherwise
 167  */
 168 static int sc1200_dma_end(ide_drive_t *drive)
 169 {
 170         ide_hwif_t *hwif = HWIF(drive);
 171         unsigned long dma_base = hwif->dma_base;
 172         byte dma_stat;
 173
 174         dma_stat = inb(dma_base+2);             /* get DMA status */
 175
 176         if (!(dma_stat & 4))
 177                 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
 178                   dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
 179
 180         outb(dma_stat|0x1b, dma_base+2);        /* clear the INTR & ERROR bits */
 181         outb(inb(dma_base)&~1, dma_base);       /* !! DO THIS HERE !! stop DMA */
 182
 183         drive->waiting_for_dma = 0;
 184         ide_destroy_dmatable(drive);            /* purge DMA mappings */
 185
 186         return (dma_stat & 7) != 4;             /* verify good DMA status */
 187 }
 188
 189 /*
 190  * sc1200_set_pio_mode() handles setting of PIO modes
 191  * for both the chipset and drive.
 192  *
 193  * All existing BIOSs for this chipset guarantee that all drives
 194  * will have valid default PIO timings set up before we get here.
 195  */
 196
 197 static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
 198 {
 199         ide_hwif_t      *hwif = HWIF(drive);
 200         int             mode = -1;
 201
 202         /*
 203          * bad abuse of ->set_pio_mode interface
 204          */
 205         switch (pio) {
 206                 case 200: mode = XFER_UDMA_0;   break;
 207                 case 201: mode = XFER_UDMA_1;   break;
 208                 case 202: mode = XFER_UDMA_2;   break;
 209                 case 100: mode = XFER_MW_DMA_0; break;
 210                 case 101: mode = XFER_MW_DMA_1; break;
 211                 case 102: mode = XFER_MW_DMA_2; break;
 212         }
 213         if (mode != -1) {
 214                 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
 215                 ide_dma_off_quietly(drive);
 216                 if (ide_set_dma_mode(drive, mode) == 0 && drive->using_dma)
 217                         hwif->dma_ops->dma_host_set(drive, 1);
 218                 return;
 219         }
 220
 221         sc1200_tunepio(drive, pio);
 222 }
 223
 224 #ifdef CONFIG_PM
 225 struct sc1200_saved_state {
 226         u32 regs[8];
 227 };
 228
 229 static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
 230 {
 231         printk("SC1200: suspend(%u)\n", state.event);
 232
 233         /*
 234          * we only save state when going from full power to less
 235          */
 236         if (state.event == PM_EVENT_ON) {
 237                 struct sc1200_saved_state *ss;
 238                 unsigned int r;
 239
 240                 /*
 241                  * allocate a permanent save area, if not already allocated
 242                  */
 243                 ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
 244                 if (ss == NULL) {
 245                         ss = kmalloc(sizeof(*ss), GFP_KERNEL);
 246                         if (ss == NULL)
 247                                 return -ENOMEM;
 248                         pci_set_drvdata(dev, ss);
 249                 }
 250
 251                 /*
 252                  * save timing registers
 253                  * (this may be unnecessary if BIOS also does it)
 254                  */
 255                 for (r = 0; r < 8; r++)
 256                         pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
 257         }
 258
 259         pci_disable_device(dev);
 260         pci_set_power_state(dev, pci_choose_state(dev, state));
 261         return 0;
 262 }
 263
 264 static int sc1200_resume (struct pci_dev *dev)
 265 {
 266         struct sc1200_saved_state *ss;
 267         unsigned int r;
 268         int i;
 269
 270         i = pci_enable_device(dev);
 271         if (i)
 272                 return i;
 273
 274         ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
 275
 276         /*
 277          * restore timing registers
 278          * (this may be unnecessary if BIOS also does it)
 279          */
 280         if (ss) {
 281                 for (r = 0; r < 8; r++)
 282                         pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
 283         }
 284
 285         return 0;
 286 }
 287 #endif
 288
 289 static const struct ide_port_ops sc1200_port_ops = {
 290         .set_pio_mode           = sc1200_set_pio_mode,
 291         .set_dma_mode           = sc1200_set_dma_mode,
 292         .udma_filter            = sc1200_udma_filter,
 293 };
 294
 295 static const struct ide_dma_ops sc1200_dma_ops = {
 296         .dma_host_set           = ide_dma_host_set,
 297         .dma_setup              = ide_dma_setup,
 298         .dma_exec_cmd           = ide_dma_exec_cmd,
 299         .dma_start              = ide_dma_start,
 300         .dma_end                = sc1200_dma_end,
 301         .dma_test_irq           = ide_dma_test_irq,
 302         .dma_lost_irq           = ide_dma_lost_irq,
 303         .dma_timeout            = ide_dma_timeout,
 304 };
 305
 306 static const struct ide_port_info sc1200_chipset __devinitdata = {
 307         .name           = "SC1200",
 308         .port_ops       = &sc1200_port_ops,
 309         .dma_ops        = &sc1200_dma_ops,
 310         .host_flags     = IDE_HFLAG_SERIALIZE |
 311                           IDE_HFLAG_POST_SET_MODE |
 312                           IDE_HFLAG_ABUSE_DMA_MODES,
 313         .pio_mask       = ATA_PIO4,
 314         .mwdma_mask     = ATA_MWDMA2,
 315         .udma_mask      = ATA_UDMA2,
 316 };
 317
 318 static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 319 {
 320         return ide_setup_pci_device(dev, &sc1200_chipset);
 321 }
 322
 323 static const struct pci_device_id sc1200_pci_tbl[] = {
 324         { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
 325         { 0, },
 326 };
 327 MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
 328
 329 static struct pci_driver driver = {
 330         .name           = "SC1200_IDE",
 331         .id_table       = sc1200_pci_tbl,
 332         .probe          = sc1200_init_one,
 333 #ifdef CONFIG_PM
 334         .suspend        = sc1200_suspend,
 335         .resume         = sc1200_resume,
 336 #endif
 337 };
 338
 339 static int __init sc1200_ide_init(void)
 340 {
 341         return ide_pci_register_driver(&driver);
 342 }
 343
 344 module_init(sc1200_ide_init);
 345
 346 MODULE_AUTHOR("Mark Lord");
 347 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
 348 MODULE_LICENSE("GPL");