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sata_nv: propagate ata_pci_device_do_resume return value
[pv_ops_mirror.git] / drivers / serial / amba-pl010.c
blobf69bd097166e96a1956f2c5394ce91da82eaa7cb
1 /*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
26 *
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
33 */
34
35 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
36 #define SUPPORT_SYSRQ
37 #endif
38
39 #include <linux/module.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/console.h>
43 #include <linux/sysrq.h>
44 #include <linux/device.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial_core.h>
48 #include <linux/serial.h>
49 #include <linux/amba/bus.h>
50 #include <linux/amba/serial.h>
51
52 #include <asm/io.h>
53
54 #define UART_NR 8
55
56 #define SERIAL_AMBA_MAJOR 204
57 #define SERIAL_AMBA_MINOR 16
58 #define SERIAL_AMBA_NR UART_NR
59
60 #define AMBA_ISR_PASS_LIMIT 256
61
62 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
63 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
64
65 #define UART_DUMMY_RSR_RX 256
66 #define UART_PORT_SIZE 64
67
68 /*
69 * We wrap our port structure around the generic uart_port.
70 */
71 struct uart_amba_port {
72 struct uart_port port;
73 struct amba_device *dev;
74 struct amba_pl010_data *data;
75 unsigned int old_status;
76 };
77
78 static void pl010_stop_tx(struct uart_port *port)
79 {
80 unsigned int cr;
81
82 cr = readb(port->membase + UART010_CR);
83 cr &= ~UART010_CR_TIE;
84 writel(cr, port->membase + UART010_CR);
85 }
86
87 static void pl010_start_tx(struct uart_port *port)
88 {
89 unsigned int cr;
90
91 cr = readb(port->membase + UART010_CR);
92 cr |= UART010_CR_TIE;
93 writel(cr, port->membase + UART010_CR);
94 }
95
96 static void pl010_stop_rx(struct uart_port *port)
97 {
98 unsigned int cr;
99
100 cr = readb(port->membase + UART010_CR);
101 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
102 writel(cr, port->membase + UART010_CR);
103 }
104
105 static void pl010_enable_ms(struct uart_port *port)
106 {
107 unsigned int cr;
108
109 cr = readb(port->membase + UART010_CR);
110 cr |= UART010_CR_MSIE;
111 writel(cr, port->membase + UART010_CR);
112 }
113
114 static void pl010_rx_chars(struct uart_port *port)
115 {
116 struct tty_struct *tty = port->info->tty;
117 unsigned int status, ch, flag, rsr, max_count = 256;
118
119 status = readb(port->membase + UART01x_FR);
120 while (UART_RX_DATA(status) && max_count--) {
121 ch = readb(port->membase + UART01x_DR);
122 flag = TTY_NORMAL;
123
124 port->icount.rx++;
125
126 /*
127 * Note that the error handling code is
128 * out of the main execution path
129 */
130 rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
131 if (unlikely(rsr & UART01x_RSR_ANY)) {
132 writel(0, port->membase + UART01x_ECR);
133
134 if (rsr & UART01x_RSR_BE) {
135 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
136 port->icount.brk++;
137 if (uart_handle_break(port))
138 goto ignore_char;
139 } else if (rsr & UART01x_RSR_PE)
140 port->icount.parity++;
141 else if (rsr & UART01x_RSR_FE)
142 port->icount.frame++;
143 if (rsr & UART01x_RSR_OE)
144 port->icount.overrun++;
145
146 rsr &= port->read_status_mask;
147
148 if (rsr & UART01x_RSR_BE)
149 flag = TTY_BREAK;
150 else if (rsr & UART01x_RSR_PE)
151 flag = TTY_PARITY;
152 else if (rsr & UART01x_RSR_FE)
153 flag = TTY_FRAME;
154 }
155
156 if (uart_handle_sysrq_char(port, ch))
157 goto ignore_char;
158
159 uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
160
161 ignore_char:
162 status = readb(port->membase + UART01x_FR);
163 }
164 tty_flip_buffer_push(tty);
165 return;
166 }
167
168 static void pl010_tx_chars(struct uart_port *port)
169 {
170 struct circ_buf *xmit = &port->info->xmit;
171 int count;
172
173 if (port->x_char) {
174 writel(port->x_char, port->membase + UART01x_DR);
175 port->icount.tx++;
176 port->x_char = 0;
177 return;
178 }
179 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
180 pl010_stop_tx(port);
181 return;
182 }
183
184 count = port->fifosize >> 1;
185 do {
186 writel(xmit->buf[xmit->tail], port->membase + UART01x_DR);
187 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
188 port->icount.tx++;
189 if (uart_circ_empty(xmit))
190 break;
191 } while (--count > 0);
192
193 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
194 uart_write_wakeup(port);
195
196 if (uart_circ_empty(xmit))
197 pl010_stop_tx(port);
198 }
199
200 static void pl010_modem_status(struct uart_port *port)
201 {
202 struct uart_amba_port *uap = (struct uart_amba_port *)port;
203 unsigned int status, delta;
204
205 writel(0, uap->port.membase + UART010_ICR);
206
207 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
208
209 delta = status ^ uap->old_status;
210 uap->old_status = status;
211
212 if (!delta)
213 return;
214
215 if (delta & UART01x_FR_DCD)
216 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
217
218 if (delta & UART01x_FR_DSR)
219 uap->port.icount.dsr++;
220
221 if (delta & UART01x_FR_CTS)
222 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
223
224 wake_up_interruptible(&uap->port.info->delta_msr_wait);
225 }
226
227 static irqreturn_t pl010_int(int irq, void *dev_id)
228 {
229 struct uart_port *port = dev_id;
230 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
231 int handled = 0;
232
233 spin_lock(&port->lock);
234
235 status = readb(port->membase + UART010_IIR);
236 if (status) {
237 do {
238 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
239 pl010_rx_chars(port);
240 if (status & UART010_IIR_MIS)
241 pl010_modem_status(port);
242 if (status & UART010_IIR_TIS)
243 pl010_tx_chars(port);
244
245 if (pass_counter-- == 0)
246 break;
247
248 status = readb(port->membase + UART010_IIR);
249 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
250 UART010_IIR_TIS));
251 handled = 1;
252 }
253
254 spin_unlock(&port->lock);
255
256 return IRQ_RETVAL(handled);
257 }
258
259 static unsigned int pl010_tx_empty(struct uart_port *port)
260 {
261 return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
262 }
263
264 static unsigned int pl010_get_mctrl(struct uart_port *port)
265 {
266 unsigned int result = 0;
267 unsigned int status;
268
269 status = readb(port->membase + UART01x_FR);
270 if (status & UART01x_FR_DCD)
271 result |= TIOCM_CAR;
272 if (status & UART01x_FR_DSR)
273 result |= TIOCM_DSR;
274 if (status & UART01x_FR_CTS)
275 result |= TIOCM_CTS;
276
277 return result;
278 }
279
280 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
281 {
282 struct uart_amba_port *uap = (struct uart_amba_port *)port;
283
284 if (uap->data)
285 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
286 }
287
288 static void pl010_break_ctl(struct uart_port *port, int break_state)
289 {
290 unsigned long flags;
291 unsigned int lcr_h;
292
293 spin_lock_irqsave(&port->lock, flags);
294 lcr_h = readb(port->membase + UART010_LCRH);
295 if (break_state == -1)
296 lcr_h |= UART01x_LCRH_BRK;
297 else
298 lcr_h &= ~UART01x_LCRH_BRK;
299 writel(lcr_h, port->membase + UART010_LCRH);
300 spin_unlock_irqrestore(&port->lock, flags);
301 }
302
303 static int pl010_startup(struct uart_port *port)
304 {
305 struct uart_amba_port *uap = (struct uart_amba_port *)port;
306 int retval;
307
308 /*
309 * Allocate the IRQ
310 */
311 retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port);
312 if (retval)
313 return retval;
314
315 /*
316 * initialise the old status of the modem signals
317 */
318 uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
319
320 /*
321 * Finally, enable interrupts
322 */
323 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
324 port->membase + UART010_CR);
325
326 return 0;
327 }
328
329 static void pl010_shutdown(struct uart_port *port)
330 {
331 /*
332 * Free the interrupt
333 */
334 free_irq(port->irq, port);
335
336 /*
337 * disable all interrupts, disable the port
338 */
339 writel(0, port->membase + UART010_CR);
340
341 /* disable break condition and fifos */
342 writel(readb(port->membase + UART010_LCRH) &
343 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
344 port->membase + UART010_LCRH);
345 }
346
347 static void
348 pl010_set_termios(struct uart_port *port, struct ktermios *termios,
349 struct ktermios *old)
350 {
351 unsigned int lcr_h, old_cr;
352 unsigned long flags;
353 unsigned int baud, quot;
354
355 /*
356 * Ask the core to calculate the divisor for us.
357 */
358 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
359 quot = uart_get_divisor(port, baud);
360
361 switch (termios->c_cflag & CSIZE) {
362 case CS5:
363 lcr_h = UART01x_LCRH_WLEN_5;
364 break;
365 case CS6:
366 lcr_h = UART01x_LCRH_WLEN_6;
367 break;
368 case CS7:
369 lcr_h = UART01x_LCRH_WLEN_7;
370 break;
371 default: // CS8
372 lcr_h = UART01x_LCRH_WLEN_8;
373 break;
374 }
375 if (termios->c_cflag & CSTOPB)
376 lcr_h |= UART01x_LCRH_STP2;
377 if (termios->c_cflag & PARENB) {
378 lcr_h |= UART01x_LCRH_PEN;
379 if (!(termios->c_cflag & PARODD))
380 lcr_h |= UART01x_LCRH_EPS;
381 }
382 if (port->fifosize > 1)
383 lcr_h |= UART01x_LCRH_FEN;
384
385 spin_lock_irqsave(&port->lock, flags);
386
387 /*
388 * Update the per-port timeout.
389 */
390 uart_update_timeout(port, termios->c_cflag, baud);
391
392 port->read_status_mask = UART01x_RSR_OE;
393 if (termios->c_iflag & INPCK)
394 port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
395 if (termios->c_iflag & (BRKINT | PARMRK))
396 port->read_status_mask |= UART01x_RSR_BE;
397
398 /*
399 * Characters to ignore
400 */
401 port->ignore_status_mask = 0;
402 if (termios->c_iflag & IGNPAR)
403 port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
404 if (termios->c_iflag & IGNBRK) {
405 port->ignore_status_mask |= UART01x_RSR_BE;
406 /*
407 * If we're ignoring parity and break indicators,
408 * ignore overruns too (for real raw support).
409 */
410 if (termios->c_iflag & IGNPAR)
411 port->ignore_status_mask |= UART01x_RSR_OE;
412 }
413
414 /*
415 * Ignore all characters if CREAD is not set.
416 */
417 if ((termios->c_cflag & CREAD) == 0)
418 port->ignore_status_mask |= UART_DUMMY_RSR_RX;
419
420 /* first, disable everything */
421 old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
422
423 if (UART_ENABLE_MS(port, termios->c_cflag))
424 old_cr |= UART010_CR_MSIE;
425
426 writel(0, port->membase + UART010_CR);
427
428 /* Set baud rate */
429 quot -= 1;
430 writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
431 writel(quot & 0xff, port->membase + UART010_LCRL);
432
433 /*
434 * ----------v----------v----------v----------v-----
435 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
436 * ----------^----------^----------^----------^-----
437 */
438 writel(lcr_h, port->membase + UART010_LCRH);
439 writel(old_cr, port->membase + UART010_CR);
440
441 spin_unlock_irqrestore(&port->lock, flags);
442 }
443
444 static const char *pl010_type(struct uart_port *port)
445 {
446 return port->type == PORT_AMBA ? "AMBA" : NULL;
447 }
448
449 /*
450 * Release the memory region(s) being used by 'port'
451 */
452 static void pl010_release_port(struct uart_port *port)
453 {
454 release_mem_region(port->mapbase, UART_PORT_SIZE);
455 }
456
457 /*
458 * Request the memory region(s) being used by 'port'
459 */
460 static int pl010_request_port(struct uart_port *port)
461 {
462 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
463 != NULL ? 0 : -EBUSY;
464 }
465
466 /*
467 * Configure/autoconfigure the port.
468 */
469 static void pl010_config_port(struct uart_port *port, int flags)
470 {
471 if (flags & UART_CONFIG_TYPE) {
472 port->type = PORT_AMBA;
473 pl010_request_port(port);
474 }
475 }
476
477 /*
478 * verify the new serial_struct (for TIOCSSERIAL).
479 */
480 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
481 {
482 int ret = 0;
483 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
484 ret = -EINVAL;
485 if (ser->irq < 0 || ser->irq >= NR_IRQS)
486 ret = -EINVAL;
487 if (ser->baud_base < 9600)
488 ret = -EINVAL;
489 return ret;
490 }
491
492 static struct uart_ops amba_pl010_pops = {
493 .tx_empty = pl010_tx_empty,
494 .set_mctrl = pl010_set_mctrl,
495 .get_mctrl = pl010_get_mctrl,
496 .stop_tx = pl010_stop_tx,
497 .start_tx = pl010_start_tx,
498 .stop_rx = pl010_stop_rx,
499 .enable_ms = pl010_enable_ms,
500 .break_ctl = pl010_break_ctl,
501 .startup = pl010_startup,
502 .shutdown = pl010_shutdown,
503 .set_termios = pl010_set_termios,
504 .type = pl010_type,
505 .release_port = pl010_release_port,
506 .request_port = pl010_request_port,
507 .config_port = pl010_config_port,
508 .verify_port = pl010_verify_port,
509 };
510
511 static struct uart_amba_port *amba_ports[UART_NR];
512
513 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
514
515 static void pl010_console_putchar(struct uart_port *port, int ch)
516 {
517 unsigned int status;
518
519 do {
520 status = readb(port->membase + UART01x_FR);
521 barrier();
522 } while (!UART_TX_READY(status));
523 writel(ch, port->membase + UART01x_DR);
524 }
525
526 static void
527 pl010_console_write(struct console *co, const char *s, unsigned int count)
528 {
529 struct uart_port *port = &amba_ports[co->index]->port;
530 unsigned int status, old_cr;
531
532 /*
533 * First save the CR then disable the interrupts
534 */
535 old_cr = readb(port->membase + UART010_CR);
536 writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
537
538 uart_console_write(port, s, count, pl010_console_putchar);
539
540 /*
541 * Finally, wait for transmitter to become empty
542 * and restore the TCR
543 */
544 do {
545 status = readb(port->membase + UART01x_FR);
546 barrier();
547 } while (status & UART01x_FR_BUSY);
548 writel(old_cr, port->membase + UART010_CR);
549 }
550
551 static void __init
552 pl010_console_get_options(struct uart_port *port, int *baud,
553 int *parity, int *bits)
554 {
555 if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) {
556 unsigned int lcr_h, quot;
557 lcr_h = readb(port->membase + UART010_LCRH);
558
559 *parity = 'n';
560 if (lcr_h & UART01x_LCRH_PEN) {
561 if (lcr_h & UART01x_LCRH_EPS)
562 *parity = 'e';
563 else
564 *parity = 'o';
565 }
566
567 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
568 *bits = 7;
569 else
570 *bits = 8;
571
572 quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8;
573 *baud = port->uartclk / (16 * (quot + 1));
574 }
575 }
576
577 static int __init pl010_console_setup(struct console *co, char *options)
578 {
579 struct uart_port *port;
580 int baud = 38400;
581 int bits = 8;
582 int parity = 'n';
583 int flow = 'n';
584
585 /*
586 * Check whether an invalid uart number has been specified, and
587 * if so, search for the first available port that does have
588 * console support.
589 */
590 if (co->index >= UART_NR)
591 co->index = 0;
592 if (!amba_ports[co->index])
593 return -ENODEV;
594 port = &amba_ports[co->index]->port;
595
596 if (options)
597 uart_parse_options(options, &baud, &parity, &bits, &flow);
598 else
599 pl010_console_get_options(port, &baud, &parity, &bits);
600
601 return uart_set_options(port, co, baud, parity, bits, flow);
602 }
603
604 static struct uart_driver amba_reg;
605 static struct console amba_console = {
606 .name = "ttyAM",
607 .write = pl010_console_write,
608 .device = uart_console_device,
609 .setup = pl010_console_setup,
610 .flags = CON_PRINTBUFFER,
611 .index = -1,
612 .data = &amba_reg,
613 };
614
615 #define AMBA_CONSOLE &amba_console
616 #else
617 #define AMBA_CONSOLE NULL
618 #endif
619
620 static struct uart_driver amba_reg = {
621 .owner = THIS_MODULE,
622 .driver_name = "ttyAM",
623 .dev_name = "ttyAM",
624 .major = SERIAL_AMBA_MAJOR,
625 .minor = SERIAL_AMBA_MINOR,
626 .nr = UART_NR,
627 .cons = AMBA_CONSOLE,
628 };
629
630 static int pl010_probe(struct amba_device *dev, void *id)
631 {
632 struct uart_amba_port *port;
633 void __iomem *base;
634 int i, ret;
635
636 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
637 if (amba_ports[i] == NULL)
638 break;
639
640 if (i == ARRAY_SIZE(amba_ports)) {
641 ret = -EBUSY;
642 goto out;
643 }
644
645 port = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
646 if (!port) {
647 ret = -ENOMEM;
648 goto out;
649 }
650
651 base = ioremap(dev->res.start, PAGE_SIZE);
652 if (!base) {
653 ret = -ENOMEM;
654 goto free;
655 }
656
657 port->port.dev = &dev->dev;
658 port->port.mapbase = dev->res.start;
659 port->port.membase = base;
660 port->port.iotype = UPIO_MEM;
661 port->port.irq = dev->irq[0];
662 port->port.uartclk = 14745600;
663 port->port.fifosize = 16;
664 port->port.ops = &amba_pl010_pops;
665 port->port.flags = UPF_BOOT_AUTOCONF;
666 port->port.line = i;
667 port->dev = dev;
668 port->data = dev->dev.platform_data;
669
670 amba_ports[i] = port;
671
672 amba_set_drvdata(dev, port);
673 ret = uart_add_one_port(&amba_reg, &port->port);
674 if (ret) {
675 amba_set_drvdata(dev, NULL);
676 amba_ports[i] = NULL;
677 iounmap(base);
678 free:
679 kfree(port);
680 }
681
682 out:
683 return ret;
684 }
685
686 static int pl010_remove(struct amba_device *dev)
687 {
688 struct uart_amba_port *port = amba_get_drvdata(dev);
689 int i;
690
691 amba_set_drvdata(dev, NULL);
692
693 uart_remove_one_port(&amba_reg, &port->port);
694
695 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
696 if (amba_ports[i] == port)
697 amba_ports[i] = NULL;
698
699 iounmap(port->port.membase);
700 kfree(port);
701
702 return 0;
703 }
704
705 static int pl010_suspend(struct amba_device *dev, pm_message_t state)
706 {
707 struct uart_amba_port *uap = amba_get_drvdata(dev);
708
709 if (uap)
710 uart_suspend_port(&amba_reg, &uap->port);
711
712 return 0;
713 }
714
715 static int pl010_resume(struct amba_device *dev)
716 {
717 struct uart_amba_port *uap = amba_get_drvdata(dev);
718
719 if (uap)
720 uart_resume_port(&amba_reg, &uap->port);
721
722 return 0;
723 }
724
725 static struct amba_id pl010_ids[] __initdata = {
726 {
727 .id = 0x00041010,
728 .mask = 0x000fffff,
729 },
730 { 0, 0 },
731 };
732
733 static struct amba_driver pl010_driver = {
734 .drv = {
735 .name = "uart-pl010",
736 },
737 .id_table = pl010_ids,
738 .probe = pl010_probe,
739 .remove = pl010_remove,
740 .suspend = pl010_suspend,
741 .resume = pl010_resume,
742 };
743
744 static int __init pl010_init(void)
745 {
746 int ret;
747
748 printk(KERN_INFO "Serial: AMBA driver $Revision: 1.41 $\n");
749
750 ret = uart_register_driver(&amba_reg);
751 if (ret == 0) {
752 ret = amba_driver_register(&pl010_driver);
753 if (ret)
754 uart_unregister_driver(&amba_reg);
755 }
756 return ret;
757 }
758
759 static void __exit pl010_exit(void)
760 {
761 amba_driver_unregister(&pl010_driver);
762 uart_unregister_driver(&amba_reg);
763 }
764
765 module_init(pl010_init);
766 module_exit(pl010_exit);
767
768 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
769 MODULE_DESCRIPTION("ARM AMBA serial port driver $Revision: 1.41 $");
770 MODULE_LICENSE("GPL");
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