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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzi...
[pv_ops_mirror.git] / drivers / pci / hotplug / pciehp_hpc.c
blob06d025b8b13f6a8f276e396bfc36a742c5a676a4
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
45 struct ctrl_reg {
46 u8 cap_id;
47 u8 nxt_ptr;
48 u16 cap_reg;
49 u32 dev_cap;
50 u16 dev_ctrl;
51 u16 dev_status;
52 u32 lnk_cap;
53 u16 lnk_ctrl;
54 u16 lnk_status;
55 u32 slot_cap;
56 u16 slot_ctrl;
57 u16 slot_status;
58 u16 root_ctrl;
59 u16 rsvp;
60 u32 root_status;
61 } __attribute__ ((packed));
62
63 /* offsets to the controller registers based on the above structure layout */
64 enum ctrl_offsets {
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
79 };
80
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
82 {
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
85 }
86
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
88 {
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
91 }
92
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
94 {
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
97 }
98
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
100 {
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
103 }
104
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
110
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
119
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
124
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
128
129 /* Link Width Encoding */
130 #define LNK_X1 0x01
131 #define LNK_X2 0x02
132 #define LNK_X4 0x04
133 #define LNK_X8 0x08
134 #define LNK_X12 0x0C
135 #define LNK_X16 0x10
136 #define LNK_X32 0x20
137
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
144
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
156
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
168
169 /* Attention indicator and Power indicator states */
170 #define LED_ON 0x01
171 #define LED_BLINK 0x10
172 #define LED_OFF 0x11
173
174 /* Power Control Command */
175 #define POWER_ON 0
176 #define POWER_OFF 0x0400
177
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
181
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
192
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
195
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
198 {
199 struct controller *ctrl = (struct controller *)data;
200
201 /* Poll for interrupt events. regs == NULL => polling */
202 pcie_isr(0, ctrl);
203
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* default polling interval is 2 sec */
207
208 start_int_poll_timer(ctrl, pciehp_poll_time);
209 }
210
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
213 {
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
216 sec = 2;
217
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
222 }
223
224 static inline int pcie_wait_cmd(struct controller *ctrl)
225 {
226 int retval = 0;
227 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
228 unsigned long timeout = msecs_to_jiffies(msecs);
229 int rc;
230
231 rc = wait_event_interruptible_timeout(ctrl->queue,
232 !ctrl->cmd_busy, timeout);
233 if (!rc)
234 dbg("Command not completed in 1000 msec\n");
235 else if (rc < 0) {
236 retval = -EINTR;
237 info("Command was interrupted by a signal\n");
238 }
239
240 return retval;
241 }
242
243 /**
244 * pcie_write_cmd - Issue controller command
245 * @slot: slot to which the command is issued
246 * @cmd: command value written to slot control register
247 * @mask: bitmask of slot control register to be modified
248 */
249 static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
250 {
251 struct controller *ctrl = slot->ctrl;
252 int retval = 0;
253 u16 slot_status;
254 u16 slot_ctrl;
255 unsigned long flags;
256
257 mutex_lock(&ctrl->ctrl_lock);
258
259 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
260 if (retval) {
261 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
262 goto out;
263 }
264
265 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
266 /* After 1 sec and CMD_COMPLETED still not set, just
267 proceed forward to issue the next command according
268 to spec. Just print out the error message */
269 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
270 __FUNCTION__);
271 }
272
273 spin_lock_irqsave(&ctrl->lock, flags);
274 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
275 if (retval) {
276 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
277 goto out_spin_unlock;
278 }
279
280 slot_ctrl &= ~mask;
281 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
282
283 ctrl->cmd_busy = 1;
284 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
285 if (retval)
286 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
287
288 out_spin_unlock:
289 spin_unlock_irqrestore(&ctrl->lock, flags);
290
291 /*
292 * Wait for command completion.
293 */
294 if (!retval)
295 retval = pcie_wait_cmd(ctrl);
296 out:
297 mutex_unlock(&ctrl->ctrl_lock);
298 return retval;
299 }
300
301 static int hpc_check_lnk_status(struct controller *ctrl)
302 {
303 u16 lnk_status;
304 int retval = 0;
305
306 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
307 if (retval) {
308 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
309 return retval;
310 }
311
312 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
313 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
314 !(lnk_status & NEG_LINK_WD)) {
315 err("%s : Link Training Error occurs \n", __FUNCTION__);
316 retval = -1;
317 return retval;
318 }
319
320 return retval;
321 }
322
323 static int hpc_get_attention_status(struct slot *slot, u8 *status)
324 {
325 struct controller *ctrl = slot->ctrl;
326 u16 slot_ctrl;
327 u8 atten_led_state;
328 int retval = 0;
329
330 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
331 if (retval) {
332 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
333 return retval;
334 }
335
336 dbg("%s: SLOTCTRL %x, value read %x\n",
337 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
338
339 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
340
341 switch (atten_led_state) {
342 case 0:
343 *status = 0xFF; /* Reserved */
344 break;
345 case 1:
346 *status = 1; /* On */
347 break;
348 case 2:
349 *status = 2; /* Blink */
350 break;
351 case 3:
352 *status = 0; /* Off */
353 break;
354 default:
355 *status = 0xFF;
356 break;
357 }
358
359 return 0;
360 }
361
362 static int hpc_get_power_status(struct slot *slot, u8 *status)
363 {
364 struct controller *ctrl = slot->ctrl;
365 u16 slot_ctrl;
366 u8 pwr_state;
367 int retval = 0;
368
369 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
370 if (retval) {
371 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
372 return retval;
373 }
374 dbg("%s: SLOTCTRL %x value read %x\n",
375 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
376
377 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
378
379 switch (pwr_state) {
380 case 0:
381 *status = 1;
382 break;
383 case 1:
384 *status = 0;
385 break;
386 default:
387 *status = 0xFF;
388 break;
389 }
390
391 return retval;
392 }
393
394 static int hpc_get_latch_status(struct slot *slot, u8 *status)
395 {
396 struct controller *ctrl = slot->ctrl;
397 u16 slot_status;
398 int retval = 0;
399
400 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
401 if (retval) {
402 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
403 return retval;
404 }
405
406 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
407
408 return 0;
409 }
410
411 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
412 {
413 struct controller *ctrl = slot->ctrl;
414 u16 slot_status;
415 u8 card_state;
416 int retval = 0;
417
418 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
419 if (retval) {
420 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
421 return retval;
422 }
423 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
424 *status = (card_state == 1) ? 1 : 0;
425
426 return 0;
427 }
428
429 static int hpc_query_power_fault(struct slot *slot)
430 {
431 struct controller *ctrl = slot->ctrl;
432 u16 slot_status;
433 u8 pwr_fault;
434 int retval = 0;
435
436 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
437 if (retval) {
438 err("%s: Cannot check for power fault\n", __FUNCTION__);
439 return retval;
440 }
441 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
442
443 return pwr_fault;
444 }
445
446 static int hpc_get_emi_status(struct slot *slot, u8 *status)
447 {
448 struct controller *ctrl = slot->ctrl;
449 u16 slot_status;
450 int retval = 0;
451
452 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
453 if (retval) {
454 err("%s : Cannot check EMI status\n", __FUNCTION__);
455 return retval;
456 }
457 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
458
459 return retval;
460 }
461
462 static int hpc_toggle_emi(struct slot *slot)
463 {
464 u16 slot_cmd;
465 u16 cmd_mask;
466 int rc;
467
468 slot_cmd = EMI_CTRL;
469 cmd_mask = EMI_CTRL;
470 if (!pciehp_poll_mode) {
471 slot_cmd = slot_cmd | HP_INTR_ENABLE;
472 cmd_mask = cmd_mask | HP_INTR_ENABLE;
473 }
474
475 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
476 slot->last_emi_toggle = get_seconds();
477
478 return rc;
479 }
480
481 static int hpc_set_attention_status(struct slot *slot, u8 value)
482 {
483 struct controller *ctrl = slot->ctrl;
484 u16 slot_cmd;
485 u16 cmd_mask;
486 int rc;
487
488 cmd_mask = ATTN_LED_CTRL;
489 switch (value) {
490 case 0 : /* turn off */
491 slot_cmd = 0x00C0;
492 break;
493 case 1: /* turn on */
494 slot_cmd = 0x0040;
495 break;
496 case 2: /* turn blink */
497 slot_cmd = 0x0080;
498 break;
499 default:
500 return -1;
501 }
502 if (!pciehp_poll_mode) {
503 slot_cmd = slot_cmd | HP_INTR_ENABLE;
504 cmd_mask = cmd_mask | HP_INTR_ENABLE;
505 }
506
507 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
508 dbg("%s: SLOTCTRL %x write cmd %x\n",
509 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
510
511 return rc;
512 }
513
514 static void hpc_set_green_led_on(struct slot *slot)
515 {
516 struct controller *ctrl = slot->ctrl;
517 u16 slot_cmd;
518 u16 cmd_mask;
519
520 slot_cmd = 0x0100;
521 cmd_mask = PWR_LED_CTRL;
522 if (!pciehp_poll_mode) {
523 slot_cmd = slot_cmd | HP_INTR_ENABLE;
524 cmd_mask = cmd_mask | HP_INTR_ENABLE;
525 }
526
527 pcie_write_cmd(slot, slot_cmd, cmd_mask);
528
529 dbg("%s: SLOTCTRL %x write cmd %x\n",
530 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
531 }
532
533 static void hpc_set_green_led_off(struct slot *slot)
534 {
535 struct controller *ctrl = slot->ctrl;
536 u16 slot_cmd;
537 u16 cmd_mask;
538
539 slot_cmd = 0x0300;
540 cmd_mask = PWR_LED_CTRL;
541 if (!pciehp_poll_mode) {
542 slot_cmd = slot_cmd | HP_INTR_ENABLE;
543 cmd_mask = cmd_mask | HP_INTR_ENABLE;
544 }
545
546 pcie_write_cmd(slot, slot_cmd, cmd_mask);
547 dbg("%s: SLOTCTRL %x write cmd %x\n",
548 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
549 }
550
551 static void hpc_set_green_led_blink(struct slot *slot)
552 {
553 struct controller *ctrl = slot->ctrl;
554 u16 slot_cmd;
555 u16 cmd_mask;
556
557 slot_cmd = 0x0200;
558 cmd_mask = PWR_LED_CTRL;
559 if (!pciehp_poll_mode) {
560 slot_cmd = slot_cmd | HP_INTR_ENABLE;
561 cmd_mask = cmd_mask | HP_INTR_ENABLE;
562 }
563
564 pcie_write_cmd(slot, slot_cmd, cmd_mask);
565
566 dbg("%s: SLOTCTRL %x write cmd %x\n",
567 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
568 }
569
570 static void hpc_release_ctlr(struct controller *ctrl)
571 {
572 if (pciehp_poll_mode)
573 del_timer(&ctrl->poll_timer);
574 else
575 free_irq(ctrl->pci_dev->irq, ctrl);
576
577 /*
578 * If this is the last controller to be released, destroy the
579 * pciehp work queue
580 */
581 if (atomic_dec_and_test(&pciehp_num_controllers))
582 destroy_workqueue(pciehp_wq);
583 }
584
585 static int hpc_power_on_slot(struct slot * slot)
586 {
587 struct controller *ctrl = slot->ctrl;
588 u16 slot_cmd;
589 u16 cmd_mask;
590 u16 slot_status;
591 int retval = 0;
592
593 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
594
595 /* Clear sticky power-fault bit from previous power failures */
596 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
597 if (retval) {
598 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
599 return retval;
600 }
601 slot_status &= PWR_FAULT_DETECTED;
602 if (slot_status) {
603 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
604 if (retval) {
605 err("%s: Cannot write to SLOTSTATUS register\n",
606 __FUNCTION__);
607 return retval;
608 }
609 }
610
611 slot_cmd = POWER_ON;
612 cmd_mask = PWR_CTRL;
613 /* Enable detection that we turned off at slot power-off time */
614 if (!pciehp_poll_mode) {
615 slot_cmd = slot_cmd |
616 PWR_FAULT_DETECT_ENABLE |
617 MRL_DETECT_ENABLE |
618 PRSN_DETECT_ENABLE |
619 HP_INTR_ENABLE;
620 cmd_mask = cmd_mask |
621 PWR_FAULT_DETECT_ENABLE |
622 MRL_DETECT_ENABLE |
623 PRSN_DETECT_ENABLE |
624 HP_INTR_ENABLE;
625 }
626
627 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
628
629 if (retval) {
630 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
631 return -1;
632 }
633 dbg("%s: SLOTCTRL %x write cmd %x\n",
634 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
635
636 return retval;
637 }
638
639 static int hpc_power_off_slot(struct slot * slot)
640 {
641 struct controller *ctrl = slot->ctrl;
642 u16 slot_cmd;
643 u16 cmd_mask;
644 int retval = 0;
645
646 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
647
648 slot_cmd = POWER_OFF;
649 cmd_mask = PWR_CTRL;
650 /*
651 * If we get MRL or presence detect interrupts now, the isr
652 * will notice the sticky power-fault bit too and issue power
653 * indicator change commands. This will lead to an endless loop
654 * of command completions, since the power-fault bit remains on
655 * till the slot is powered on again.
656 */
657 if (!pciehp_poll_mode) {
658 slot_cmd = (slot_cmd &
659 ~PWR_FAULT_DETECT_ENABLE &
660 ~MRL_DETECT_ENABLE &
661 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
662 cmd_mask = cmd_mask |
663 PWR_FAULT_DETECT_ENABLE |
664 MRL_DETECT_ENABLE |
665 PRSN_DETECT_ENABLE |
666 HP_INTR_ENABLE;
667 }
668
669 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
670 if (retval) {
671 err("%s: Write command failed!\n", __FUNCTION__);
672 return -1;
673 }
674 dbg("%s: SLOTCTRL %x write cmd %x\n",
675 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
676
677 return retval;
678 }
679
680 static irqreturn_t pcie_isr(int irq, void *dev_id)
681 {
682 struct controller *ctrl = (struct controller *)dev_id;
683 u16 slot_status, intr_detect, intr_loc;
684 u16 temp_word;
685 int hp_slot = 0; /* only 1 slot per PCI Express port */
686 int rc = 0;
687 unsigned long flags;
688
689 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
690 if (rc) {
691 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
692 return IRQ_NONE;
693 }
694
695 intr_detect = (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
696 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | CMD_COMPLETED);
697
698 intr_loc = slot_status & intr_detect;
699
700 /* Check to see if it was our interrupt */
701 if ( !intr_loc )
702 return IRQ_NONE;
703
704 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
705 /* Mask Hot-plug Interrupt Enable */
706 if (!pciehp_poll_mode) {
707 spin_lock_irqsave(&ctrl->lock, flags);
708 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
709 if (rc) {
710 err("%s: Cannot read SLOT_CTRL register\n",
711 __FUNCTION__);
712 spin_unlock_irqrestore(&ctrl->lock, flags);
713 return IRQ_NONE;
714 }
715
716 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
717 __FUNCTION__, temp_word);
718 temp_word = (temp_word & ~HP_INTR_ENABLE &
719 ~CMD_CMPL_INTR_ENABLE) | 0x00;
720 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
721 if (rc) {
722 err("%s: Cannot write to SLOTCTRL register\n",
723 __FUNCTION__);
724 spin_unlock_irqrestore(&ctrl->lock, flags);
725 return IRQ_NONE;
726 }
727 spin_unlock_irqrestore(&ctrl->lock, flags);
728
729 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
730 if (rc) {
731 err("%s: Cannot read SLOT_STATUS register\n",
732 __FUNCTION__);
733 return IRQ_NONE;
734 }
735 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
736 __FUNCTION__, slot_status);
737
738 /* Clear command complete interrupt caused by this write */
739 temp_word = 0x1f;
740 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
741 if (rc) {
742 err("%s: Cannot write to SLOTSTATUS register\n",
743 __FUNCTION__);
744 return IRQ_NONE;
745 }
746 }
747
748 if (intr_loc & CMD_COMPLETED) {
749 /*
750 * Command Complete Interrupt Pending
751 */
752 ctrl->cmd_busy = 0;
753 wake_up_interruptible(&ctrl->queue);
754 }
755
756 if (intr_loc & MRL_SENS_CHANGED)
757 pciehp_handle_switch_change(hp_slot, ctrl);
758
759 if (intr_loc & ATTN_BUTTN_PRESSED)
760 pciehp_handle_attention_button(hp_slot, ctrl);
761
762 if (intr_loc & PRSN_DETECT_CHANGED)
763 pciehp_handle_presence_change(hp_slot, ctrl);
764
765 if (intr_loc & PWR_FAULT_DETECTED)
766 pciehp_handle_power_fault(hp_slot, ctrl);
767
768 /* Clear all events after serving them */
769 temp_word = 0x1F;
770 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
771 if (rc) {
772 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
773 return IRQ_NONE;
774 }
775 /* Unmask Hot-plug Interrupt Enable */
776 if (!pciehp_poll_mode) {
777 spin_lock_irqsave(&ctrl->lock, flags);
778 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
779 if (rc) {
780 err("%s: Cannot read SLOTCTRL register\n",
781 __FUNCTION__);
782 spin_unlock_irqrestore(&ctrl->lock, flags);
783 return IRQ_NONE;
784 }
785
786 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
787 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
788
789 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
790 if (rc) {
791 err("%s: Cannot write to SLOTCTRL register\n",
792 __FUNCTION__);
793 spin_unlock_irqrestore(&ctrl->lock, flags);
794 return IRQ_NONE;
795 }
796 spin_unlock_irqrestore(&ctrl->lock, flags);
797
798 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
799 if (rc) {
800 err("%s: Cannot read SLOT_STATUS register\n",
801 __FUNCTION__);
802 return IRQ_NONE;
803 }
804
805 /* Clear command complete interrupt caused by this write */
806 temp_word = 0x1F;
807 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
808 if (rc) {
809 err("%s: Cannot write to SLOTSTATUS failed\n",
810 __FUNCTION__);
811 return IRQ_NONE;
812 }
813 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
814 __FUNCTION__, temp_word);
815 }
816
817 return IRQ_HANDLED;
818 }
819
820 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
821 {
822 struct controller *ctrl = slot->ctrl;
823 enum pcie_link_speed lnk_speed;
824 u32 lnk_cap;
825 int retval = 0;
826
827 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
828 if (retval) {
829 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
830 return retval;
831 }
832
833 switch (lnk_cap & 0x000F) {
834 case 1:
835 lnk_speed = PCIE_2PT5GB;
836 break;
837 default:
838 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
839 break;
840 }
841
842 *value = lnk_speed;
843 dbg("Max link speed = %d\n", lnk_speed);
844
845 return retval;
846 }
847
848 static int hpc_get_max_lnk_width(struct slot *slot,
849 enum pcie_link_width *value)
850 {
851 struct controller *ctrl = slot->ctrl;
852 enum pcie_link_width lnk_wdth;
853 u32 lnk_cap;
854 int retval = 0;
855
856 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
857 if (retval) {
858 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
859 return retval;
860 }
861
862 switch ((lnk_cap & 0x03F0) >> 4){
863 case 0:
864 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
865 break;
866 case 1:
867 lnk_wdth = PCIE_LNK_X1;
868 break;
869 case 2:
870 lnk_wdth = PCIE_LNK_X2;
871 break;
872 case 4:
873 lnk_wdth = PCIE_LNK_X4;
874 break;
875 case 8:
876 lnk_wdth = PCIE_LNK_X8;
877 break;
878 case 12:
879 lnk_wdth = PCIE_LNK_X12;
880 break;
881 case 16:
882 lnk_wdth = PCIE_LNK_X16;
883 break;
884 case 32:
885 lnk_wdth = PCIE_LNK_X32;
886 break;
887 default:
888 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
889 break;
890 }
891
892 *value = lnk_wdth;
893 dbg("Max link width = %d\n", lnk_wdth);
894
895 return retval;
896 }
897
898 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
899 {
900 struct controller *ctrl = slot->ctrl;
901 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
902 int retval = 0;
903 u16 lnk_status;
904
905 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
906 if (retval) {
907 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
908 return retval;
909 }
910
911 switch (lnk_status & 0x0F) {
912 case 1:
913 lnk_speed = PCIE_2PT5GB;
914 break;
915 default:
916 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
917 break;
918 }
919
920 *value = lnk_speed;
921 dbg("Current link speed = %d\n", lnk_speed);
922
923 return retval;
924 }
925
926 static int hpc_get_cur_lnk_width(struct slot *slot,
927 enum pcie_link_width *value)
928 {
929 struct controller *ctrl = slot->ctrl;
930 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
931 int retval = 0;
932 u16 lnk_status;
933
934 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
935 if (retval) {
936 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
937 return retval;
938 }
939
940 switch ((lnk_status & 0x03F0) >> 4){
941 case 0:
942 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
943 break;
944 case 1:
945 lnk_wdth = PCIE_LNK_X1;
946 break;
947 case 2:
948 lnk_wdth = PCIE_LNK_X2;
949 break;
950 case 4:
951 lnk_wdth = PCIE_LNK_X4;
952 break;
953 case 8:
954 lnk_wdth = PCIE_LNK_X8;
955 break;
956 case 12:
957 lnk_wdth = PCIE_LNK_X12;
958 break;
959 case 16:
960 lnk_wdth = PCIE_LNK_X16;
961 break;
962 case 32:
963 lnk_wdth = PCIE_LNK_X32;
964 break;
965 default:
966 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
967 break;
968 }
969
970 *value = lnk_wdth;
971 dbg("Current link width = %d\n", lnk_wdth);
972
973 return retval;
974 }
975
976 static struct hpc_ops pciehp_hpc_ops = {
977 .power_on_slot = hpc_power_on_slot,
978 .power_off_slot = hpc_power_off_slot,
979 .set_attention_status = hpc_set_attention_status,
980 .get_power_status = hpc_get_power_status,
981 .get_attention_status = hpc_get_attention_status,
982 .get_latch_status = hpc_get_latch_status,
983 .get_adapter_status = hpc_get_adapter_status,
984 .get_emi_status = hpc_get_emi_status,
985 .toggle_emi = hpc_toggle_emi,
986
987 .get_max_bus_speed = hpc_get_max_lnk_speed,
988 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
989 .get_max_lnk_width = hpc_get_max_lnk_width,
990 .get_cur_lnk_width = hpc_get_cur_lnk_width,
991
992 .query_power_fault = hpc_query_power_fault,
993 .green_led_on = hpc_set_green_led_on,
994 .green_led_off = hpc_set_green_led_off,
995 .green_led_blink = hpc_set_green_led_blink,
996
997 .release_ctlr = hpc_release_ctlr,
998 .check_lnk_status = hpc_check_lnk_status,
999 };
1000
1001 #ifdef CONFIG_ACPI
1002 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1003 {
1004 acpi_status status;
1005 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1006 struct pci_dev *pdev = dev;
1007 struct pci_bus *parent;
1008 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1009
1010 /*
1011 * Per PCI firmware specification, we should run the ACPI _OSC
1012 * method to get control of hotplug hardware before using it.
1013 * If an _OSC is missing, we look for an OSHP to do the same thing.
1014 * To handle different BIOS behavior, we look for _OSC and OSHP
1015 * within the scope of the hotplug controller and its parents, upto
1016 * the host bridge under which this controller exists.
1017 */
1018 while (!handle) {
1019 /*
1020 * This hotplug controller was not listed in the ACPI name
1021 * space at all. Try to get acpi handle of parent pci bus.
1022 */
1023 if (!pdev || !pdev->bus->parent)
1024 break;
1025 parent = pdev->bus->parent;
1026 dbg("Could not find %s in acpi namespace, trying parent\n",
1027 pci_name(pdev));
1028 if (!parent->self)
1029 /* Parent must be a host bridge */
1030 handle = acpi_get_pci_rootbridge_handle(
1031 pci_domain_nr(parent),
1032 parent->number);
1033 else
1034 handle = DEVICE_ACPI_HANDLE(
1035 &(parent->self->dev));
1036 pdev = parent->self;
1037 }
1038
1039 while (handle) {
1040 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1041 dbg("Trying to get hotplug control for %s \n",
1042 (char *)string.pointer);
1043 status = pci_osc_control_set(handle,
1044 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1045 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1046 if (status == AE_NOT_FOUND)
1047 status = acpi_run_oshp(handle);
1048 if (ACPI_SUCCESS(status)) {
1049 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1050 pci_name(dev), (char *)string.pointer);
1051 kfree(string.pointer);
1052 return 0;
1053 }
1054 if (acpi_root_bridge(handle))
1055 break;
1056 chandle = handle;
1057 status = acpi_get_parent(chandle, &handle);
1058 if (ACPI_FAILURE(status))
1059 break;
1060 }
1061
1062 err("Cannot get control of hotplug hardware for pci %s\n",
1063 pci_name(dev));
1064
1065 kfree(string.pointer);
1066 return -1;
1067 }
1068 #endif
1069
1070 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1071 {
1072 int rc;
1073 u16 temp_word;
1074 u16 cap_reg;
1075 u16 intr_enable = 0;
1076 u32 slot_cap;
1077 int cap_base;
1078 u16 slot_status, slot_ctrl;
1079 struct pci_dev *pdev;
1080
1081 pdev = dev->port;
1082 ctrl->pci_dev = pdev; /* save pci_dev in context */
1083
1084 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1085 __FUNCTION__, pdev->vendor, pdev->device);
1086
1087 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1088 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1089 goto abort_free_ctlr;
1090 }
1091
1092 ctrl->cap_base = cap_base;
1093
1094 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1095
1096 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1097 if (rc) {
1098 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1099 goto abort_free_ctlr;
1100 }
1101 dbg("%s: CAPREG offset %x cap_reg %x\n",
1102 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
1103
1104 if (((cap_reg & SLOT_IMPL) == 0) ||
1105 (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1106 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1107 dbg("%s : This is not a root port or the port is not "
1108 "connected to a slot\n", __FUNCTION__);
1109 goto abort_free_ctlr;
1110 }
1111
1112 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1113 if (rc) {
1114 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1115 goto abort_free_ctlr;
1116 }
1117 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1118 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1119
1120 if (!(slot_cap & HP_CAP)) {
1121 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1122 goto abort_free_ctlr;
1123 }
1124 /* For debugging purpose */
1125 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1126 if (rc) {
1127 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1128 goto abort_free_ctlr;
1129 }
1130 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1131 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
1132
1133 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1134 if (rc) {
1135 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1136 goto abort_free_ctlr;
1137 }
1138 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1139 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1140
1141 for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1142 if (pci_resource_len(pdev, rc) > 0)
1143 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1144 (unsigned long long)pci_resource_start(pdev, rc),
1145 (unsigned long long)pci_resource_len(pdev, rc));
1146
1147 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1148 pdev->vendor, pdev->device,
1149 pdev->subsystem_vendor, pdev->subsystem_device);
1150
1151 mutex_init(&ctrl->crit_sect);
1152 mutex_init(&ctrl->ctrl_lock);
1153 spin_lock_init(&ctrl->lock);
1154
1155 /* setup wait queue */
1156 init_waitqueue_head(&ctrl->queue);
1157
1158 /* return PCI Controller Info */
1159 ctrl->slot_device_offset = 0;
1160 ctrl->num_slots = 1;
1161 ctrl->first_slot = slot_cap >> 19;
1162 ctrl->ctrlcap = slot_cap & 0x0000007f;
1163
1164 /* Mask Hot-plug Interrupt Enable */
1165 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1166 if (rc) {
1167 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1168 goto abort_free_ctlr;
1169 }
1170
1171 dbg("%s: SLOTCTRL %x value read %x\n",
1172 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1173 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
1174 0x00;
1175
1176 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1177 if (rc) {
1178 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1179 goto abort_free_ctlr;
1180 }
1181
1182 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1183 if (rc) {
1184 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1185 goto abort_free_ctlr;
1186 }
1187
1188 temp_word = 0x1F; /* Clear all events */
1189 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1190 if (rc) {
1191 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1192 goto abort_free_ctlr;
1193 }
1194
1195 if (pciehp_poll_mode) {
1196 /* Install interrupt polling timer. Start with 10 sec delay */
1197 init_timer(&ctrl->poll_timer);
1198 start_int_poll_timer(ctrl, 10);
1199 } else {
1200 /* Installs the interrupt handler */
1201 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1202 MY_NAME, (void *)ctrl);
1203 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1204 __FUNCTION__, ctrl->pci_dev->irq,
1205 atomic_read(&pciehp_num_controllers), rc);
1206 if (rc) {
1207 err("Can't get irq %d for the hotplug controller\n",
1208 ctrl->pci_dev->irq);
1209 goto abort_free_ctlr;
1210 }
1211 }
1212 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1213 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1214
1215 /*
1216 * If this is the first controller to be initialized,
1217 * initialize the pciehp work queue
1218 */
1219 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1220 pciehp_wq = create_singlethread_workqueue("pciehpd");
1221 if (!pciehp_wq) {
1222 rc = -ENOMEM;
1223 goto abort_free_irq;
1224 }
1225 }
1226
1227 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1228 if (rc) {
1229 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1230 goto abort_free_irq;
1231 }
1232
1233 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1234
1235 if (ATTN_BUTTN(slot_cap))
1236 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1237
1238 if (POWER_CTRL(slot_cap))
1239 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1240
1241 if (MRL_SENS(slot_cap))
1242 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1243
1244 temp_word = (temp_word & ~intr_enable) | intr_enable;
1245
1246 if (pciehp_poll_mode) {
1247 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1248 } else {
1249 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1250 }
1251
1252 /*
1253 * Unmask Hot-plug Interrupt Enable for the interrupt
1254 * notification mechanism case.
1255 */
1256 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1257 if (rc) {
1258 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1259 goto abort_free_irq;
1260 }
1261 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1262 if (rc) {
1263 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1264 goto abort_disable_intr;
1265 }
1266
1267 temp_word = 0x1F; /* Clear all events */
1268 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1269 if (rc) {
1270 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1271 goto abort_disable_intr;
1272 }
1273
1274 if (pciehp_force) {
1275 dbg("Bypassing BIOS check for pciehp use on %s\n",
1276 pci_name(ctrl->pci_dev));
1277 } else {
1278 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1279 if (rc)
1280 goto abort_disable_intr;
1281 }
1282
1283 ctrl->hpc_ops = &pciehp_hpc_ops;
1284
1285 return 0;
1286
1287 /* We end up here for the many possible ways to fail this API. */
1288 abort_disable_intr:
1289 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1290 if (!rc) {
1291 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1292 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1293 }
1294 if (rc)
1295 err("%s : disabling interrupts failed\n", __FUNCTION__);
1296
1297 abort_free_irq:
1298 if (pciehp_poll_mode)
1299 del_timer_sync(&ctrl->poll_timer);
1300 else
1301 free_irq(ctrl->pci_dev->irq, ctrl);
1302
1303 abort_free_ctlr:
1304 return -1;
1305 }
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