arch/powerpc/boot/dcr.h

   1 #ifndef _PPC_BOOT_DCR_H_
   2 #define _PPC_BOOT_DCR_H_
   3
   4 #define mfdcr(rn) \
   5         ({      \
   6                 unsigned long rval; \
   7                 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
   8                 rval; \
   9         })
  10 #define mtdcr(rn, val) \
  11         asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
  12
  13 /* 440GP/440GX SDRAM controller DCRs */
  14 #define DCRN_SDRAM0_CFGADDR                             0x010
  15 #define DCRN_SDRAM0_CFGDATA                             0x011
  16
  17 #define         SDRAM0_B0CR                             0x40
  18 #define         SDRAM0_B1CR                             0x44
  19 #define         SDRAM0_B2CR                             0x48
  20 #define         SDRAM0_B3CR                             0x4c
  21
  22 static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
  23
  24 #define                 SDRAM_CONFIG_BANK_ENABLE        0x00000001
  25 #define                 SDRAM_CONFIG_SIZE_MASK          0x000e0000
  26 #define                 SDRAM_CONFIG_BANK_SIZE(reg)     \
  27         (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
  28
  29 /* 440GP Clock, PM, chip control */
  30 #define DCRN_CPC0_SR                                    0x0b0
  31 #define DCRN_CPC0_ER                                    0x0b1
  32 #define DCRN_CPC0_FR                                    0x0b2
  33 #define DCRN_CPC0_SYS0                                  0x0e0
  34 #define   CPC0_SYS0_TUNE                                  0xffc00000
  35 #define   CPC0_SYS0_FBDV_MASK                             0x003c0000
  36 #define   CPC0_SYS0_FWDVA_MASK                            0x00038000
  37 #define   CPC0_SYS0_FWDVB_MASK                            0x00007000
  38 #define   CPC0_SYS0_OPDV_MASK                             0x00000c00
  39 #define   CPC0_SYS0_EPDV_MASK                             0x00000300
  40 /* Helper macros to compute the actual clock divider values from the
  41  * encodings in the CPC0 register */
  42 #define   CPC0_SYS0_FBDV(reg) \
  43                 ((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
  44 #define   CPC0_SYS0_FWDVA(reg) \
  45                 (8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
  46 #define   CPC0_SYS0_FWDVB(reg) \
  47                 (8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
  48 #define   CPC0_SYS0_OPDV(reg) \
  49                 ((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
  50 #define   CPC0_SYS0_EPDV(reg) \
  51                 ((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
  52 #define   CPC0_SYS0_EXTSL                                 0x00000080
  53 #define   CPC0_SYS0_RW_MASK                               0x00000060
  54 #define   CPC0_SYS0_RL                                    0x00000010
  55 #define   CPC0_SYS0_ZMIISL_MASK                           0x0000000c
  56 #define   CPC0_SYS0_BYPASS                                0x00000002
  57 #define   CPC0_SYS0_NTO1                                  0x00000001
  58 #define DCRN_CPC0_SYS1                                  0x0e1
  59 #define DCRN_CPC0_CUST0                                 0x0e2
  60 #define DCRN_CPC0_CUST1                                 0x0e3
  61 #define DCRN_CPC0_STRP0                                 0x0e4
  62 #define DCRN_CPC0_STRP1                                 0x0e5
  63 #define DCRN_CPC0_STRP2                                 0x0e6
  64 #define DCRN_CPC0_STRP3                                 0x0e7
  65 #define DCRN_CPC0_GPIO                                  0x0e8
  66 #define DCRN_CPC0_PLB                                   0x0e9
  67 #define DCRN_CPC0_CR1                                   0x0ea
  68 #define DCRN_CPC0_CR0                                   0x0eb
  69 #define   CPC0_CR0_SWE                                    0x80000000
  70 #define   CPC0_CR0_CETE                                   0x40000000
  71 #define   CPC0_CR0_U1FCS                                  0x20000000
  72 #define   CPC0_CR0_U0DTE                                  0x10000000
  73 #define   CPC0_CR0_U0DRE                                  0x08000000
  74 #define   CPC0_CR0_U0DC                                   0x04000000
  75 #define   CPC0_CR0_U1DTE                                  0x02000000
  76 #define   CPC0_CR0_U1DRE                                  0x01000000
  77 #define   CPC0_CR0_U1DC                                   0x00800000
  78 #define   CPC0_CR0_U0EC                                   0x00400000
  79 #define   CPC0_CR0_U1EC                                   0x00200000
  80 #define   CPC0_CR0_UDIV_MASK                              0x001f0000
  81 #define   CPC0_CR0_UDIV(reg) \
  82                 ((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
  83 #define DCRN_CPC0_MIRQ0                                 0x0ec
  84 #define DCRN_CPC0_MIRQ1                                 0x0ed
  85 #define DCRN_CPC0_JTAGID                                0x0ef
  86
  87 #endif  /* _PPC_BOOT_DCR_H_ */