libata: request PHY speed configuration on SControl access failure
[pv_ops_mirror.git] / include / asm-alpha / auxvec.h
blobe96fe880e310fc91e0f8b74ab5e6a96a8b84388e
1 #ifndef __ASM_ALPHA_AUXVEC_H
2 #define __ASM_ALPHA_AUXVEC_H
4 /* Reserve these numbers for any future use of a VDSO. */
5 #if 0
6 #define AT_SYSINFO 32
7 #define AT_SYSINFO_EHDR 33
8 #endif
10 /* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
11 value is -1, then the cache doesn't exist. Otherwise:
13 bit 0-3: Cache set-associativity; 0 means fully associative.
14 bit 4-7: Log2 of cacheline size.
15 bit 8-31: Size of the entire cache >> 8.
16 bit 32-63: Reserved.
19 #define AT_L1I_CACHESHAPE 34
20 #define AT_L1D_CACHESHAPE 35
21 #define AT_L2_CACHESHAPE 36
22 #define AT_L3_CACHESHAPE 37
24 #endif /* __ASM_ALPHA_AUXVEC_H */