?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
alpha: fix trivial section mismatch warnings
[pv_ops_mirror.git] / drivers / usb / host / ehci-dbg.c
blobc9cc4413198e15d977a5d1e8b4d671eb2d72188a
1 /*
2 * Copyright (c) 2001-2002 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 /* this file is part of ehci-hcd.c */
20
21 #define ehci_dbg(ehci, fmt, args...) \
22 dev_dbg (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
23 #define ehci_err(ehci, fmt, args...) \
24 dev_err (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
25 #define ehci_info(ehci, fmt, args...) \
26 dev_info (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
27 #define ehci_warn(ehci, fmt, args...) \
28 dev_warn (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
29
30 #ifdef EHCI_VERBOSE_DEBUG
31 # define vdbg dbg
32 # define ehci_vdbg ehci_dbg
33 #else
34 # define vdbg(fmt,args...) do { } while (0)
35 # define ehci_vdbg(ehci, fmt, args...) do { } while (0)
36 #endif
37
38 #ifdef DEBUG
39
40 /* check the values in the HCSPARAMS register
41 * (host controller _Structural_ parameters)
42 * see EHCI spec, Table 2-4 for each value
43 */
44 static void dbg_hcs_params (struct ehci_hcd *ehci, char *label)
45 {
46 u32 params = ehci_readl(ehci, &ehci->caps->hcs_params);
47
48 ehci_dbg (ehci,
49 "%s hcs_params 0x%x dbg=%d%s cc=%d pcc=%d%s%s ports=%d\n",
50 label, params,
51 HCS_DEBUG_PORT (params),
52 HCS_INDICATOR (params) ? " ind" : "",
53 HCS_N_CC (params),
54 HCS_N_PCC (params),
55 HCS_PORTROUTED (params) ? "" : " ordered",
56 HCS_PPC (params) ? "" : " !ppc",
57 HCS_N_PORTS (params)
58 );
59 /* Port routing, per EHCI 0.95 Spec, Section 2.2.5 */
60 if (HCS_PORTROUTED (params)) {
61 int i;
62 char buf [46], tmp [7], byte;
63
64 buf[0] = 0;
65 for (i = 0; i < HCS_N_PORTS (params); i++) {
66 // FIXME MIPS won't readb() ...
67 byte = readb (&ehci->caps->portroute[(i>>1)]);
68 sprintf(tmp, "%d ",
69 ((i & 0x1) ? ((byte)&0xf) : ((byte>>4)&0xf)));
70 strcat(buf, tmp);
71 }
72 ehci_dbg (ehci, "%s portroute %s\n",
73 label, buf);
74 }
75 }
76 #else
77
78 static inline void dbg_hcs_params (struct ehci_hcd *ehci, char *label) {}
79
80 #endif
81
82 #ifdef DEBUG
83
84 /* check the values in the HCCPARAMS register
85 * (host controller _Capability_ parameters)
86 * see EHCI Spec, Table 2-5 for each value
87 * */
88 static void dbg_hcc_params (struct ehci_hcd *ehci, char *label)
89 {
90 u32 params = ehci_readl(ehci, &ehci->caps->hcc_params);
91
92 if (HCC_ISOC_CACHE (params)) {
93 ehci_dbg (ehci,
94 "%s hcc_params %04x caching frame %s%s%s\n",
95 label, params,
96 HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
97 HCC_CANPARK(params) ? " park" : "",
98 HCC_64BIT_ADDR(params) ? " 64 bit addr" : "");
99 } else {
100 ehci_dbg (ehci,
101 "%s hcc_params %04x thresh %d uframes %s%s%s\n",
102 label,
103 params,
104 HCC_ISOC_THRES(params),
105 HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
106 HCC_CANPARK(params) ? " park" : "",
107 HCC_64BIT_ADDR(params) ? " 64 bit addr" : "");
108 }
109 }
110 #else
111
112 static inline void dbg_hcc_params (struct ehci_hcd *ehci, char *label) {}
113
114 #endif
115
116 #ifdef DEBUG
117
118 static void __maybe_unused
119 dbg_qtd (const char *label, struct ehci_hcd *ehci, struct ehci_qtd *qtd)
120 {
121 ehci_dbg(ehci, "%s td %p n%08x %08x t%08x p0=%08x\n", label, qtd,
122 hc32_to_cpup(ehci, &qtd->hw_next),
123 hc32_to_cpup(ehci, &qtd->hw_alt_next),
124 hc32_to_cpup(ehci, &qtd->hw_token),
125 hc32_to_cpup(ehci, &qtd->hw_buf [0]));
126 if (qtd->hw_buf [1])
127 ehci_dbg(ehci, " p1=%08x p2=%08x p3=%08x p4=%08x\n",
128 hc32_to_cpup(ehci, &qtd->hw_buf[1]),
129 hc32_to_cpup(ehci, &qtd->hw_buf[2]),
130 hc32_to_cpup(ehci, &qtd->hw_buf[3]),
131 hc32_to_cpup(ehci, &qtd->hw_buf[4]));
132 }
133
134 static void __maybe_unused
135 dbg_qh (const char *label, struct ehci_hcd *ehci, struct ehci_qh *qh)
136 {
137 ehci_dbg (ehci, "%s qh %p n%08x info %x %x qtd %x\n", label,
138 qh, qh->hw_next, qh->hw_info1, qh->hw_info2,
139 qh->hw_current);
140 dbg_qtd ("overlay", ehci, (struct ehci_qtd *) &qh->hw_qtd_next);
141 }
142
143 static void __maybe_unused
144 dbg_itd (const char *label, struct ehci_hcd *ehci, struct ehci_itd *itd)
145 {
146 ehci_dbg (ehci, "%s [%d] itd %p, next %08x, urb %p\n",
147 label, itd->frame, itd, hc32_to_cpu(ehci, itd->hw_next),
148 itd->urb);
149 ehci_dbg (ehci,
150 " trans: %08x %08x %08x %08x %08x %08x %08x %08x\n",
151 hc32_to_cpu(ehci, itd->hw_transaction[0]),
152 hc32_to_cpu(ehci, itd->hw_transaction[1]),
153 hc32_to_cpu(ehci, itd->hw_transaction[2]),
154 hc32_to_cpu(ehci, itd->hw_transaction[3]),
155 hc32_to_cpu(ehci, itd->hw_transaction[4]),
156 hc32_to_cpu(ehci, itd->hw_transaction[5]),
157 hc32_to_cpu(ehci, itd->hw_transaction[6]),
158 hc32_to_cpu(ehci, itd->hw_transaction[7]));
159 ehci_dbg (ehci,
160 " buf: %08x %08x %08x %08x %08x %08x %08x\n",
161 hc32_to_cpu(ehci, itd->hw_bufp[0]),
162 hc32_to_cpu(ehci, itd->hw_bufp[1]),
163 hc32_to_cpu(ehci, itd->hw_bufp[2]),
164 hc32_to_cpu(ehci, itd->hw_bufp[3]),
165 hc32_to_cpu(ehci, itd->hw_bufp[4]),
166 hc32_to_cpu(ehci, itd->hw_bufp[5]),
167 hc32_to_cpu(ehci, itd->hw_bufp[6]));
168 ehci_dbg (ehci, " index: %d %d %d %d %d %d %d %d\n",
169 itd->index[0], itd->index[1], itd->index[2],
170 itd->index[3], itd->index[4], itd->index[5],
171 itd->index[6], itd->index[7]);
172 }
173
174 static void __maybe_unused
175 dbg_sitd (const char *label, struct ehci_hcd *ehci, struct ehci_sitd *sitd)
176 {
177 ehci_dbg (ehci, "%s [%d] sitd %p, next %08x, urb %p\n",
178 label, sitd->frame, sitd, hc32_to_cpu(ehci, sitd->hw_next),
179 sitd->urb);
180 ehci_dbg (ehci,
181 " addr %08x sched %04x result %08x buf %08x %08x\n",
182 hc32_to_cpu(ehci, sitd->hw_fullspeed_ep),
183 hc32_to_cpu(ehci, sitd->hw_uframe),
184 hc32_to_cpu(ehci, sitd->hw_results),
185 hc32_to_cpu(ehci, sitd->hw_buf[0]),
186 hc32_to_cpu(ehci, sitd->hw_buf[1]));
187 }
188
189 static int __maybe_unused
190 dbg_status_buf (char *buf, unsigned len, const char *label, u32 status)
191 {
192 return scnprintf (buf, len,
193 "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
194 label, label [0] ? " " : "", status,
195 (status & STS_ASS) ? " Async" : "",
196 (status & STS_PSS) ? " Periodic" : "",
197 (status & STS_RECL) ? " Recl" : "",
198 (status & STS_HALT) ? " Halt" : "",
199 (status & STS_IAA) ? " IAA" : "",
200 (status & STS_FATAL) ? " FATAL" : "",
201 (status & STS_FLR) ? " FLR" : "",
202 (status & STS_PCD) ? " PCD" : "",
203 (status & STS_ERR) ? " ERR" : "",
204 (status & STS_INT) ? " INT" : ""
205 );
206 }
207
208 static int __maybe_unused
209 dbg_intr_buf (char *buf, unsigned len, const char *label, u32 enable)
210 {
211 return scnprintf (buf, len,
212 "%s%sintrenable %02x%s%s%s%s%s%s",
213 label, label [0] ? " " : "", enable,
214 (enable & STS_IAA) ? " IAA" : "",
215 (enable & STS_FATAL) ? " FATAL" : "",
216 (enable & STS_FLR) ? " FLR" : "",
217 (enable & STS_PCD) ? " PCD" : "",
218 (enable & STS_ERR) ? " ERR" : "",
219 (enable & STS_INT) ? " INT" : ""
220 );
221 }
222
223 static const char *const fls_strings [] =
224 { "1024", "512", "256", "??" };
225
226 static int
227 dbg_command_buf (char *buf, unsigned len, const char *label, u32 command)
228 {
229 return scnprintf (buf, len,
230 "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
231 label, label [0] ? " " : "", command,
232 (command & CMD_PARK) ? "park" : "(park)",
233 CMD_PARK_CNT (command),
234 (command >> 16) & 0x3f,
235 (command & CMD_LRESET) ? " LReset" : "",
236 (command & CMD_IAAD) ? " IAAD" : "",
237 (command & CMD_ASE) ? " Async" : "",
238 (command & CMD_PSE) ? " Periodic" : "",
239 fls_strings [(command >> 2) & 0x3],
240 (command & CMD_RESET) ? " Reset" : "",
241 (command & CMD_RUN) ? "RUN" : "HALT"
242 );
243 }
244
245 static int
246 dbg_port_buf (char *buf, unsigned len, const char *label, int port, u32 status)
247 {
248 char *sig;
249
250 /* signaling state */
251 switch (status & (3 << 10)) {
252 case 0 << 10: sig = "se0"; break;
253 case 1 << 10: sig = "k"; break; /* low speed */
254 case 2 << 10: sig = "j"; break;
255 default: sig = "?"; break;
256 }
257
258 return scnprintf (buf, len,
259 "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
260 label, label [0] ? " " : "", port, status,
261 (status & PORT_POWER) ? " POWER" : "",
262 (status & PORT_OWNER) ? " OWNER" : "",
263 sig,
264 (status & PORT_RESET) ? " RESET" : "",
265 (status & PORT_SUSPEND) ? " SUSPEND" : "",
266 (status & PORT_RESUME) ? " RESUME" : "",
267 (status & PORT_OCC) ? " OCC" : "",
268 (status & PORT_OC) ? " OC" : "",
269 (status & PORT_PEC) ? " PEC" : "",
270 (status & PORT_PE) ? " PE" : "",
271 (status & PORT_CSC) ? " CSC" : "",
272 (status & PORT_CONNECT) ? " CONNECT" : "");
273 }
274
275 #else
276 static inline void __maybe_unused
277 dbg_qh (char *label, struct ehci_hcd *ehci, struct ehci_qh *qh)
278 {}
279
280 static inline int __maybe_unused
281 dbg_status_buf (char *buf, unsigned len, const char *label, u32 status)
282 { return 0; }
283
284 static inline int __maybe_unused
285 dbg_command_buf (char *buf, unsigned len, const char *label, u32 command)
286 { return 0; }
287
288 static inline int __maybe_unused
289 dbg_intr_buf (char *buf, unsigned len, const char *label, u32 enable)
290 { return 0; }
291
292 static inline int __maybe_unused
293 dbg_port_buf (char *buf, unsigned len, const char *label, int port, u32 status)
294 { return 0; }
295
296 #endif /* DEBUG */
297
298 /* functions have the "wrong" filename when they're output... */
299 #define dbg_status(ehci, label, status) { \
300 char _buf [80]; \
301 dbg_status_buf (_buf, sizeof _buf, label, status); \
302 ehci_dbg (ehci, "%s\n", _buf); \
303 }
304
305 #define dbg_cmd(ehci, label, command) { \
306 char _buf [80]; \
307 dbg_command_buf (_buf, sizeof _buf, label, command); \
308 ehci_dbg (ehci, "%s\n", _buf); \
309 }
310
311 #define dbg_port(ehci, label, port, status) { \
312 char _buf [80]; \
313 dbg_port_buf (_buf, sizeof _buf, label, port, status); \
314 ehci_dbg (ehci, "%s\n", _buf); \
315 }
316
317 /*-------------------------------------------------------------------------*/
318
319 #ifdef STUB_DEBUG_FILES
320
321 static inline void create_debug_files (struct ehci_hcd *bus) { }
322 static inline void remove_debug_files (struct ehci_hcd *bus) { }
323
324 #else
325
326 /* troubleshooting help: expose state in sysfs */
327
328 #define speed_char(info1) ({ char tmp; \
329 switch (info1 & (3 << 12)) { \
330 case 0 << 12: tmp = 'f'; break; \
331 case 1 << 12: tmp = 'l'; break; \
332 case 2 << 12: tmp = 'h'; break; \
333 default: tmp = '?'; break; \
334 }; tmp; })
335
336 static inline char token_mark(struct ehci_hcd *ehci, __hc32 token)
337 {
338 __u32 v = hc32_to_cpu(ehci, token);
339
340 if (v & QTD_STS_ACTIVE)
341 return '*';
342 if (v & QTD_STS_HALT)
343 return '-';
344 if (!IS_SHORT_READ (v))
345 return ' ';
346 /* tries to advance through hw_alt_next */
347 return '/';
348 }
349
350 static void qh_lines (
351 struct ehci_hcd *ehci,
352 struct ehci_qh *qh,
353 char **nextp,
354 unsigned *sizep
355 )
356 {
357 u32 scratch;
358 u32 hw_curr;
359 struct list_head *entry;
360 struct ehci_qtd *td;
361 unsigned temp;
362 unsigned size = *sizep;
363 char *next = *nextp;
364 char mark;
365 u32 list_end = EHCI_LIST_END(ehci);
366
367 if (qh->hw_qtd_next == list_end) /* NEC does this */
368 mark = '@';
369 else
370 mark = token_mark(ehci, qh->hw_token);
371 if (mark == '/') { /* qh_alt_next controls qh advance? */
372 if ((qh->hw_alt_next & QTD_MASK(ehci))
373 == ehci->async->hw_alt_next)
374 mark = '#'; /* blocked */
375 else if (qh->hw_alt_next == list_end)
376 mark = '.'; /* use hw_qtd_next */
377 /* else alt_next points to some other qtd */
378 }
379 scratch = hc32_to_cpup(ehci, &qh->hw_info1);
380 hw_curr = (mark == '*') ? hc32_to_cpup(ehci, &qh->hw_current) : 0;
381 temp = scnprintf (next, size,
382 "qh/%p dev%d %cs ep%d %08x %08x (%08x%c %s nak%d)",
383 qh, scratch & 0x007f,
384 speed_char (scratch),
385 (scratch >> 8) & 0x000f,
386 scratch, hc32_to_cpup(ehci, &qh->hw_info2),
387 hc32_to_cpup(ehci, &qh->hw_token), mark,
388 (cpu_to_hc32(ehci, QTD_TOGGLE) & qh->hw_token)
389 ? "data1" : "data0",
390 (hc32_to_cpup(ehci, &qh->hw_alt_next) >> 1) & 0x0f);
391 size -= temp;
392 next += temp;
393
394 /* hc may be modifying the list as we read it ... */
395 list_for_each (entry, &qh->qtd_list) {
396 td = list_entry (entry, struct ehci_qtd, qtd_list);
397 scratch = hc32_to_cpup(ehci, &td->hw_token);
398 mark = ' ';
399 if (hw_curr == td->qtd_dma)
400 mark = '*';
401 else if (qh->hw_qtd_next == cpu_to_hc32(ehci, td->qtd_dma))
402 mark = '+';
403 else if (QTD_LENGTH (scratch)) {
404 if (td->hw_alt_next == ehci->async->hw_alt_next)
405 mark = '#';
406 else if (td->hw_alt_next != list_end)
407 mark = '/';
408 }
409 temp = snprintf (next, size,
410 "\n\t%p%c%s len=%d %08x urb %p",
411 td, mark, ({ char *tmp;
412 switch ((scratch>>8)&0x03) {
413 case 0: tmp = "out"; break;
414 case 1: tmp = "in"; break;
415 case 2: tmp = "setup"; break;
416 default: tmp = "?"; break;
417 } tmp;}),
418 (scratch >> 16) & 0x7fff,
419 scratch,
420 td->urb);
421 if (temp < 0)
422 temp = 0;
423 else if (size < temp)
424 temp = size;
425 size -= temp;
426 next += temp;
427 if (temp == size)
428 goto done;
429 }
430
431 temp = snprintf (next, size, "\n");
432 if (temp < 0)
433 temp = 0;
434 else if (size < temp)
435 temp = size;
436 size -= temp;
437 next += temp;
438
439 done:
440 *sizep = size;
441 *nextp = next;
442 }
443
444 static ssize_t
445 show_async (struct class_device *class_dev, char *buf)
446 {
447 struct usb_bus *bus;
448 struct usb_hcd *hcd;
449 struct ehci_hcd *ehci;
450 unsigned long flags;
451 unsigned temp, size;
452 char *next;
453 struct ehci_qh *qh;
454
455 *buf = 0;
456
457 bus = class_get_devdata(class_dev);
458 hcd = bus_to_hcd(bus);
459 ehci = hcd_to_ehci (hcd);
460 next = buf;
461 size = PAGE_SIZE;
462
463 /* dumps a snapshot of the async schedule.
464 * usually empty except for long-term bulk reads, or head.
465 * one QH per line, and TDs we know about
466 */
467 spin_lock_irqsave (&ehci->lock, flags);
468 for (qh = ehci->async->qh_next.qh; size > 0 && qh; qh = qh->qh_next.qh)
469 qh_lines (ehci, qh, &next, &size);
470 if (ehci->reclaim && size > 0) {
471 temp = scnprintf (next, size, "\nreclaim =\n");
472 size -= temp;
473 next += temp;
474
475 for (qh = ehci->reclaim; size > 0 && qh; qh = qh->reclaim)
476 qh_lines (ehci, qh, &next, &size);
477 }
478 spin_unlock_irqrestore (&ehci->lock, flags);
479
480 return strlen (buf);
481 }
482 static CLASS_DEVICE_ATTR (async, S_IRUGO, show_async, NULL);
483
484 #define DBG_SCHED_LIMIT 64
485
486 static ssize_t
487 show_periodic (struct class_device *class_dev, char *buf)
488 {
489 struct usb_bus *bus;
490 struct usb_hcd *hcd;
491 struct ehci_hcd *ehci;
492 unsigned long flags;
493 union ehci_shadow p, *seen;
494 unsigned temp, size, seen_count;
495 char *next;
496 unsigned i;
497 __hc32 tag;
498
499 if (!(seen = kmalloc (DBG_SCHED_LIMIT * sizeof *seen, GFP_ATOMIC)))
500 return 0;
501 seen_count = 0;
502
503 bus = class_get_devdata(class_dev);
504 hcd = bus_to_hcd(bus);
505 ehci = hcd_to_ehci (hcd);
506 next = buf;
507 size = PAGE_SIZE;
508
509 temp = scnprintf (next, size, "size = %d\n", ehci->periodic_size);
510 size -= temp;
511 next += temp;
512
513 /* dump a snapshot of the periodic schedule.
514 * iso changes, interrupt usually doesn't.
515 */
516 spin_lock_irqsave (&ehci->lock, flags);
517 for (i = 0; i < ehci->periodic_size; i++) {
518 p = ehci->pshadow [i];
519 if (likely (!p.ptr))
520 continue;
521 tag = Q_NEXT_TYPE(ehci, ehci->periodic [i]);
522
523 temp = scnprintf (next, size, "%4d: ", i);
524 size -= temp;
525 next += temp;
526
527 do {
528 switch (hc32_to_cpu(ehci, tag)) {
529 case Q_TYPE_QH:
530 temp = scnprintf (next, size, " qh%d-%04x/%p",
531 p.qh->period,
532 hc32_to_cpup(ehci,
533 &p.qh->hw_info2)
534 /* uframe masks */
535 & (QH_CMASK | QH_SMASK),
536 p.qh);
537 size -= temp;
538 next += temp;
539 /* don't repeat what follows this qh */
540 for (temp = 0; temp < seen_count; temp++) {
541 if (seen [temp].ptr != p.ptr)
542 continue;
543 if (p.qh->qh_next.ptr)
544 temp = scnprintf (next, size,
545 " ...");
546 p.ptr = NULL;
547 break;
548 }
549 /* show more info the first time around */
550 if (temp == seen_count && p.ptr) {
551 u32 scratch = hc32_to_cpup(ehci,
552 &p.qh->hw_info1);
553 struct ehci_qtd *qtd;
554 char *type = "";
555
556 /* count tds, get ep direction */
557 temp = 0;
558 list_for_each_entry (qtd,
559 &p.qh->qtd_list,
560 qtd_list) {
561 temp++;
562 switch (0x03 & (hc32_to_cpu(
563 ehci,
564 qtd->hw_token) >> 8)) {
565 case 0: type = "out"; continue;
566 case 1: type = "in"; continue;
567 }
568 }
569
570 temp = scnprintf (next, size,
571 " (%c%d ep%d%s "
572 "[%d/%d] q%d p%d)",
573 speed_char (scratch),
574 scratch & 0x007f,
575 (scratch >> 8) & 0x000f, type,
576 p.qh->usecs, p.qh->c_usecs,
577 temp,
578 0x7ff & (scratch >> 16));
579
580 if (seen_count < DBG_SCHED_LIMIT)
581 seen [seen_count++].qh = p.qh;
582 } else
583 temp = 0;
584 if (p.qh) {
585 tag = Q_NEXT_TYPE(ehci, p.qh->hw_next);
586 p = p.qh->qh_next;
587 }
588 break;
589 case Q_TYPE_FSTN:
590 temp = scnprintf (next, size,
591 " fstn-%8x/%p", p.fstn->hw_prev,
592 p.fstn);
593 tag = Q_NEXT_TYPE(ehci, p.fstn->hw_next);
594 p = p.fstn->fstn_next;
595 break;
596 case Q_TYPE_ITD:
597 temp = scnprintf (next, size,
598 " itd/%p", p.itd);
599 tag = Q_NEXT_TYPE(ehci, p.itd->hw_next);
600 p = p.itd->itd_next;
601 break;
602 case Q_TYPE_SITD:
603 temp = scnprintf (next, size,
604 " sitd%d-%04x/%p",
605 p.sitd->stream->interval,
606 hc32_to_cpup(ehci, &p.sitd->hw_uframe)
607 & 0x0000ffff,
608 p.sitd);
609 tag = Q_NEXT_TYPE(ehci, p.sitd->hw_next);
610 p = p.sitd->sitd_next;
611 break;
612 }
613 size -= temp;
614 next += temp;
615 } while (p.ptr);
616
617 temp = scnprintf (next, size, "\n");
618 size -= temp;
619 next += temp;
620 }
621 spin_unlock_irqrestore (&ehci->lock, flags);
622 kfree (seen);
623
624 return PAGE_SIZE - size;
625 }
626 static CLASS_DEVICE_ATTR (periodic, S_IRUGO, show_periodic, NULL);
627
628 #undef DBG_SCHED_LIMIT
629
630 static ssize_t
631 show_registers (struct class_device *class_dev, char *buf)
632 {
633 struct usb_bus *bus;
634 struct usb_hcd *hcd;
635 struct ehci_hcd *ehci;
636 unsigned long flags;
637 unsigned temp, size, i;
638 char *next, scratch [80];
639 static char fmt [] = "%*s\n";
640 static char label [] = "";
641
642 bus = class_get_devdata(class_dev);
643 hcd = bus_to_hcd(bus);
644 ehci = hcd_to_ehci (hcd);
645 next = buf;
646 size = PAGE_SIZE;
647
648 spin_lock_irqsave (&ehci->lock, flags);
649
650 if (bus->controller->power.power_state.event) {
651 size = scnprintf (next, size,
652 "bus %s, device %s (driver " DRIVER_VERSION ")\n"
653 "%s\n"
654 "SUSPENDED (no register access)\n",
655 hcd->self.controller->bus->name,
656 hcd->self.controller->bus_id,
657 hcd->product_desc);
658 goto done;
659 }
660
661 /* Capability Registers */
662 i = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
663 temp = scnprintf (next, size,
664 "bus %s, device %s (driver " DRIVER_VERSION ")\n"
665 "%s\n"
666 "EHCI %x.%02x, hcd state %d\n",
667 hcd->self.controller->bus->name,
668 hcd->self.controller->bus_id,
669 hcd->product_desc,
670 i >> 8, i & 0x0ff, hcd->state);
671 size -= temp;
672 next += temp;
673
674 #ifdef CONFIG_PCI
675 /* EHCI 0.96 and later may have "extended capabilities" */
676 if (hcd->self.controller->bus == &pci_bus_type) {
677 struct pci_dev *pdev;
678 u32 offset, cap, cap2;
679 unsigned count = 256/4;
680
681 pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
682 offset = HCC_EXT_CAPS(ehci_readl(ehci,
683 &ehci->caps->hcc_params));
684 while (offset && count--) {
685 pci_read_config_dword (pdev, offset, &cap);
686 switch (cap & 0xff) {
687 case 1:
688 temp = scnprintf (next, size,
689 "ownership %08x%s%s\n", cap,
690 (cap & (1 << 24)) ? " linux" : "",
691 (cap & (1 << 16)) ? " firmware" : "");
692 size -= temp;
693 next += temp;
694
695 offset += 4;
696 pci_read_config_dword (pdev, offset, &cap2);
697 temp = scnprintf (next, size,
698 "SMI sts/enable 0x%08x\n", cap2);
699 size -= temp;
700 next += temp;
701 break;
702 case 0: /* illegal reserved capability */
703 cap = 0;
704 /* FALLTHROUGH */
705 default: /* unknown */
706 break;
707 }
708 temp = (cap >> 8) & 0xff;
709 }
710 }
711 #endif
712
713 // FIXME interpret both types of params
714 i = ehci_readl(ehci, &ehci->caps->hcs_params);
715 temp = scnprintf (next, size, "structural params 0x%08x\n", i);
716 size -= temp;
717 next += temp;
718
719 i = ehci_readl(ehci, &ehci->caps->hcc_params);
720 temp = scnprintf (next, size, "capability params 0x%08x\n", i);
721 size -= temp;
722 next += temp;
723
724 /* Operational Registers */
725 temp = dbg_status_buf (scratch, sizeof scratch, label,
726 ehci_readl(ehci, &ehci->regs->status));
727 temp = scnprintf (next, size, fmt, temp, scratch);
728 size -= temp;
729 next += temp;
730
731 temp = dbg_command_buf (scratch, sizeof scratch, label,
732 ehci_readl(ehci, &ehci->regs->command));
733 temp = scnprintf (next, size, fmt, temp, scratch);
734 size -= temp;
735 next += temp;
736
737 temp = dbg_intr_buf (scratch, sizeof scratch, label,
738 ehci_readl(ehci, &ehci->regs->intr_enable));
739 temp = scnprintf (next, size, fmt, temp, scratch);
740 size -= temp;
741 next += temp;
742
743 temp = scnprintf (next, size, "uframe %04x\n",
744 ehci_readl(ehci, &ehci->regs->frame_index));
745 size -= temp;
746 next += temp;
747
748 for (i = 1; i <= HCS_N_PORTS (ehci->hcs_params); i++) {
749 temp = dbg_port_buf (scratch, sizeof scratch, label, i,
750 ehci_readl(ehci,
751 &ehci->regs->port_status[i - 1]));
752 temp = scnprintf (next, size, fmt, temp, scratch);
753 size -= temp;
754 next += temp;
755 if (i == HCS_DEBUG_PORT(ehci->hcs_params) && ehci->debug) {
756 temp = scnprintf (next, size,
757 " debug control %08x\n",
758 ehci_readl(ehci,
759 &ehci->debug->control));
760 size -= temp;
761 next += temp;
762 }
763 }
764
765 if (ehci->reclaim) {
766 temp = scnprintf (next, size, "reclaim qh %p%s\n",
767 ehci->reclaim,
768 ehci->reclaim_ready ? " ready" : "");
769 size -= temp;
770 next += temp;
771 }
772
773 #ifdef EHCI_STATS
774 temp = scnprintf (next, size,
775 "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
776 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
777 ehci->stats.lost_iaa);
778 size -= temp;
779 next += temp;
780
781 temp = scnprintf (next, size, "complete %ld unlink %ld\n",
782 ehci->stats.complete, ehci->stats.unlink);
783 size -= temp;
784 next += temp;
785 #endif
786
787 done:
788 spin_unlock_irqrestore (&ehci->lock, flags);
789
790 return PAGE_SIZE - size;
791 }
792 static CLASS_DEVICE_ATTR (registers, S_IRUGO, show_registers, NULL);
793
794 static inline void create_debug_files (struct ehci_hcd *ehci)
795 {
796 struct class_device *cldev = ehci_to_hcd(ehci)->self.class_dev;
797 int retval;
798
799 retval = class_device_create_file(cldev, &class_device_attr_async);
800 retval = class_device_create_file(cldev, &class_device_attr_periodic);
801 retval = class_device_create_file(cldev, &class_device_attr_registers);
802 }
803
804 static inline void remove_debug_files (struct ehci_hcd *ehci)
805 {
806 struct class_device *cldev = ehci_to_hcd(ehci)->self.class_dev;
807
808 class_device_remove_file(cldev, &class_device_attr_async);
809 class_device_remove_file(cldev, &class_device_attr_periodic);
810 class_device_remove_file(cldev, &class_device_attr_registers);
811 }
812
813 #endif /* STUB_DEBUG_FILES */
814
Mirror for ia64_pv_ops.git