| commit | 4af2b1454da7a2feec071a6a50dd957df7d0b7a7 | |
| author | Ralf Baechle <ralf@linux-mips.org> | |
| Mon, 3 Sep 2007 14:22:26 +0000 (3 16:22 +0200) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Tue, 11 Sep 2007 18:03:25 +0000 (11 19:03 +0100) | ||
| tree | 5a930850752154a0a9e4b4458f67b04e756bf744 | treesnapshot (tar.gz zip) |
| parent | 76e7f79950b54eb17f4041d020811331b7ae1a9e | commitdiff |
[MIPS] Provide empty irq_enable_hazard definition for legacy and R1 cores.
Following a strict interpretation the empty definition of irq_enable_hazard
has always been a bug - but an intentional one because it didn't bite.
This has now changed, for uniprocessor kernels mm/slab.c:do_drain()
[...]
on_each_cpu(do_drain, cachep, 1, 1);
check_irq_on();
[...]
may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting
in a back-to-back hazard.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Following a strict interpretation the empty definition of irq_enable_hazard
has always been a bug - but an intentional one because it didn't bite.
This has now changed, for uniprocessor kernels mm/slab.c:do_drain()
[...]
on_each_cpu(do_drain, cachep, 1, 1);
check_irq_on();
[...]
may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting
in a back-to-back hazard.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| include/asm-mips/hazards.h | diffblobblamehistory |