| commit | 7b0fdaa6a193e0b07d9f72e942f51ce25d9e0387 | |
| author | Ralf Baechle <ralf@linux-mips.org> | |
| Mon, 3 Sep 2007 14:22:26 +0000 (3 16:22 +0200) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Mon, 10 Sep 2007 20:25:28 +0000 (10 21:25 +0100) | ||
| tree | 5a930850752154a0a9e4b4458f67b04e756bf744 | treesnapshot (tar.gz zip) |
| parent | 2e4dafd5d169ea2d5b066e38b5f8f9e416dc9eaa | commitdiff |
[MIPS] Provide empty irq_enable_hazard definition for legacy and R1 cores.
Following a strict interpretation the empty definition of irq_enable_hazard
has always been a bug - but an intentional one because it didn't bite.
This has now changed, for uniprocessor kernels mm/slab.c:do_drain()
[...]
on_each_cpu(do_drain, cachep, 1, 1);
check_irq_on();
[...]
may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting
in a back-to-back hazard.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Following a strict interpretation the empty definition of irq_enable_hazard
has always been a bug - but an intentional one because it didn't bite.
This has now changed, for uniprocessor kernels mm/slab.c:do_drain()
[...]
on_each_cpu(do_drain, cachep, 1, 1);
check_irq_on();
[...]
may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting
in a back-to-back hazard.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| include/asm-mips/hazards.h | diffblobblamehistory |