hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "qemu-timer.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #ifdef USE_KVM
  27 #include "qemu-kvm.h"
  28 #endif
  29 #include "string.h"
  30
  31 //#define DEBUG
  32
  33 /* i82731AB (PIIX4) compatible power management function */
  34 #define PM_FREQ 3579545
  35
  36 #define ACPI_DBG_IO_ADDR  0xb044
  37
  38 typedef struct PIIX4PMState {
  39     PCIDevice dev;
  40     uint16_t pmsts;
  41     uint16_t pmen;
  42     uint16_t pmcntrl;
  43     uint8_t apmc;
  44     uint8_t apms;
  45     QEMUTimer *tmr_timer;
  46     int64_t tmr_overflow_time;
  47     i2c_bus *smbus;
  48     uint8_t smb_stat;
  49     uint8_t smb_ctl;
  50     uint8_t smb_cmd;
  51     uint8_t smb_addr;
  52     uint8_t smb_data0;
  53     uint8_t smb_data1;
  54     uint8_t smb_data[32];
  55     uint8_t smb_index;
  56     qemu_irq irq;
  57 } PIIX4PMState;
  58
  59 #define RTC_EN (1 << 10)
  60 #define PWRBTN_EN (1 << 8)
  61 #define GBL_EN (1 << 5)
  62 #define TMROF_EN (1 << 0)
  63
  64 #define SCI_EN (1 << 0)
  65
  66 #define SUS_EN (1 << 13)
  67
  68 #define ACPI_ENABLE 0xf1
  69 #define ACPI_DISABLE 0xf0
  70
  71 #define SMBHSTSTS 0x00
  72 #define SMBHSTCNT 0x02
  73 #define SMBHSTCMD 0x03
  74 #define SMBHSTADD 0x04
  75 #define SMBHSTDAT0 0x05
  76 #define SMBHSTDAT1 0x06
  77 #define SMBBLKDAT 0x07
  78
  79 static PIIX4PMState *pm_state;
  80
  81 static uint32_t get_pmtmr(PIIX4PMState *s)
  82 {
  83     uint32_t d;
  84     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  85     return d & 0xffffff;
  86 }
  87
  88 static int get_pmsts(PIIX4PMState *s)
  89 {
  90     int64_t d;
  91     int pmsts;
  92     pmsts = s->pmsts;
  93     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  94     if (d >= s->tmr_overflow_time)
  95         s->pmsts |= TMROF_EN;
  96     return pmsts;
  97 }
  98
  99 static void pm_update_sci(PIIX4PMState *s)
 100 {
 101     int sci_level, pmsts;
 102     int64_t expire_time;
 103
 104     pmsts = get_pmsts(s);
 105     sci_level = (((pmsts & s->pmen) &
 106                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 107     qemu_set_irq(s->irq, sci_level);
 108     /* schedule a timer interruption if needed */
 109     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 110         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
 111         qemu_mod_timer(s->tmr_timer, expire_time);
 112     } else {
 113         qemu_del_timer(s->tmr_timer);
 114     }
 115 }
 116
 117 static void pm_tmr_timer(void *opaque)
 118 {
 119     PIIX4PMState *s = opaque;
 120     pm_update_sci(s);
 121 }
 122
 123 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 124 {
 125     PIIX4PMState *s = opaque;
 126     addr &= 0x3f;
 127     switch(addr) {
 128     case 0x00:
 129         {
 130             int64_t d;
 131             int pmsts;
 132             pmsts = get_pmsts(s);
 133             if (pmsts & val & TMROF_EN) {
 134                 /* if TMRSTS is reset, then compute the new overflow time */
 135                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 136                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 137             }
 138             s->pmsts &= ~val;
 139             pm_update_sci(s);
 140         }
 141         break;
 142     case 0x02:
 143         s->pmen = val;
 144         pm_update_sci(s);
 145         break;
 146     case 0x04:
 147         {
 148             int sus_typ;
 149             s->pmcntrl = val & ~(SUS_EN);
 150             if (val & SUS_EN) {
 151                 /* change suspend type */
 152                 sus_typ = (val >> 10) & 7;
 153                 switch(sus_typ) {
 154                 case 0: /* soft power off */
 155                     qemu_system_shutdown_request();
 156                     break;
 157                 default:
 158                     break;
 159                 }
 160             }
 161         }
 162         break;
 163     default:
 164         break;
 165     }
 166 #ifdef DEBUG
 167     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 168 #endif
 169 }
 170
 171 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 172 {
 173     PIIX4PMState *s = opaque;
 174     uint32_t val;
 175
 176     addr &= 0x3f;
 177     switch(addr) {
 178     case 0x00:
 179         val = get_pmsts(s);
 180         break;
 181     case 0x02:
 182         val = s->pmen;
 183         break;
 184     case 0x04:
 185         val = s->pmcntrl;
 186         break;
 187     default:
 188         val = 0;
 189         break;
 190     }
 191 #ifdef DEBUG
 192     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 193 #endif
 194     return val;
 195 }
 196
 197 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 198 {
 199     //    PIIX4PMState *s = opaque;
 200     addr &= 0x3f;
 201 #ifdef DEBUG
 202     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 203 #endif
 204 }
 205
 206 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 207 {
 208     PIIX4PMState *s = opaque;
 209     uint32_t val;
 210
 211     addr &= 0x3f;
 212     switch(addr) {
 213     case 0x08:
 214         val = get_pmtmr(s);
 215         break;
 216     default:
 217         val = 0;
 218         break;
 219     }
 220 #ifdef DEBUG
 221     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 222 #endif
 223     return val;
 224 }
 225
 226 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 227 {
 228     PIIX4PMState *s = opaque;
 229     addr &= 1;
 230 #ifdef DEBUG
 231     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 232 #endif
 233     if (addr == 0) {
 234         s->apmc = val;
 235
 236         /* ACPI specs 3.0, 4.7.2.5 */
 237         if (val == ACPI_ENABLE) {
 238             s->pmcntrl |= SCI_EN;
 239         } else if (val == ACPI_DISABLE) {
 240             s->pmcntrl &= ~SCI_EN;
 241         }
 242
 243         if (s->dev.config[0x5b] & (1 << 1)) {
 244             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 245         }
 246     } else {
 247         s->apms = val;
 248     }
 249 }
 250
 251 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 252 {
 253     PIIX4PMState *s = opaque;
 254     uint32_t val;
 255
 256     addr &= 1;
 257     if (addr == 0) {
 258         val = s->apmc;
 259     } else {
 260         val = s->apms;
 261     }
 262 #ifdef DEBUG
 263     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 264 #endif
 265     return val;
 266 }
 267
 268 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 269 {
 270 #if defined(DEBUG)
 271     printf("ACPI: DBG: 0x%08x\n", val);
 272 #endif
 273 }
 274
 275 static void smb_transaction(PIIX4PMState *s)
 276 {
 277     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 278     uint8_t read = s->smb_addr & 0x01;
 279     uint8_t cmd = s->smb_cmd;
 280     uint8_t addr = s->smb_addr >> 1;
 281     i2c_bus *bus = s->smbus;
 282
 283 #ifdef DEBUG
 284     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 285 #endif
 286     switch(prot) {
 287     case 0x0:
 288         smbus_quick_command(bus, addr, read);
 289         break;
 290     case 0x1:
 291         if (read) {
 292             s->smb_data0 = smbus_receive_byte(bus, addr);
 293         } else {
 294             smbus_send_byte(bus, addr, cmd);
 295         }
 296         break;
 297     case 0x2:
 298         if (read) {
 299             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 300         } else {
 301             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 302         }
 303         break;
 304     case 0x3:
 305         if (read) {
 306             uint16_t val;
 307             val = smbus_read_word(bus, addr, cmd);
 308             s->smb_data0 = val;
 309             s->smb_data1 = val >> 8;
 310         } else {
 311             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 312         }
 313         break;
 314     case 0x5:
 315         if (read) {
 316             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 317         } else {
 318             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 319         }
 320         break;
 321     default:
 322         goto error;
 323     }
 324     return;
 325
 326   error:
 327     s->smb_stat |= 0x04;
 328 }
 329
 330 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 331 {
 332     PIIX4PMState *s = opaque;
 333     addr &= 0x3f;
 334 #ifdef DEBUG
 335     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 336 #endif
 337     switch(addr) {
 338     case SMBHSTSTS:
 339         s->smb_stat = 0;
 340         s->smb_index = 0;
 341         break;
 342     case SMBHSTCNT:
 343         s->smb_ctl = val;
 344         if (val & 0x40)
 345             smb_transaction(s);
 346         break;
 347     case SMBHSTCMD:
 348         s->smb_cmd = val;
 349         break;
 350     case SMBHSTADD:
 351         s->smb_addr = val;
 352         break;
 353     case SMBHSTDAT0:
 354         s->smb_data0 = val;
 355         break;
 356     case SMBHSTDAT1:
 357         s->smb_data1 = val;
 358         break;
 359     case SMBBLKDAT:
 360         s->smb_data[s->smb_index++] = val;
 361         if (s->smb_index > 31)
 362             s->smb_index = 0;
 363         break;
 364     default:
 365         break;
 366     }
 367 }
 368
 369 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 370 {
 371     PIIX4PMState *s = opaque;
 372     uint32_t val;
 373
 374     addr &= 0x3f;
 375     switch(addr) {
 376     case SMBHSTSTS:
 377         val = s->smb_stat;
 378         break;
 379     case SMBHSTCNT:
 380         s->smb_index = 0;
 381         val = s->smb_ctl & 0x1f;
 382         break;
 383     case SMBHSTCMD:
 384         val = s->smb_cmd;
 385         break;
 386     case SMBHSTADD:
 387         val = s->smb_addr;
 388         break;
 389     case SMBHSTDAT0:
 390         val = s->smb_data0;
 391         break;
 392     case SMBHSTDAT1:
 393         val = s->smb_data1;
 394         break;
 395     case SMBBLKDAT:
 396         val = s->smb_data[s->smb_index++];
 397         if (s->smb_index > 31)
 398             s->smb_index = 0;
 399         break;
 400     default:
 401         val = 0;
 402         break;
 403     }
 404 #ifdef DEBUG
 405     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 406 #endif
 407     return val;
 408 }
 409
 410 static void pm_io_space_update(PIIX4PMState *s)
 411 {
 412     uint32_t pm_io_base;
 413
 414     if (s->dev.config[0x80] & 1) {
 415         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 416         pm_io_base &= 0xffc0;
 417
 418         /* XXX: need to improve memory and ioport allocation */
 419 #if defined(DEBUG)
 420         printf("PM: mapping to 0x%x\n", pm_io_base);
 421 #endif
 422         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 423         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 424         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 425         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 426     }
 427 }
 428
 429 static void pm_write_config(PCIDevice *d,
 430                             uint32_t address, uint32_t val, int len)
 431 {
 432     pci_default_write_config(d, address, val, len);
 433     if (address == 0x80)
 434         pm_io_space_update((PIIX4PMState *)d);
 435 }
 436
 437 static void pm_save(QEMUFile* f,void *opaque)
 438 {
 439     PIIX4PMState *s = opaque;
 440
 441     pci_device_save(&s->dev, f);
 442
 443     qemu_put_be16s(f, &s->pmsts);
 444     qemu_put_be16s(f, &s->pmen);
 445     qemu_put_be16s(f, &s->pmcntrl);
 446     qemu_put_8s(f, &s->apmc);
 447     qemu_put_8s(f, &s->apms);
 448     qemu_put_timer(f, s->tmr_timer);
 449     qemu_put_be64(f, s->tmr_overflow_time);
 450 }
 451
 452 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 453 {
 454     PIIX4PMState *s = opaque;
 455     int ret;
 456
 457     if (version_id > 1)
 458         return -EINVAL;
 459
 460     ret = pci_device_load(&s->dev, f);
 461     if (ret < 0)
 462         return ret;
 463
 464     qemu_get_be16s(f, &s->pmsts);
 465     qemu_get_be16s(f, &s->pmen);
 466     qemu_get_be16s(f, &s->pmcntrl);
 467     qemu_get_8s(f, &s->apmc);
 468     qemu_get_8s(f, &s->apms);
 469     qemu_get_timer(f, s->tmr_timer);
 470     s->tmr_overflow_time=qemu_get_be64(f);
 471
 472     pm_io_space_update(s);
 473
 474     return 0;
 475 }
 476
 477 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 478                        qemu_irq sci_irq)
 479 {
 480     PIIX4PMState *s;
 481     uint8_t *pci_conf;
 482
 483     s = (PIIX4PMState *)pci_register_device(bus,
 484                                          "PM", sizeof(PIIX4PMState),
 485                                          devfn, NULL, pm_write_config);
 486     pm_state = s;
 487     pci_conf = s->dev.config;
 488     pci_conf[0x00] = 0x86;
 489     pci_conf[0x01] = 0x80;
 490     pci_conf[0x02] = 0x13;
 491     pci_conf[0x03] = 0x71;
 492     pci_conf[0x06] = 0x80;
 493     pci_conf[0x07] = 0x02;
 494     pci_conf[0x08] = 0x03; // revision number
 495     pci_conf[0x09] = 0x00;
 496     pci_conf[0x0a] = 0x80; // other bridge device
 497     pci_conf[0x0b] = 0x06; // bridge device
 498     pci_conf[0x0e] = 0x00; // header_type
 499     pci_conf[0x3d] = 0x01; // interrupt pin 1
 500
 501     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 502
 503 #if defined(TARGET_IA64)
 504     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 505     pci_conf[0x41] = 0x1f;
 506     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 507 #endif
 508
 509     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 510     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 511
 512     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 513
 514     /* XXX: which specification is used ? The i82731AB has different
 515        mappings */
 516     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 517     pci_conf[0x63] = 0x60;
 518     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 519         (serial_hds[1] != NULL ? 0x90 : 0);
 520
 521     pci_conf[0x90] = smb_io_base | 1;
 522     pci_conf[0x91] = smb_io_base >> 8;
 523     pci_conf[0xd2] = 0x09;
 524     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 525     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 526
 527     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 528
 529     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 530
 531     s->smbus = i2c_init_bus();
 532     s->irq = sci_irq;
 533     return s->smbus;
 534 }
 535
 536 #if defined(TARGET_I386)
 537 void qemu_system_powerdown(void)
 538 {
 539     if (!pm_state) {
 540         qemu_system_shutdown_request();
 541     } else if (pm_state->pmen & PWRBTN_EN) {
 542         pm_state->pmsts |= PWRBTN_EN;
 543         pm_update_sci(pm_state);
 544     }
 545 }
 546 #endif
 547 #define GPE_BASE 0xafe0
 548 #define PROC_BASE 0xaf00
 549 #define PCI_BASE 0xae00
 550 #define PCI_EJ_BASE 0xae08
 551
 552 struct gpe_regs {
 553     uint16_t sts; /* status */
 554     uint16_t en;  /* enabled */
 555     uint8_t up;
 556     uint8_t down;
 557 };
 558
 559 struct pci_status {
 560     uint32_t up;
 561     uint32_t down;
 562 };
 563
 564 static struct gpe_regs gpe;
 565 static struct pci_status pci0_status;
 566
 567 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 568 {
 569     uint32_t val = 0;
 570     struct gpe_regs *g = opaque;
 571     switch (addr) {
 572         case PROC_BASE:
 573             val = g->up;
 574             break;
 575         case PROC_BASE + 1:
 576             val = g->down;
 577             break;
 578
 579         case GPE_BASE:
 580             val = g->sts & 0xFF;
 581             break;
 582         case GPE_BASE + 1:
 583             val =  (g->sts >> 8) & 0xFF;
 584             break;
 585         case GPE_BASE + 2:
 586             val =  g->en & 0xFF;
 587             break;
 588         case GPE_BASE + 3:
 589             val =  (g->en >> 8) & 0xFF;
 590             break;
 591         default:
 592             break;
 593     }
 594
 595 #if defined(DEBUG)
 596     printf("gpe read %x == %x\n", addr, val);
 597 #endif
 598     return val;
 599 }
 600
 601 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 602 {
 603     struct gpe_regs *g = opaque;
 604     switch (addr) {
 605         case PROC_BASE:
 606             g->up = val;
 607             break;
 608         case PROC_BASE + 1:
 609             g->down = val;
 610             break;
 611
 612         case GPE_BASE:
 613             g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
 614             break;
 615         case GPE_BASE + 1:
 616             g->sts = (g->sts & 0xFFFF) | (val << 8);
 617             break;
 618         case GPE_BASE + 2:
 619             g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
 620             break;
 621         case GPE_BASE + 3:
 622             g->en = (g->en & 0xFFFF) | (val << 8);
 623             break;
 624         default:
 625             break;
 626    }
 627
 628 #if defined(DEBUG)
 629     printf("gpe write %x <== %d\n", addr, val);
 630 #endif
 631 }
 632
 633 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 634 {
 635     uint32_t val = 0;
 636     struct pci_status *g = opaque;
 637     switch (addr) {
 638         case PCI_BASE:
 639             val = g->up;
 640             break;
 641         case PCI_BASE + 4:
 642             val = g->down;
 643             break;
 644         default:
 645             break;
 646     }
 647
 648 #if defined(DEBUG)
 649     printf("pcihotplug read %x == %x\n", addr, val);
 650 #endif
 651     return val;
 652 }
 653
 654 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 655 {
 656     struct pci_status *g = opaque;
 657     switch (addr) {
 658         case PCI_BASE:
 659             g->up = val;
 660             break;
 661         case PCI_BASE + 4:
 662             g->down = val;
 663             break;
 664    }
 665
 666 #if defined(DEBUG)
 667     printf("pcihotplug write %x <== %d\n", addr, val);
 668 #endif
 669 }
 670
 671 static uint32_t pciej_read(void *opaque, uint32_t addr)
 672 {
 673 #if defined(DEBUG)
 674     printf("pciej read %x\n", addr);
 675 #endif
 676     return 0;
 677 }
 678
 679 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 680 {
 681     int slot = ffs(val) - 1;
 682
 683     device_hot_remove_success(0, slot);
 684
 685 #if defined(DEBUG)
 686     printf("pciej write %x <== %d\n", addr, val);
 687 #endif
 688 }
 689
 690 static const char *model;
 691
 692 void qemu_system_hot_add_init(const char *cpu_model)
 693 {
 694     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 695     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 696
 697     register_ioport_write(PROC_BASE, 4, 1, gpe_writeb, &gpe);
 698     register_ioport_read(PROC_BASE, 4, 1,  gpe_readb, &gpe);
 699
 700     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 701     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 702
 703     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
 704     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, NULL);
 705
 706     model = cpu_model;
 707 }
 708
 709 static void enable_processor(struct gpe_regs *g, int cpu)
 710 {
 711     g->sts |= 1;
 712     g->en |= 1;
 713     g->up |= (1 << cpu);
 714 }
 715
 716 static void disable_processor(struct gpe_regs *g, int cpu)
 717 {
 718     g->sts |= 1;
 719     g->en |= 1;
 720     g->down |= (1 << cpu);
 721 }
 722
 723 #if defined(TARGET_I386) || defined(TARGET_X86_64)
 724 void qemu_system_cpu_hot_add(int cpu, int state)
 725 {
 726     CPUState *env;
 727
 728     if ((state) && (!qemu_kvm_cpu_env(cpu))) {
 729         env = pc_new_cpu(cpu, model, 1);
 730         if (!env) {
 731             fprintf(stderr, "cpu %d creation failed\n", cpu);
 732             return;
 733         }
 734 #ifdef USE_KVM
 735         kvm_init_new_ap(cpu, env);
 736 #endif
 737     }
 738
 739     qemu_set_irq(pm_state->irq, 1);
 740     gpe.up = 0;
 741     gpe.down = 0;
 742     if (state)
 743         enable_processor(&gpe, cpu);
 744     else
 745         disable_processor(&gpe, cpu);
 746     qemu_set_irq(pm_state->irq, 0);
 747 }
 748 #endif
 749
 750 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 751 {
 752     g->sts |= 2;
 753     g->en |= 2;
 754     p->up |= (1 << slot);
 755 }
 756
 757 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 758 {
 759     g->sts |= 2;
 760     g->en |= 2;
 761     p->down |= (1 << slot);
 762 }
 763
 764 void qemu_system_device_hot_add(int pcibus, int slot, int state)
 765 {
 766     qemu_set_irq(pm_state->irq, 1);
 767     pci0_status.up = 0;
 768     pci0_status.down = 0;
 769     if (state)
 770         enable_device(&pci0_status, &gpe, slot);
 771     else
 772         disable_device(&pci0_status, &gpe, slot);
 773     qemu_set_irq(pm_state->irq, 0);
 774 }