hw/lsi53c895a.c

   1 /*
   2  * QEMU LSI53C895A SCSI Host Bus Adapter emulation
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 /* ??? Need to check if the {read,write}[wl] routines work properly on
  11    big-endian targets.  */
  12
  13 #include "hw.h"
  14 #include "pci.h"
  15 #include "scsi-disk.h"
  16 #include "block_int.h"
  17
  18 //#define DEBUG_LSI
  19 //#define DEBUG_LSI_REG
  20
  21 #ifdef DEBUG_LSI
  22 #define DPRINTF(fmt, args...) \
  23 do { printf("lsi_scsi: " fmt , ##args); } while (0)
  24 #define BADF(fmt, args...) \
  25 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
  26 #else
  27 #define DPRINTF(fmt, args...) do {} while(0)
  28 #define BADF(fmt, args...) \
  29 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
  30 #endif
  31
  32 #define LSI_SCNTL0_TRG    0x01
  33 #define LSI_SCNTL0_AAP    0x02
  34 #define LSI_SCNTL0_EPC    0x08
  35 #define LSI_SCNTL0_WATN   0x10
  36 #define LSI_SCNTL0_START  0x20
  37
  38 #define LSI_SCNTL1_SST    0x01
  39 #define LSI_SCNTL1_IARB   0x02
  40 #define LSI_SCNTL1_AESP   0x04
  41 #define LSI_SCNTL1_RST    0x08
  42 #define LSI_SCNTL1_CON    0x10
  43 #define LSI_SCNTL1_DHP    0x20
  44 #define LSI_SCNTL1_ADB    0x40
  45 #define LSI_SCNTL1_EXC    0x80
  46
  47 #define LSI_SCNTL2_WSR    0x01
  48 #define LSI_SCNTL2_VUE0   0x02
  49 #define LSI_SCNTL2_VUE1   0x04
  50 #define LSI_SCNTL2_WSS    0x08
  51 #define LSI_SCNTL2_SLPHBEN 0x10
  52 #define LSI_SCNTL2_SLPMD  0x20
  53 #define LSI_SCNTL2_CHM    0x40
  54 #define LSI_SCNTL2_SDU    0x80
  55
  56 #define LSI_ISTAT0_DIP    0x01
  57 #define LSI_ISTAT0_SIP    0x02
  58 #define LSI_ISTAT0_INTF   0x04
  59 #define LSI_ISTAT0_CON    0x08
  60 #define LSI_ISTAT0_SEM    0x10
  61 #define LSI_ISTAT0_SIGP   0x20
  62 #define LSI_ISTAT0_SRST   0x40
  63 #define LSI_ISTAT0_ABRT   0x80
  64
  65 #define LSI_ISTAT1_SI     0x01
  66 #define LSI_ISTAT1_SRUN   0x02
  67 #define LSI_ISTAT1_FLSH   0x04
  68
  69 #define LSI_SSTAT0_SDP0   0x01
  70 #define LSI_SSTAT0_RST    0x02
  71 #define LSI_SSTAT0_WOA    0x04
  72 #define LSI_SSTAT0_LOA    0x08
  73 #define LSI_SSTAT0_AIP    0x10
  74 #define LSI_SSTAT0_OLF    0x20
  75 #define LSI_SSTAT0_ORF    0x40
  76 #define LSI_SSTAT0_ILF    0x80
  77
  78 #define LSI_SIST0_PAR     0x01
  79 #define LSI_SIST0_RST     0x02
  80 #define LSI_SIST0_UDC     0x04
  81 #define LSI_SIST0_SGE     0x08
  82 #define LSI_SIST0_RSL     0x10
  83 #define LSI_SIST0_SEL     0x20
  84 #define LSI_SIST0_CMP     0x40
  85 #define LSI_SIST0_MA      0x80
  86
  87 #define LSI_SIST1_HTH     0x01
  88 #define LSI_SIST1_GEN     0x02
  89 #define LSI_SIST1_STO     0x04
  90 #define LSI_SIST1_SBMC    0x10
  91
  92 #define LSI_SOCL_IO       0x01
  93 #define LSI_SOCL_CD       0x02
  94 #define LSI_SOCL_MSG      0x04
  95 #define LSI_SOCL_ATN      0x08
  96 #define LSI_SOCL_SEL      0x10
  97 #define LSI_SOCL_BSY      0x20
  98 #define LSI_SOCL_ACK      0x40
  99 #define LSI_SOCL_REQ      0x80
 100
 101 #define LSI_DSTAT_IID     0x01
 102 #define LSI_DSTAT_SIR     0x04
 103 #define LSI_DSTAT_SSI     0x08
 104 #define LSI_DSTAT_ABRT    0x10
 105 #define LSI_DSTAT_BF      0x20
 106 #define LSI_DSTAT_MDPE    0x40
 107 #define LSI_DSTAT_DFE     0x80
 108
 109 #define LSI_DCNTL_COM     0x01
 110 #define LSI_DCNTL_IRQD    0x02
 111 #define LSI_DCNTL_STD     0x04
 112 #define LSI_DCNTL_IRQM    0x08
 113 #define LSI_DCNTL_SSM     0x10
 114 #define LSI_DCNTL_PFEN    0x20
 115 #define LSI_DCNTL_PFF     0x40
 116 #define LSI_DCNTL_CLSE    0x80
 117
 118 #define LSI_DMODE_MAN     0x01
 119 #define LSI_DMODE_BOF     0x02
 120 #define LSI_DMODE_ERMP    0x04
 121 #define LSI_DMODE_ERL     0x08
 122 #define LSI_DMODE_DIOM    0x10
 123 #define LSI_DMODE_SIOM    0x20
 124
 125 #define LSI_CTEST2_DACK   0x01
 126 #define LSI_CTEST2_DREQ   0x02
 127 #define LSI_CTEST2_TEOP   0x04
 128 #define LSI_CTEST2_PCICIE 0x08
 129 #define LSI_CTEST2_CM     0x10
 130 #define LSI_CTEST2_CIO    0x20
 131 #define LSI_CTEST2_SIGP   0x40
 132 #define LSI_CTEST2_DDIR   0x80
 133
 134 #define LSI_CTEST5_BL2    0x04
 135 #define LSI_CTEST5_DDIR   0x08
 136 #define LSI_CTEST5_MASR   0x10
 137 #define LSI_CTEST5_DFSN   0x20
 138 #define LSI_CTEST5_BBCK   0x40
 139 #define LSI_CTEST5_ADCK   0x80
 140
 141 #define LSI_CCNTL0_DILS   0x01
 142 #define LSI_CCNTL0_DISFC  0x10
 143 #define LSI_CCNTL0_ENNDJ  0x20
 144 #define LSI_CCNTL0_PMJCTL 0x40
 145 #define LSI_CCNTL0_ENPMJ  0x80
 146
 147 #define PHASE_DO          0
 148 #define PHASE_DI          1
 149 #define PHASE_CMD         2
 150 #define PHASE_ST          3
 151 #define PHASE_MO          6
 152 #define PHASE_MI          7
 153 #define PHASE_MASK        7
 154
 155 /* Maximum length of MSG IN data.  */
 156 #define LSI_MAX_MSGIN_LEN 8
 157
 158 /* Flag set if this is a tagged command.  */
 159 #define LSI_TAG_VALID     (1 << 16)
 160
 161 typedef struct {
 162     uint32_t tag;
 163     uint32_t pending;
 164     int out;
 165 } lsi_queue;
 166
 167 typedef struct {
 168     PCIDevice pci_dev;
 169     int mmio_io_addr;
 170     int ram_io_addr;
 171     uint32_t script_ram_base;
 172
 173     int carry; /* ??? Should this be an a visible register somewhere?  */
 174     int sense;
 175     /* Action to take at the end of a MSG IN phase.
 176        0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN.  */
 177     int msg_action;
 178     int msg_len;
 179     uint8_t msg[LSI_MAX_MSGIN_LEN];
 180     /* 0 if SCRIPTS are running or stopped.
 181      * 1 if a Wait Reselect instruction has been issued.
 182      * 2 if processing DMA from lsi_execute_script.
 183      * 3 if a DMA operation is in progress.  */
 184     int waiting;
 185     SCSIDevice *scsi_dev[LSI_MAX_DEVS];
 186     SCSIDevice *current_dev;
 187     int current_lun;
 188     /* The tag is a combination of the device ID and the SCSI tag.  */
 189     uint32_t current_tag;
 190     uint32_t current_dma_len;
 191     int command_complete;
 192     uint8_t *dma_buf;
 193     lsi_queue *queue;
 194     int queue_len;
 195     int active_commands;
 196
 197     uint32_t dsa;
 198     uint32_t temp;
 199     uint32_t dnad;
 200     uint32_t dbc;
 201     uint8_t istat0;
 202     uint8_t istat1;
 203     uint8_t dcmd;
 204     uint8_t dstat;
 205     uint8_t dien;
 206     uint8_t sist0;
 207     uint8_t sist1;
 208     uint8_t sien0;
 209     uint8_t sien1;
 210     uint8_t mbox0;
 211     uint8_t mbox1;
 212     uint8_t dfifo;
 213     uint8_t ctest3;
 214     uint8_t ctest4;
 215     uint8_t ctest5;
 216     uint8_t ccntl0;
 217     uint8_t ccntl1;
 218     uint32_t dsp;
 219     uint32_t dsps;
 220     uint8_t dmode;
 221     uint8_t dcntl;
 222     uint8_t scntl0;
 223     uint8_t scntl1;
 224     uint8_t scntl2;
 225     uint8_t scntl3;
 226     uint8_t sstat0;
 227     uint8_t sstat1;
 228     uint8_t scid;
 229     uint8_t sxfer;
 230     uint8_t socl;
 231     uint8_t sdid;
 232     uint8_t ssid;
 233     uint8_t sfbr;
 234     uint8_t stest1;
 235     uint8_t stest2;
 236     uint8_t stest3;
 237     uint8_t sidl;
 238     uint8_t stime0;
 239     uint8_t respid0;
 240     uint8_t respid1;
 241     uint32_t mmrs;
 242     uint32_t mmws;
 243     uint32_t sfs;
 244     uint32_t drs;
 245     uint32_t sbms;
 246     uint32_t dmbs;
 247     uint32_t dnad64;
 248     uint32_t pmjad1;
 249     uint32_t pmjad2;
 250     uint32_t rbc;
 251     uint32_t ua;
 252     uint32_t ia;
 253     uint32_t sbc;
 254     uint32_t csbc;
 255     uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
 256
 257     /* Script ram is stored as 32-bit words in host byteorder.  */
 258     uint32_t script_ram[2048];
 259 } LSIState;
 260
 261 static void lsi_soft_reset(LSIState *s)
 262 {
 263     DPRINTF("Reset\n");
 264     s->carry = 0;
 265
 266     s->waiting = 0;
 267     s->dsa = 0;
 268     s->dnad = 0;
 269     s->dbc = 0;
 270     s->temp = 0;
 271     memset(s->scratch, 0, sizeof(s->scratch));
 272     s->istat0 = 0;
 273     s->istat1 = 0;
 274     s->dcmd = 0;
 275     s->dstat = 0;
 276     s->dien = 0;
 277     s->sist0 = 0;
 278     s->sist1 = 0;
 279     s->sien0 = 0;
 280     s->sien1 = 0;
 281     s->mbox0 = 0;
 282     s->mbox1 = 0;
 283     s->dfifo = 0;
 284     s->ctest3 = 0;
 285     s->ctest4 = 0;
 286     s->ctest5 = 0;
 287     s->ccntl0 = 0;
 288     s->ccntl1 = 0;
 289     s->dsp = 0;
 290     s->dsps = 0;
 291     s->dmode = 0;
 292     s->dcntl = 0;
 293     s->scntl0 = 0xc0;
 294     s->scntl1 = 0;
 295     s->scntl2 = 0;
 296     s->scntl3 = 0;
 297     s->sstat0 = 0;
 298     s->sstat1 = 0;
 299     s->scid = 7;
 300     s->sxfer = 0;
 301     s->socl = 0;
 302     s->stest1 = 0;
 303     s->stest2 = 0;
 304     s->stest3 = 0;
 305     s->sidl = 0;
 306     s->stime0 = 0;
 307     s->respid0 = 0x80;
 308     s->respid1 = 0;
 309     s->mmrs = 0;
 310     s->mmws = 0;
 311     s->sfs = 0;
 312     s->drs = 0;
 313     s->sbms = 0;
 314     s->dmbs = 0;
 315     s->dnad64 = 0;
 316     s->pmjad1 = 0;
 317     s->pmjad2 = 0;
 318     s->rbc = 0;
 319     s->ua = 0;
 320     s->ia = 0;
 321     s->sbc = 0;
 322     s->csbc = 0;
 323 }
 324
 325 static uint8_t lsi_reg_readb(LSIState *s, int offset);
 326 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
 327 static void lsi_execute_script(LSIState *s);
 328
 329 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
 330 {
 331     uint32_t buf;
 332
 333     /* Optimize reading from SCRIPTS RAM.  */
 334     if ((addr & 0xffffe000) == s->script_ram_base) {
 335         return s->script_ram[(addr & 0x1fff) >> 2];
 336     }
 337     cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
 338     return cpu_to_le32(buf);
 339 }
 340
 341 static void lsi_stop_script(LSIState *s)
 342 {
 343     s->istat1 &= ~LSI_ISTAT1_SRUN;
 344 }
 345
 346 static void lsi_update_irq(LSIState *s)
 347 {
 348     int level;
 349     static int last_level;
 350
 351     /* It's unclear whether the DIP/SIP bits should be cleared when the
 352        Interrupt Status Registers are cleared or when istat0 is read.
 353        We currently do the formwer, which seems to work.  */
 354     level = 0;
 355     if (s->dstat) {
 356         if (s->dstat & s->dien)
 357             level = 1;
 358         s->istat0 |= LSI_ISTAT0_DIP;
 359     } else {
 360         s->istat0 &= ~LSI_ISTAT0_DIP;
 361     }
 362
 363     if (s->sist0 || s->sist1) {
 364         if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
 365             level = 1;
 366         s->istat0 |= LSI_ISTAT0_SIP;
 367     } else {
 368         s->istat0 &= ~LSI_ISTAT0_SIP;
 369     }
 370     if (s->istat0 & LSI_ISTAT0_INTF)
 371         level = 1;
 372
 373     if (level != last_level) {
 374         DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
 375                 level, s->dstat, s->sist1, s->sist0);
 376         last_level = level;
 377     }
 378     qemu_set_irq(s->pci_dev.irq[0], level);
 379 }
 380
 381 /* Stop SCRIPTS execution and raise a SCSI interrupt.  */
 382 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
 383 {
 384     uint32_t mask0;
 385     uint32_t mask1;
 386
 387     DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
 388             stat1, stat0, s->sist1, s->sist0);
 389     s->sist0 |= stat0;
 390     s->sist1 |= stat1;
 391     /* Stop processor on fatal or unmasked interrupt.  As a special hack
 392        we don't stop processing when raising STO.  Instead continue
 393        execution and stop at the next insn that accesses the SCSI bus.  */
 394     mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
 395     mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
 396     mask1 &= ~LSI_SIST1_STO;
 397     if (s->sist0 & mask0 || s->sist1 & mask1) {
 398         lsi_stop_script(s);
 399     }
 400     lsi_update_irq(s);
 401 }
 402
 403 /* Stop SCRIPTS execution and raise a DMA interrupt.  */
 404 static void lsi_script_dma_interrupt(LSIState *s, int stat)
 405 {
 406     DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
 407     s->dstat |= stat;
 408     lsi_update_irq(s);
 409     lsi_stop_script(s);
 410 }
 411
 412 static inline void lsi_set_phase(LSIState *s, int phase)
 413 {
 414     s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
 415 }
 416
 417 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
 418 {
 419     /* Trigger a phase mismatch.  */
 420     if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
 421         if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
 422             s->dsp = s->pmjad1;
 423         } else {
 424             s->dsp = s->pmjad2;
 425         }
 426         DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
 427     } else {
 428         DPRINTF("Phase mismatch interrupt\n");
 429         lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 430         lsi_stop_script(s);
 431     }
 432     lsi_set_phase(s, new_phase);
 433 }
 434
 435
 436 /* Resume SCRIPTS execution after a DMA operation.  */
 437 static void lsi_resume_script(LSIState *s)
 438 {
 439     if (s->waiting != 2) {
 440         s->waiting = 0;
 441         lsi_execute_script(s);
 442     } else {
 443         s->waiting = 0;
 444     }
 445 }
 446
 447 /* Initiate a SCSI layer data transfer.  */
 448 static void lsi_do_dma(LSIState *s, int out)
 449 {
 450     uint32_t count;
 451     uint32_t addr;
 452
 453     if (!s->current_dma_len) {
 454         /* Wait until data is available.  */
 455         DPRINTF("DMA no data available\n");
 456         return;
 457     }
 458
 459     count = s->dbc;
 460     if (count > s->current_dma_len)
 461         count = s->current_dma_len;
 462     DPRINTF("DMA addr=0x%08x len=%d\n", s->dnad, count);
 463
 464     addr = s->dnad;
 465     s->csbc += count;
 466     s->dnad += count;
 467     s->dbc -= count;
 468
 469     if (s->dma_buf == NULL) {
 470         s->dma_buf = s->current_dev->get_buf(s->current_dev,
 471                                              s->current_tag);
 472     }
 473
 474     /* ??? Set SFBR to first data byte.  */
 475     if (out) {
 476         cpu_physical_memory_read(addr, s->dma_buf, count);
 477     } else {
 478         cpu_physical_memory_write(addr, s->dma_buf, count);
 479     }
 480     s->current_dma_len -= count;
 481     if (s->current_dma_len == 0) {
 482         s->dma_buf = NULL;
 483         if (out) {
 484             /* Write the data.  */
 485             s->current_dev->write_data(s->current_dev, s->current_tag);
 486         } else {
 487             /* Request any remaining data.  */
 488             s->current_dev->read_data(s->current_dev, s->current_tag);
 489         }
 490     } else {
 491         s->dma_buf += count;
 492         lsi_resume_script(s);
 493     }
 494 }
 495
 496
 497 /* Add a command to the queue.  */
 498 static void lsi_queue_command(LSIState *s)
 499 {
 500     lsi_queue *p;
 501
 502     DPRINTF("Queueing tag=0x%x\n", s->current_tag);
 503     if (s->queue_len == s->active_commands) {
 504         s->queue_len++;
 505         s->queue = qemu_realloc(s->queue, s->queue_len * sizeof(lsi_queue));
 506     }
 507     p = &s->queue[s->active_commands++];
 508     p->tag = s->current_tag;
 509     p->pending = 0;
 510     p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 511 }
 512
 513 /* Queue a byte for a MSG IN phase.  */
 514 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
 515 {
 516     if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
 517         BADF("MSG IN data too long\n");
 518     } else {
 519         DPRINTF("MSG IN 0x%02x\n", data);
 520         s->msg[s->msg_len++] = data;
 521     }
 522 }
 523
 524 /* Perform reselection to continue a command.  */
 525 static void lsi_reselect(LSIState *s, uint32_t tag)
 526 {
 527     lsi_queue *p;
 528     int n;
 529     int id;
 530
 531     p = NULL;
 532     for (n = 0; n < s->active_commands; n++) {
 533         p = &s->queue[n];
 534         if (p->tag == tag)
 535             break;
 536     }
 537     if (n == s->active_commands) {
 538         BADF("Reselected non-existant command tag=0x%x\n", tag);
 539         return;
 540     }
 541     id = (tag >> 8) & 0xf;
 542     s->ssid = id | 0x80;
 543     DPRINTF("Reselected target %d\n", id);
 544     s->current_dev = s->scsi_dev[id];
 545     s->current_tag = tag;
 546     s->scntl1 |= LSI_SCNTL1_CON;
 547     lsi_set_phase(s, PHASE_MI);
 548     s->msg_action = p->out ? 2 : 3;
 549     s->current_dma_len = p->pending;
 550     s->dma_buf = NULL;
 551     lsi_add_msg_byte(s, 0x80);
 552     if (s->current_tag & LSI_TAG_VALID) {
 553         lsi_add_msg_byte(s, 0x20);
 554         lsi_add_msg_byte(s, tag & 0xff);
 555     }
 556
 557     s->active_commands--;
 558     if (n != s->active_commands) {
 559         s->queue[n] = s->queue[s->active_commands];
 560     }
 561 }
 562
 563 /* Record that data is available for a queued command.  Returns zero if
 564    the device was reselected, nonzero if the IO is deferred.  */
 565 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
 566 {
 567     lsi_queue *p;
 568     int i;
 569     for (i = 0; i < s->active_commands; i++) {
 570         p = &s->queue[i];
 571         if (p->tag == tag) {
 572             if (p->pending) {
 573                 BADF("Multiple IO pending for tag %d\n", tag);
 574             }
 575             p->pending = arg;
 576             if (s->waiting == 1) {
 577                 /* Reselect device.  */
 578                 lsi_reselect(s, tag);
 579                 return 0;
 580             } else {
 581                DPRINTF("Queueing IO tag=0x%x\n", tag);
 582                 p->pending = arg;
 583                 return 1;
 584             }
 585         }
 586     }
 587     BADF("IO with unknown tag %d\n", tag);
 588     return 1;
 589 }
 590
 591 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 592 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
 593                                  uint32_t arg)
 594 {
 595     LSIState *s = (LSIState *)opaque;
 596     int out;
 597
 598     out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 599     if (reason == SCSI_REASON_DONE) {
 600         DPRINTF("Command complete sense=%d\n", (int)arg);
 601         s->sense = arg;
 602         s->command_complete = 2;
 603         if (s->waiting && s->dbc != 0) {
 604             /* Raise phase mismatch for short transfers.  */
 605             lsi_bad_phase(s, out, PHASE_ST);
 606         } else {
 607             lsi_set_phase(s, PHASE_ST);
 608         }
 609         lsi_resume_script(s);
 610         return;
 611     }
 612
 613     if (s->waiting == 1 || tag != s->current_tag) {
 614         if (lsi_queue_tag(s, tag, arg))
 615             return;
 616     }
 617     DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
 618     s->current_dma_len = arg;
 619     s->command_complete = 1;
 620     if (!s->waiting)
 621         return;
 622     if (s->waiting == 1 || s->dbc == 0) {
 623         lsi_resume_script(s);
 624     } else {
 625         lsi_do_dma(s, out);
 626     }
 627 }
 628
 629 static void lsi_do_command(LSIState *s)
 630 {
 631     uint8_t buf[16];
 632     int n;
 633
 634     DPRINTF("Send command len=%d\n", s->dbc);
 635     if (s->dbc > 16)
 636         s->dbc = 16;
 637     cpu_physical_memory_read(s->dnad, buf, s->dbc);
 638     s->sfbr = buf[0];
 639     s->command_complete = 0;
 640     n = s->current_dev->send_command(s->current_dev, s->current_tag, buf,
 641                                      s->current_lun);
 642     if (n > 0) {
 643         lsi_set_phase(s, PHASE_DI);
 644         s->current_dev->read_data(s->current_dev, s->current_tag);
 645     } else if (n < 0) {
 646         lsi_set_phase(s, PHASE_DO);
 647         s->current_dev->write_data(s->current_dev, s->current_tag);
 648     }
 649
 650     if (!s->command_complete) {
 651         if (n) {
 652             /* Command did not complete immediately so disconnect.  */
 653             lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
 654             lsi_add_msg_byte(s, 4); /* DISCONNECT */
 655             /* wait data */
 656             lsi_set_phase(s, PHASE_MI);
 657             s->msg_action = 1;
 658             lsi_queue_command(s);
 659         } else {
 660             /* wait command complete */
 661             lsi_set_phase(s, PHASE_DI);
 662         }
 663     }
 664 }
 665
 666 static void lsi_do_status(LSIState *s)
 667 {
 668     uint8_t sense;
 669     DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
 670     if (s->dbc != 1)
 671         BADF("Bad Status move\n");
 672     s->dbc = 1;
 673     sense = s->sense;
 674     s->sfbr = sense;
 675     cpu_physical_memory_write(s->dnad, &sense, 1);
 676     lsi_set_phase(s, PHASE_MI);
 677     s->msg_action = 1;
 678     lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
 679 }
 680
 681 static void lsi_disconnect(LSIState *s)
 682 {
 683     s->scntl1 &= ~LSI_SCNTL1_CON;
 684     s->sstat1 &= ~PHASE_MASK;
 685 }
 686
 687 static void lsi_do_msgin(LSIState *s)
 688 {
 689     int len;
 690     DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
 691     s->sfbr = s->msg[0];
 692     len = s->msg_len;
 693     if (len > s->dbc)
 694         len = s->dbc;
 695     cpu_physical_memory_write(s->dnad, s->msg, len);
 696     /* Linux drivers rely on the last byte being in the SIDL.  */
 697     s->sidl = s->msg[len - 1];
 698     s->msg_len -= len;
 699     if (s->msg_len) {
 700         memmove(s->msg, s->msg + len, s->msg_len);
 701     } else {
 702         /* ??? Check if ATN (not yet implemented) is asserted and maybe
 703            switch to PHASE_MO.  */
 704         switch (s->msg_action) {
 705         case 0:
 706             lsi_set_phase(s, PHASE_CMD);
 707             break;
 708         case 1:
 709             lsi_disconnect(s);
 710             break;
 711         case 2:
 712             lsi_set_phase(s, PHASE_DO);
 713             break;
 714         case 3:
 715             lsi_set_phase(s, PHASE_DI);
 716             break;
 717         default:
 718             abort();
 719         }
 720     }
 721 }
 722
 723 /* Read the next byte during a MSGOUT phase.  */
 724 static uint8_t lsi_get_msgbyte(LSIState *s)
 725 {
 726     uint8_t data;
 727     cpu_physical_memory_read(s->dnad, &data, 1);
 728     s->dnad++;
 729     s->dbc--;
 730     return data;
 731 }
 732
 733 static void lsi_do_msgout(LSIState *s)
 734 {
 735     uint8_t msg;
 736     int len;
 737
 738     DPRINTF("MSG out len=%d\n", s->dbc);
 739     while (s->dbc) {
 740         msg = lsi_get_msgbyte(s);
 741         s->sfbr = msg;
 742
 743         switch (msg) {
 744         case 0x00:
 745             DPRINTF("MSG: Disconnect\n");
 746             lsi_disconnect(s);
 747             break;
 748         case 0x08:
 749             DPRINTF("MSG: No Operation\n");
 750             lsi_set_phase(s, PHASE_CMD);
 751             break;
 752         case 0x01:
 753             len = lsi_get_msgbyte(s);
 754             msg = lsi_get_msgbyte(s);
 755             DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
 756             switch (msg) {
 757             case 1:
 758                 DPRINTF("SDTR (ignored)\n");
 759                 s->dbc -= 2;
 760                 break;
 761             case 3:
 762                 DPRINTF("WDTR (ignored)\n");
 763                 s->dbc -= 1;
 764                 break;
 765             default:
 766                 goto bad;
 767             }
 768             break;
 769         case 0x20: /* SIMPLE queue */
 770             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 771             DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
 772             break;
 773         case 0x21: /* HEAD of queue */
 774             BADF("HEAD queue not implemented\n");
 775             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 776             break;
 777         case 0x22: /* ORDERED queue */
 778             BADF("ORDERED queue not implemented\n");
 779             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 780             break;
 781         default:
 782             if ((msg & 0x80) == 0) {
 783                 goto bad;
 784             }
 785             s->current_lun = msg & 7;
 786             DPRINTF("Select LUN %d\n", s->current_lun);
 787             lsi_set_phase(s, PHASE_CMD);
 788             break;
 789         }
 790     }
 791     return;
 792 bad:
 793     BADF("Unimplemented message 0x%02x\n", msg);
 794     lsi_set_phase(s, PHASE_MI);
 795     lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
 796     s->msg_action = 0;
 797 }
 798
 799 /* Sign extend a 24-bit value.  */
 800 static inline int32_t sxt24(int32_t n)
 801 {
 802     return (n << 8) >> 8;
 803 }
 804
 805 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
 806 {
 807     int n;
 808     uint8_t buf[TARGET_PAGE_SIZE];
 809
 810     DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
 811     while (count) {
 812         n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
 813         cpu_physical_memory_read(src, buf, n);
 814         cpu_physical_memory_write(dest, buf, n);
 815         src += n;
 816         dest += n;
 817         count -= n;
 818     }
 819 }
 820
 821 static void lsi_wait_reselect(LSIState *s)
 822 {
 823     int i;
 824     DPRINTF("Wait Reselect\n");
 825     if (s->current_dma_len)
 826         BADF("Reselect with pending DMA\n");
 827     for (i = 0; i < s->active_commands; i++) {
 828         if (s->queue[i].pending) {
 829             lsi_reselect(s, s->queue[i].tag);
 830             break;
 831         }
 832     }
 833     if (s->current_dma_len == 0) {
 834         s->waiting = 1;
 835     }
 836 }
 837
 838 static void lsi_execute_script(LSIState *s)
 839 {
 840     uint32_t insn;
 841     uint32_t addr;
 842     int opcode;
 843
 844     s->istat1 |= LSI_ISTAT1_SRUN;
 845 again:
 846     insn = read_dword(s, s->dsp);
 847     addr = read_dword(s, s->dsp + 4);
 848     DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
 849     s->dsps = addr;
 850     s->dcmd = insn >> 24;
 851     s->dsp += 8;
 852     switch (insn >> 30) {
 853     case 0: /* Block move.  */
 854         if (s->sist1 & LSI_SIST1_STO) {
 855             DPRINTF("Delayed select timeout\n");
 856             lsi_stop_script(s);
 857             break;
 858         }
 859         s->dbc = insn & 0xffffff;
 860         s->rbc = s->dbc;
 861         if (insn & (1 << 29)) {
 862             /* Indirect addressing.  */
 863             addr = read_dword(s, addr);
 864         } else if (insn & (1 << 28)) {
 865             uint32_t buf[2];
 866             int32_t offset;
 867             /* Table indirect addressing.  */
 868             offset = sxt24(addr);
 869             cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
 870             s->dbc = cpu_to_le32(buf[0]);
 871             s->rbc = s->dbc;
 872             addr = cpu_to_le32(buf[1]);
 873         }
 874         if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
 875             DPRINTF("Wrong phase got %d expected %d\n",
 876                     s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
 877             lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 878             break;
 879         }
 880         s->dnad = addr;
 881         /* ??? Set ESA.  */
 882         s->ia = s->dsp - 8;
 883         switch (s->sstat1 & 0x7) {
 884         case PHASE_DO:
 885             s->waiting = 2;
 886             lsi_do_dma(s, 1);
 887             if (s->waiting)
 888                 s->waiting = 3;
 889             break;
 890         case PHASE_DI:
 891             s->waiting = 2;
 892             lsi_do_dma(s, 0);
 893             if (s->waiting)
 894                 s->waiting = 3;
 895             break;
 896         case PHASE_CMD:
 897             lsi_do_command(s);
 898             break;
 899         case PHASE_ST:
 900             lsi_do_status(s);
 901             break;
 902         case PHASE_MO:
 903             lsi_do_msgout(s);
 904             break;
 905         case PHASE_MI:
 906             lsi_do_msgin(s);
 907             break;
 908         default:
 909             BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
 910             exit(1);
 911         }
 912         s->dfifo = s->dbc & 0xff;
 913         s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
 914         s->sbc = s->dbc;
 915         s->rbc -= s->dbc;
 916         s->ua = addr + s->dbc;
 917         break;
 918
 919     case 1: /* IO or Read/Write instruction.  */
 920         opcode = (insn >> 27) & 7;
 921         if (opcode < 5) {
 922             uint32_t id;
 923
 924             if (insn & (1 << 25)) {
 925                 id = read_dword(s, s->dsa + sxt24(insn));
 926             } else {
 927                 id = addr;
 928             }
 929             id = (id >> 16) & 0xf;
 930             if (insn & (1 << 26)) {
 931                 addr = s->dsp + sxt24(addr);
 932             }
 933             s->dnad = addr;
 934             switch (opcode) {
 935             case 0: /* Select */
 936                 s->sdid = id;
 937                 if (s->current_dma_len && (s->ssid & 0xf) == id) {
 938                     DPRINTF("Already reselected by target %d\n", id);
 939                     break;
 940                 }
 941                 s->sstat0 |= LSI_SSTAT0_WOA;
 942                 s->scntl1 &= ~LSI_SCNTL1_IARB;
 943                 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
 944                     DPRINTF("Selected absent target %d\n", id);
 945                     lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
 946                     lsi_disconnect(s);
 947                     break;
 948                 }
 949                 DPRINTF("Selected target %d%s\n",
 950                         id, insn & (1 << 3) ? " ATN" : "");
 951                 /* ??? Linux drivers compain when this is set.  Maybe
 952                    it only applies in low-level mode (unimplemented).
 953                 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
 954                 s->current_dev = s->scsi_dev[id];
 955                 s->current_tag = id << 8;
 956                 s->scntl1 |= LSI_SCNTL1_CON;
 957                 if (insn & (1 << 3)) {
 958                     s->socl |= LSI_SOCL_ATN;
 959                 }
 960                 lsi_set_phase(s, PHASE_MO);
 961                 break;
 962             case 1: /* Disconnect */
 963                 DPRINTF("Wait Disconect\n");
 964                 s->scntl1 &= ~LSI_SCNTL1_CON;
 965                 break;
 966             case 2: /* Wait Reselect */
 967                 lsi_wait_reselect(s);
 968                 break;
 969             case 3: /* Set */
 970                 DPRINTF("Set%s%s%s%s\n",
 971                         insn & (1 << 3) ? " ATN" : "",
 972                         insn & (1 << 6) ? " ACK" : "",
 973                         insn & (1 << 9) ? " TM" : "",
 974                         insn & (1 << 10) ? " CC" : "");
 975                 if (insn & (1 << 3)) {
 976                     s->socl |= LSI_SOCL_ATN;
 977                     lsi_set_phase(s, PHASE_MO);
 978                 }
 979                 if (insn & (1 << 9)) {
 980                     BADF("Target mode not implemented\n");
 981                     exit(1);
 982                 }
 983                 if (insn & (1 << 10))
 984                     s->carry = 1;
 985                 break;
 986             case 4: /* Clear */
 987                 DPRINTF("Clear%s%s%s%s\n",
 988                         insn & (1 << 3) ? " ATN" : "",
 989                         insn & (1 << 6) ? " ACK" : "",
 990                         insn & (1 << 9) ? " TM" : "",
 991                         insn & (1 << 10) ? " CC" : "");
 992                 if (insn & (1 << 3)) {
 993                     s->socl &= ~LSI_SOCL_ATN;
 994                 }
 995                 if (insn & (1 << 10))
 996                     s->carry = 0;
 997                 break;
 998             }
 999         } else {
1000             uint8_t op0;
1001             uint8_t op1;
1002             uint8_t data8;
1003             int reg;
1004             int operator;
1005 #ifdef DEBUG_LSI
1006             static const char *opcode_names[3] =
1007                 {"Write", "Read", "Read-Modify-Write"};
1008             static const char *operator_names[8] =
1009                 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1010 #endif
1011
1012             reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1013             data8 = (insn >> 8) & 0xff;
1014             opcode = (insn >> 27) & 7;
1015             operator = (insn >> 24) & 7;
1016             DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1017                     opcode_names[opcode - 5], reg,
1018                     operator_names[operator], data8, s->sfbr,
1019                     (insn & (1 << 23)) ? " SFBR" : "");
1020             op0 = op1 = 0;
1021             switch (opcode) {
1022             case 5: /* From SFBR */
1023                 op0 = s->sfbr;
1024                 op1 = data8;
1025                 break;
1026             case 6: /* To SFBR */
1027                 if (operator)
1028                     op0 = lsi_reg_readb(s, reg);
1029                 op1 = data8;
1030                 break;
1031             case 7: /* Read-modify-write */
1032                 if (operator)
1033                     op0 = lsi_reg_readb(s, reg);
1034                 if (insn & (1 << 23)) {
1035                     op1 = s->sfbr;
1036                 } else {
1037                     op1 = data8;
1038                 }
1039                 break;
1040             }
1041
1042             switch (operator) {
1043             case 0: /* move */
1044                 op0 = op1;
1045                 break;
1046             case 1: /* Shift left */
1047                 op1 = op0 >> 7;
1048                 op0 = (op0 << 1) | s->carry;
1049                 s->carry = op1;
1050                 break;
1051             case 2: /* OR */
1052                 op0 |= op1;
1053                 break;
1054             case 3: /* XOR */
1055                 op0 ^= op1;
1056                 break;
1057             case 4: /* AND */
1058                 op0 &= op1;
1059                 break;
1060             case 5: /* SHR */
1061                 op1 = op0 & 1;
1062                 op0 = (op0 >> 1) | (s->carry << 7);
1063                 s->carry = op1;
1064                 break;
1065             case 6: /* ADD */
1066                 op0 += op1;
1067                 s->carry = op0 < op1;
1068                 break;
1069             case 7: /* ADC */
1070                 op0 += op1 + s->carry;
1071                 if (s->carry)
1072                     s->carry = op0 <= op1;
1073                 else
1074                     s->carry = op0 < op1;
1075                 break;
1076             }
1077
1078             switch (opcode) {
1079             case 5: /* From SFBR */
1080             case 7: /* Read-modify-write */
1081                 lsi_reg_writeb(s, reg, op0);
1082                 break;
1083             case 6: /* To SFBR */
1084                 s->sfbr = op0;
1085                 break;
1086             }
1087         }
1088         break;
1089
1090     case 2: /* Transfer Control.  */
1091         {
1092             int cond;
1093             int jmp;
1094
1095             if ((insn & 0x002e0000) == 0) {
1096                 DPRINTF("NOP\n");
1097                 break;
1098             }
1099             if (s->sist1 & LSI_SIST1_STO) {
1100                 DPRINTF("Delayed select timeout\n");
1101                 lsi_stop_script(s);
1102                 break;
1103             }
1104             cond = jmp = (insn & (1 << 19)) != 0;
1105             if (cond == jmp && (insn & (1 << 21))) {
1106                 DPRINTF("Compare carry %d\n", s->carry == jmp);
1107                 cond = s->carry != 0;
1108             }
1109             if (cond == jmp && (insn & (1 << 17))) {
1110                 DPRINTF("Compare phase %d %c= %d\n",
1111                         (s->sstat1 & PHASE_MASK),
1112                         jmp ? '=' : '!',
1113                         ((insn >> 24) & 7));
1114                 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1115             }
1116             if (cond == jmp && (insn & (1 << 18))) {
1117                 uint8_t mask;
1118
1119                 mask = (~insn >> 8) & 0xff;
1120                 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1121                         s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1122                 cond = (s->sfbr & mask) == (insn & mask);
1123             }
1124             if (cond == jmp) {
1125                 if (insn & (1 << 23)) {
1126                     /* Relative address.  */
1127                     addr = s->dsp + sxt24(addr);
1128                 }
1129                 switch ((insn >> 27) & 7) {
1130                 case 0: /* Jump */
1131                     DPRINTF("Jump to 0x%08x\n", addr);
1132                     s->dsp = addr;
1133                     break;
1134                 case 1: /* Call */
1135                     DPRINTF("Call 0x%08x\n", addr);
1136                     s->temp = s->dsp;
1137                     s->dsp = addr;
1138                     break;
1139                 case 2: /* Return */
1140                     DPRINTF("Return to 0x%08x\n", s->temp);
1141                     s->dsp = s->temp;
1142                     break;
1143                 case 3: /* Interrupt */
1144                     DPRINTF("Interrupt 0x%08x\n", s->dsps);
1145                     if ((insn & (1 << 20)) != 0) {
1146                         s->istat0 |= LSI_ISTAT0_INTF;
1147                         lsi_update_irq(s);
1148                     } else {
1149                         lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1150                     }
1151                     break;
1152                 default:
1153                     DPRINTF("Illegal transfer control\n");
1154                     lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1155                     break;
1156                 }
1157             } else {
1158                 DPRINTF("Control condition failed\n");
1159             }
1160         }
1161         break;
1162
1163     case 3:
1164         if ((insn & (1 << 29)) == 0) {
1165             /* Memory move.  */
1166             uint32_t dest;
1167             /* ??? The docs imply the destination address is loaded into
1168                the TEMP register.  However the Linux drivers rely on
1169                the value being presrved.  */
1170             dest = read_dword(s, s->dsp);
1171             s->dsp += 4;
1172             lsi_memcpy(s, dest, addr, insn & 0xffffff);
1173         } else {
1174             uint8_t data[7];
1175             int reg;
1176             int n;
1177             int i;
1178
1179             if (insn & (1 << 28)) {
1180                 addr = s->dsa + sxt24(addr);
1181             }
1182             n = (insn & 7);
1183             reg = (insn >> 16) & 0xff;
1184             if (insn & (1 << 24)) {
1185                 cpu_physical_memory_read(addr, data, n);
1186                 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1187                         addr, *(int *)data);
1188                 for (i = 0; i < n; i++) {
1189                     lsi_reg_writeb(s, reg + i, data[i]);
1190                 }
1191             } else {
1192                 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1193                 for (i = 0; i < n; i++) {
1194                     data[i] = lsi_reg_readb(s, reg + i);
1195                 }
1196                 cpu_physical_memory_write(addr, data, n);
1197             }
1198         }
1199     }
1200     /* ??? Need to avoid infinite loops.  */
1201     if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1202         if (s->dcntl & LSI_DCNTL_SSM) {
1203             lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1204         } else {
1205             goto again;
1206         }
1207     }
1208     DPRINTF("SCRIPTS execution stopped\n");
1209 }
1210
1211 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1212 {
1213     uint8_t tmp;
1214 #define CASE_GET_REG32(name, addr) \
1215     case addr: return s->name & 0xff; \
1216     case addr + 1: return (s->name >> 8) & 0xff; \
1217     case addr + 2: return (s->name >> 16) & 0xff; \
1218     case addr + 3: return (s->name >> 24) & 0xff;
1219
1220 #ifdef DEBUG_LSI_REG
1221     DPRINTF("Read reg %x\n", offset);
1222 #endif
1223     switch (offset) {
1224     case 0x00: /* SCNTL0 */
1225         return s->scntl0;
1226     case 0x01: /* SCNTL1 */
1227         return s->scntl1;
1228     case 0x02: /* SCNTL2 */
1229         return s->scntl2;
1230     case 0x03: /* SCNTL3 */
1231         return s->scntl3;
1232     case 0x04: /* SCID */
1233         return s->scid;
1234     case 0x05: /* SXFER */
1235         return s->sxfer;
1236     case 0x06: /* SDID */
1237         return s->sdid;
1238     case 0x07: /* GPREG0 */
1239         return 0x7f;
1240     case 0x08: /* Revision ID */
1241         return 0x00;
1242     case 0xa: /* SSID */
1243         return s->ssid;
1244     case 0xb: /* SBCL */
1245         /* ??? This is not correct. However it's (hopefully) only
1246            used for diagnostics, so should be ok.  */
1247         return 0;
1248     case 0xc: /* DSTAT */
1249         tmp = s->dstat | 0x80;
1250         if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1251             s->dstat = 0;
1252         lsi_update_irq(s);
1253         return tmp;
1254     case 0x0d: /* SSTAT0 */
1255         return s->sstat0;
1256     case 0x0e: /* SSTAT1 */
1257         return s->sstat1;
1258     case 0x0f: /* SSTAT2 */
1259         return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1260     CASE_GET_REG32(dsa, 0x10)
1261     case 0x14: /* ISTAT0 */
1262         return s->istat0;
1263     case 0x16: /* MBOX0 */
1264         return s->mbox0;
1265     case 0x17: /* MBOX1 */
1266         return s->mbox1;
1267     case 0x18: /* CTEST0 */
1268         return 0xff;
1269     case 0x19: /* CTEST1 */
1270         return 0;
1271     case 0x1a: /* CTEST2 */
1272         tmp = LSI_CTEST2_DACK | LSI_CTEST2_CM;
1273         if (s->istat0 & LSI_ISTAT0_SIGP) {
1274             s->istat0 &= ~LSI_ISTAT0_SIGP;
1275             tmp |= LSI_CTEST2_SIGP;
1276         }
1277         return tmp;
1278     case 0x1b: /* CTEST3 */
1279         return s->ctest3;
1280     CASE_GET_REG32(temp, 0x1c)
1281     case 0x20: /* DFIFO */
1282         return 0;
1283     case 0x21: /* CTEST4 */
1284         return s->ctest4;
1285     case 0x22: /* CTEST5 */
1286         return s->ctest5;
1287     case 0x23: /* CTEST6 */
1288          return 0;
1289     case 0x24: /* DBC[0:7] */
1290         return s->dbc & 0xff;
1291     case 0x25: /* DBC[8:15] */
1292         return (s->dbc >> 8) & 0xff;
1293     case 0x26: /* DBC[16->23] */
1294         return (s->dbc >> 16) & 0xff;
1295     case 0x27: /* DCMD */
1296         return s->dcmd;
1297     CASE_GET_REG32(dsp, 0x2c)
1298     CASE_GET_REG32(dsps, 0x30)
1299     CASE_GET_REG32(scratch[0], 0x34)
1300     case 0x38: /* DMODE */
1301         return s->dmode;
1302     case 0x39: /* DIEN */
1303         return s->dien;
1304     case 0x3b: /* DCNTL */
1305         return s->dcntl;
1306     case 0x40: /* SIEN0 */
1307         return s->sien0;
1308     case 0x41: /* SIEN1 */
1309         return s->sien1;
1310     case 0x42: /* SIST0 */
1311         tmp = s->sist0;
1312         s->sist0 = 0;
1313         lsi_update_irq(s);
1314         return tmp;
1315     case 0x43: /* SIST1 */
1316         tmp = s->sist1;
1317         s->sist1 = 0;
1318         lsi_update_irq(s);
1319         return tmp;
1320     case 0x47: /* GPCNTL0 */
1321         return 0x0f;
1322     case 0x48: /* STIME0 */
1323         return s->stime0;
1324     case 0x4a: /* RESPID0 */
1325         return s->respid0;
1326     case 0x4b: /* RESPID1 */
1327         return s->respid1;
1328     case 0x4d: /* STEST1 */
1329         return s->stest1;
1330     case 0x4e: /* STEST2 */
1331         return s->stest2;
1332     case 0x4f: /* STEST3 */
1333         return s->stest3;
1334     case 0x50: /* SIDL */
1335         /* This is needed by the linux drivers.  We currently only update it
1336            during the MSG IN phase.  */
1337         return s->sidl;
1338     case 0x52: /* STEST4 */
1339         return 0xe0;
1340     case 0x56: /* CCNTL0 */
1341         return s->ccntl0;
1342     case 0x57: /* CCNTL1 */
1343         return s->ccntl1;
1344     case 0x58: /* SBDL */
1345         /* Some drivers peek at the data bus during the MSG IN phase.  */
1346         if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1347             return s->msg[0];
1348         return 0;
1349     case 0x59: /* SBDL high */
1350         return 0;
1351     CASE_GET_REG32(mmrs, 0xa0)
1352     CASE_GET_REG32(mmws, 0xa4)
1353     CASE_GET_REG32(sfs, 0xa8)
1354     CASE_GET_REG32(drs, 0xac)
1355     CASE_GET_REG32(sbms, 0xb0)
1356     CASE_GET_REG32(dmbs, 0xb4)
1357     CASE_GET_REG32(dnad64, 0xb8)
1358     CASE_GET_REG32(pmjad1, 0xc0)
1359     CASE_GET_REG32(pmjad2, 0xc4)
1360     CASE_GET_REG32(rbc, 0xc8)
1361     CASE_GET_REG32(ua, 0xcc)
1362     CASE_GET_REG32(ia, 0xd4)
1363     CASE_GET_REG32(sbc, 0xd8)
1364     CASE_GET_REG32(csbc, 0xdc)
1365     }
1366     if (offset >= 0x5c && offset < 0xa0) {
1367         int n;
1368         int shift;
1369         n = (offset - 0x58) >> 2;
1370         shift = (offset & 3) * 8;
1371         return (s->scratch[n] >> shift) & 0xff;
1372     }
1373     BADF("readb 0x%x\n", offset);
1374     exit(1);
1375 #undef CASE_GET_REG32
1376 }
1377
1378 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1379 {
1380 #define CASE_SET_REG32(name, addr) \
1381     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
1382     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
1383     case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1384     case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1385
1386 #ifdef DEBUG_LSI_REG
1387     DPRINTF("Write reg %x = %02x\n", offset, val);
1388 #endif
1389     switch (offset) {
1390     case 0x00: /* SCNTL0 */
1391         s->scntl0 = val;
1392         if (val & LSI_SCNTL0_START) {
1393             BADF("Start sequence not implemented\n");
1394         }
1395         break;
1396     case 0x01: /* SCNTL1 */
1397         s->scntl1 = val & ~LSI_SCNTL1_SST;
1398         if (val & LSI_SCNTL1_IARB) {
1399             BADF("Immediate Arbritration not implemented\n");
1400         }
1401         if (val & LSI_SCNTL1_RST) {
1402             s->sstat0 |= LSI_SSTAT0_RST;
1403             lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1404         } else {
1405             s->sstat0 &= ~LSI_SSTAT0_RST;
1406         }
1407         break;
1408     case 0x02: /* SCNTL2 */
1409         val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1410         s->scntl2 = val;
1411         break;
1412     case 0x03: /* SCNTL3 */
1413         s->scntl3 = val;
1414         break;
1415     case 0x04: /* SCID */
1416         s->scid = val;
1417         break;
1418     case 0x05: /* SXFER */
1419         s->sxfer = val;
1420         break;
1421     case 0x06: /* SDID */
1422         if ((val & 0xf) != (s->ssid & 0xf))
1423             BADF("Destination ID does not match SSID\n");
1424         s->sdid = val & 0xf;
1425         break;
1426     case 0x07: /* GPREG0 */
1427         break;
1428     case 0x08: /* SFBR */
1429         /* The CPU is not allowed to write to this register.  However the
1430            SCRIPTS register move instructions are.  */
1431         s->sfbr = val;
1432         break;
1433     case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1434         /* Linux writes to these readonly registers on startup.  */
1435         return;
1436     CASE_SET_REG32(dsa, 0x10)
1437     case 0x14: /* ISTAT0 */
1438         s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1439         if (val & LSI_ISTAT0_ABRT) {
1440             lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1441         }
1442         if (val & LSI_ISTAT0_INTF) {
1443             s->istat0 &= ~LSI_ISTAT0_INTF;
1444             lsi_update_irq(s);
1445         }
1446         if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1447             DPRINTF("Woken by SIGP\n");
1448             s->waiting = 0;
1449             s->dsp = s->dnad;
1450             lsi_execute_script(s);
1451         }
1452         if (val & LSI_ISTAT0_SRST) {
1453             lsi_soft_reset(s);
1454         }
1455         break;
1456     case 0x16: /* MBOX0 */
1457         s->mbox0 = val;
1458         break;
1459     case 0x17: /* MBOX1 */
1460         s->mbox1 = val;
1461         break;
1462     case 0x1b: /* CTEST3 */
1463         s->ctest3 = val & 0x0f;
1464         break;
1465     CASE_SET_REG32(temp, 0x1c)
1466     case 0x21: /* CTEST4 */
1467         if (val & 7) {
1468            BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1469         }
1470         s->ctest4 = val;
1471         break;
1472     case 0x22: /* CTEST5 */
1473         if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1474             BADF("CTEST5 DMA increment not implemented\n");
1475         }
1476         s->ctest5 = val;
1477         break;
1478     case 0x2c: /* DSP[0:7] */
1479         s->dsp &= 0xffffff00;
1480         s->dsp |= val;
1481         break;
1482     case 0x2d: /* DSP[8:15] */
1483         s->dsp &= 0xffff00ff;
1484         s->dsp |= val << 8;
1485         break;
1486     case 0x2e: /* DSP[16:23] */
1487         s->dsp &= 0xff00ffff;
1488         s->dsp |= val << 16;
1489         break;
1490     case 0x2f: /* DSP[24:31] */
1491         s->dsp &= 0x00ffffff;
1492         s->dsp |= val << 24;
1493         if ((s->dmode & LSI_DMODE_MAN) == 0
1494             && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1495             lsi_execute_script(s);
1496         break;
1497     CASE_SET_REG32(dsps, 0x30)
1498     CASE_SET_REG32(scratch[0], 0x34)
1499     case 0x38: /* DMODE */
1500         if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1501             BADF("IO mappings not implemented\n");
1502         }
1503         s->dmode = val;
1504         break;
1505     case 0x39: /* DIEN */
1506         s->dien = val;
1507         lsi_update_irq(s);
1508         break;
1509     case 0x3b: /* DCNTL */
1510         s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1511         if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1512             lsi_execute_script(s);
1513         break;
1514     case 0x40: /* SIEN0 */
1515         s->sien0 = val;
1516         lsi_update_irq(s);
1517         break;
1518     case 0x41: /* SIEN1 */
1519         s->sien1 = val;
1520         lsi_update_irq(s);
1521         break;
1522     case 0x47: /* GPCNTL0 */
1523         break;
1524     case 0x48: /* STIME0 */
1525         s->stime0 = val;
1526         break;
1527     case 0x49: /* STIME1 */
1528         if (val & 0xf) {
1529             DPRINTF("General purpose timer not implemented\n");
1530             /* ??? Raising the interrupt immediately seems to be sufficient
1531                to keep the FreeBSD driver happy.  */
1532             lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1533         }
1534         break;
1535     case 0x4a: /* RESPID0 */
1536         s->respid0 = val;
1537         break;
1538     case 0x4b: /* RESPID1 */
1539         s->respid1 = val;
1540         break;
1541     case 0x4d: /* STEST1 */
1542         s->stest1 = val;
1543         break;
1544     case 0x4e: /* STEST2 */
1545         if (val & 1) {
1546             BADF("Low level mode not implemented\n");
1547         }
1548         s->stest2 = val;
1549         break;
1550     case 0x4f: /* STEST3 */
1551         if (val & 0x41) {
1552             BADF("SCSI FIFO test mode not implemented\n");
1553         }
1554         s->stest3 = val;
1555         break;
1556     case 0x56: /* CCNTL0 */
1557         s->ccntl0 = val;
1558         break;
1559     case 0x57: /* CCNTL1 */
1560         s->ccntl1 = val;
1561         break;
1562     CASE_SET_REG32(mmrs, 0xa0)
1563     CASE_SET_REG32(mmws, 0xa4)
1564     CASE_SET_REG32(sfs, 0xa8)
1565     CASE_SET_REG32(drs, 0xac)
1566     CASE_SET_REG32(sbms, 0xb0)
1567     CASE_SET_REG32(dmbs, 0xb4)
1568     CASE_SET_REG32(dnad64, 0xb8)
1569     CASE_SET_REG32(pmjad1, 0xc0)
1570     CASE_SET_REG32(pmjad2, 0xc4)
1571     CASE_SET_REG32(rbc, 0xc8)
1572     CASE_SET_REG32(ua, 0xcc)
1573     CASE_SET_REG32(ia, 0xd4)
1574     CASE_SET_REG32(sbc, 0xd8)
1575     CASE_SET_REG32(csbc, 0xdc)
1576     default:
1577         if (offset >= 0x5c && offset < 0xa0) {
1578             int n;
1579             int shift;
1580             n = (offset - 0x58) >> 2;
1581             shift = (offset & 3) * 8;
1582             s->scratch[n] &= ~(0xff << shift);
1583             s->scratch[n] |= (val & 0xff) << shift;
1584         } else {
1585             BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1586         }
1587     }
1588 #undef CASE_SET_REG32
1589 }
1590
1591 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1592 {
1593     LSIState *s = (LSIState *)opaque;
1594
1595     lsi_reg_writeb(s, addr & 0xff, val);
1596 }
1597
1598 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1599 {
1600     LSIState *s = (LSIState *)opaque;
1601
1602     addr &= 0xff;
1603     lsi_reg_writeb(s, addr, val & 0xff);
1604     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1605 }
1606
1607 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1608 {
1609     LSIState *s = (LSIState *)opaque;
1610
1611     addr &= 0xff;
1612     lsi_reg_writeb(s, addr, val & 0xff);
1613     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1614     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1615     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1616 }
1617
1618 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1619 {
1620     LSIState *s = (LSIState *)opaque;
1621
1622     return lsi_reg_readb(s, addr & 0xff);
1623 }
1624
1625 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1626 {
1627     LSIState *s = (LSIState *)opaque;
1628     uint32_t val;
1629
1630     addr &= 0xff;
1631     val = lsi_reg_readb(s, addr);
1632     val |= lsi_reg_readb(s, addr + 1) << 8;
1633     return val;
1634 }
1635
1636 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1637 {
1638     LSIState *s = (LSIState *)opaque;
1639     uint32_t val;
1640     addr &= 0xff;
1641     val = lsi_reg_readb(s, addr);
1642     val |= lsi_reg_readb(s, addr + 1) << 8;
1643     val |= lsi_reg_readb(s, addr + 2) << 16;
1644     val |= lsi_reg_readb(s, addr + 3) << 24;
1645     return val;
1646 }
1647
1648 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1649     lsi_mmio_readb,
1650     lsi_mmio_readw,
1651     lsi_mmio_readl,
1652 };
1653
1654 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1655     lsi_mmio_writeb,
1656     lsi_mmio_writew,
1657     lsi_mmio_writel,
1658 };
1659
1660 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1661 {
1662     LSIState *s = (LSIState *)opaque;
1663     uint32_t newval;
1664     int shift;
1665
1666     addr &= 0x1fff;
1667     newval = s->script_ram[addr >> 2];
1668     shift = (addr & 3) * 8;
1669     newval &= ~(0xff << shift);
1670     newval |= val << shift;
1671     s->script_ram[addr >> 2] = newval;
1672 }
1673
1674 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1675 {
1676     LSIState *s = (LSIState *)opaque;
1677     uint32_t newval;
1678
1679     addr &= 0x1fff;
1680     newval = s->script_ram[addr >> 2];
1681     if (addr & 2) {
1682         newval = (newval & 0xffff) | (val << 16);
1683     } else {
1684         newval = (newval & 0xffff0000) | val;
1685     }
1686     s->script_ram[addr >> 2] = newval;
1687 }
1688
1689
1690 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1691 {
1692     LSIState *s = (LSIState *)opaque;
1693
1694     addr &= 0x1fff;
1695     s->script_ram[addr >> 2] = val;
1696 }
1697
1698 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1699 {
1700     LSIState *s = (LSIState *)opaque;
1701     uint32_t val;
1702
1703     addr &= 0x1fff;
1704     val = s->script_ram[addr >> 2];
1705     val >>= (addr & 3) * 8;
1706     return val & 0xff;
1707 }
1708
1709 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1710 {
1711     LSIState *s = (LSIState *)opaque;
1712     uint32_t val;
1713
1714     addr &= 0x1fff;
1715     val = s->script_ram[addr >> 2];
1716     if (addr & 2)
1717         val >>= 16;
1718     return le16_to_cpu(val);
1719 }
1720
1721 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1722 {
1723     LSIState *s = (LSIState *)opaque;
1724
1725     addr &= 0x1fff;
1726     return le32_to_cpu(s->script_ram[addr >> 2]);
1727 }
1728
1729 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1730     lsi_ram_readb,
1731     lsi_ram_readw,
1732     lsi_ram_readl,
1733 };
1734
1735 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1736     lsi_ram_writeb,
1737     lsi_ram_writew,
1738     lsi_ram_writel,
1739 };
1740
1741 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1742 {
1743     LSIState *s = (LSIState *)opaque;
1744     return lsi_reg_readb(s, addr & 0xff);
1745 }
1746
1747 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1748 {
1749     LSIState *s = (LSIState *)opaque;
1750     uint32_t val;
1751     addr &= 0xff;
1752     val = lsi_reg_readb(s, addr);
1753     val |= lsi_reg_readb(s, addr + 1) << 8;
1754     return val;
1755 }
1756
1757 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1758 {
1759     LSIState *s = (LSIState *)opaque;
1760     uint32_t val;
1761     addr &= 0xff;
1762     val = lsi_reg_readb(s, addr);
1763     val |= lsi_reg_readb(s, addr + 1) << 8;
1764     val |= lsi_reg_readb(s, addr + 2) << 16;
1765     val |= lsi_reg_readb(s, addr + 3) << 24;
1766     return val;
1767 }
1768
1769 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1770 {
1771     LSIState *s = (LSIState *)opaque;
1772     lsi_reg_writeb(s, addr & 0xff, val);
1773 }
1774
1775 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1776 {
1777     LSIState *s = (LSIState *)opaque;
1778     addr &= 0xff;
1779     lsi_reg_writeb(s, addr, val & 0xff);
1780     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1781 }
1782
1783 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1784 {
1785     LSIState *s = (LSIState *)opaque;
1786     addr &= 0xff;
1787     lsi_reg_writeb(s, addr, val & 0xff);
1788     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1789     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1790     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1791 }
1792
1793 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1794                            uint32_t addr, uint32_t size, int type)
1795 {
1796     LSIState *s = (LSIState *)pci_dev;
1797
1798     DPRINTF("Mapping IO at %08x\n", addr);
1799
1800     register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1801     register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1802     register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1803     register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1804     register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1805     register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1806 }
1807
1808 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1809                             uint32_t addr, uint32_t size, int type)
1810 {
1811     LSIState *s = (LSIState *)pci_dev;
1812
1813     DPRINTF("Mapping ram at %08x\n", addr);
1814     s->script_ram_base = addr;
1815     cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1816 }
1817
1818 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1819                              uint32_t addr, uint32_t size, int type)
1820 {
1821     LSIState *s = (LSIState *)pci_dev;
1822
1823     DPRINTF("Mapping registers at %08x\n", addr);
1824     cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1825 }
1826
1827 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1828 {
1829     LSIState *s = (LSIState *)opaque;
1830
1831     if (id < 0) {
1832         for (id = 0; id < LSI_MAX_DEVS; id++) {
1833             if (s->scsi_dev[id] == NULL)
1834                 break;
1835         }
1836     }
1837     if (id >= LSI_MAX_DEVS) {
1838         BADF("Bad Device ID %d\n", id);
1839         return;
1840     }
1841     if (s->scsi_dev[id]) {
1842         DPRINTF("Destroying device %d\n", id);
1843         s->scsi_dev[id]->destroy(s->scsi_dev[id]);
1844     }
1845     DPRINTF("Attaching block device %d\n", id);
1846     s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
1847     if (s->scsi_dev[id] == NULL)
1848         s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1849     bd->devfn = s->pci_dev.devfn;
1850 }
1851
1852 int lsi_scsi_uninit(PCIDevice *d)
1853 {
1854     LSIState *s = (LSIState *) d;
1855
1856     cpu_unregister_io_memory(s->mmio_io_addr);
1857     cpu_unregister_io_memory(s->ram_io_addr);
1858
1859     qemu_free(s->queue);
1860
1861     return 0;
1862 }
1863
1864 void *lsi_scsi_init(PCIBus *bus, int devfn)
1865 {
1866     LSIState *s;
1867
1868     s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1869                                         sizeof(*s), devfn, NULL, NULL);
1870     if (s == NULL) {
1871         fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1872         return NULL;
1873     }
1874
1875     s->pci_dev.config[0x00] = 0x00;
1876     s->pci_dev.config[0x01] = 0x10;
1877     s->pci_dev.config[0x02] = 0x12;
1878     s->pci_dev.config[0x03] = 0x00;
1879     s->pci_dev.config[0x0b] = 0x01;
1880     s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1881
1882     s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
1883                                              lsi_mmio_writefn, s);
1884     s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
1885                                             lsi_ram_writefn, s);
1886
1887     pci_register_io_region((struct PCIDevice *)s, 0, 256,
1888                            PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
1889     pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
1890                            PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
1891     pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
1892                            PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
1893     s->queue = qemu_malloc(sizeof(lsi_queue));
1894     s->queue_len = 1;
1895     s->active_commands = 0;
1896     s->pci_dev.unregister = lsi_scsi_uninit;
1897
1898     lsi_soft_reset(s);
1899
1900     return s;
1901 }
1902