hw/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdio.h>
  25 #include <sys/time.h>
  26 #include "hw.h"
  27 #include "sysemu.h"
  28 #include "qemu-timer.h"
  29
  30 #define D(x)
  31
  32 #define RW_TMR0_DIV   0x00
  33 #define R_TMR0_DATA   0x04
  34 #define RW_TMR0_CTRL  0x08
  35 #define RW_TMR1_DIV   0x10
  36 #define R_TMR1_DATA   0x14
  37 #define RW_TMR1_CTRL  0x18
  38 #define R_TIME        0x38
  39 #define RW_WD_CTRL    0x40
  40 #define R_WD_STAT     0x44
  41 #define RW_INTR_MASK  0x48
  42 #define RW_ACK_INTR   0x4c
  43 #define R_INTR        0x50
  44 #define R_MASKED_INTR 0x54
  45
  46 struct fs_timer_t {
  47         CPUState *env;
  48         qemu_irq *irq;
  49         qemu_irq *nmi;
  50         target_phys_addr_t base;
  51
  52         QEMUBH *bh_t0;
  53         QEMUBH *bh_t1;
  54         QEMUBH *bh_wd;
  55         ptimer_state *ptimer_t0;
  56         ptimer_state *ptimer_t1;
  57         ptimer_state *ptimer_wd;
  58         struct timeval last;
  59
  60         int wd_hits;
  61
  62         /* Control registers.  */
  63         uint32_t rw_tmr0_div;
  64         uint32_t r_tmr0_data;
  65         uint32_t rw_tmr0_ctrl;
  66
  67         uint32_t rw_tmr1_div;
  68         uint32_t r_tmr1_data;
  69         uint32_t rw_tmr1_ctrl;
  70
  71         uint32_t rw_wd_ctrl;
  72
  73         uint32_t rw_intr_mask;
  74         uint32_t rw_ack_intr;
  75         uint32_t r_intr;
  76         uint32_t r_masked_intr;
  77 };
  78
  79 static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
  80 {
  81         struct fs_timer_t *t = opaque;
  82         CPUState *env = t->env;
  83         cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
  84                   addr);
  85         return 0;
  86 }
  87
  88 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
  89 {
  90         struct fs_timer_t *t = opaque;
  91         uint32_t r = 0;
  92
  93         /* Make addr relative to this instances base.  */
  94         addr -= t->base;
  95         switch (addr) {
  96         case R_TMR0_DATA:
  97                 break;
  98         case R_TMR1_DATA:
  99                 D(printf ("R_TMR1_DATA\n"));
 100                 break;
 101         case R_TIME:
 102                 r = qemu_get_clock(vm_clock) * 10;
 103                 break;
 104         case RW_INTR_MASK:
 105                 r = t->rw_intr_mask;
 106                 break;
 107         case R_MASKED_INTR:
 108                 r = t->r_intr & t->rw_intr_mask;
 109                 break;
 110         default:
 111                 D(printf ("%s %x\n", __func__, addr));
 112                 break;
 113         }
 114         return r;
 115 }
 116
 117 static void
 118 timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
 119 {
 120         struct fs_timer_t *t = opaque;
 121         CPUState *env = t->env;
 122         cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
 123                   addr);
 124 }
 125
 126 #define TIMER_SLOWDOWN 1
 127 static void update_ctrl(struct fs_timer_t *t, int tnum)
 128 {
 129         unsigned int op;
 130         unsigned int freq;
 131         unsigned int freq_hz;
 132         unsigned int div;
 133         uint32_t ctrl;
 134
 135         ptimer_state *timer;
 136
 137         if (tnum == 0) {
 138                 ctrl = t->rw_tmr0_ctrl;
 139                 div = t->rw_tmr0_div;
 140                 timer = t->ptimer_t0;
 141         } else {
 142                 ctrl = t->rw_tmr1_ctrl;
 143                 div = t->rw_tmr1_div;
 144                 timer = t->ptimer_t1;
 145         }
 146
 147
 148         op = ctrl & 3;
 149         freq = ctrl >> 2;
 150         freq_hz = 32000000;
 151
 152         switch (freq)
 153         {
 154         case 0:
 155         case 1:
 156                 D(printf ("extern or disabled timer clock?\n"));
 157                 break;
 158         case 4: freq_hz =  29493000; break;
 159         case 5: freq_hz =  32000000; break;
 160         case 6: freq_hz =  32768000; break;
 161         case 7: freq_hz = 100001000; break;
 162         default:
 163                 abort();
 164                 break;
 165         }
 166
 167         D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
 168         div = div * TIMER_SLOWDOWN;
 169         div >>= 10;
 170         freq_hz >>= 10;
 171         ptimer_set_freq(timer, freq_hz);
 172         ptimer_set_limit(timer, div, 0);
 173
 174         switch (op)
 175         {
 176                 case 0:
 177                         /* Load.  */
 178                         ptimer_set_limit(timer, div, 1);
 179                         break;
 180                 case 1:
 181                         /* Hold.  */
 182                         ptimer_stop(timer);
 183                         break;
 184                 case 2:
 185                         /* Run.  */
 186                         ptimer_run(timer, 0);
 187                         break;
 188                 default:
 189                         abort();
 190                         break;
 191         }
 192 }
 193
 194 static void timer_update_irq(struct fs_timer_t *t)
 195 {
 196         t->r_intr &= ~(t->rw_ack_intr);
 197         t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 198
 199         D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 200         if (t->r_masked_intr)
 201                 qemu_irq_raise(t->irq[0]);
 202         else
 203                 qemu_irq_lower(t->irq[0]);
 204 }
 205
 206 static void timer0_hit(void *opaque)
 207 {
 208         struct fs_timer_t *t = opaque;
 209         t->r_intr |= 1;
 210         timer_update_irq(t);
 211 }
 212
 213 static void timer1_hit(void *opaque)
 214 {
 215         struct fs_timer_t *t = opaque;
 216         t->r_intr |= 2;
 217         timer_update_irq(t);
 218 }
 219
 220 static void watchdog_hit(void *opaque)
 221 {
 222         struct fs_timer_t *t = opaque;
 223         if (t->wd_hits == 0) {
 224                 /* real hw gives a single tick before reseting but we are
 225                    a bit friendlier to compensate for our slower execution.  */
 226                 ptimer_set_count(t->ptimer_wd, 10);
 227                 ptimer_run(t->ptimer_wd, 1);
 228                 qemu_irq_raise(t->nmi[0]);
 229         }
 230         else
 231                 qemu_system_reset_request();
 232
 233         t->wd_hits++;
 234 }
 235
 236 static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
 237 {
 238         unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
 239         unsigned int wd_key = t->rw_wd_ctrl >> 9;
 240         unsigned int wd_cnt = t->rw_wd_ctrl & 511;
 241         unsigned int new_key = value >> 9 & ((1 << 7) - 1);
 242         unsigned int new_cmd = (value >> 8) & 1;
 243
 244         /* If the watchdog is enabled, they written key must match the
 245            complement of the previous.  */
 246         wd_key = ~wd_key & ((1 << 7) - 1);
 247
 248         if (wd_en && wd_key != new_key)
 249                 return;
 250
 251         D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
 252                  wd_en, new_key, wd_key, new_cmd, wd_cnt));
 253
 254         if (t->wd_hits)
 255                 qemu_irq_lower(t->nmi[0]);
 256
 257         t->wd_hits = 0;
 258
 259         ptimer_set_freq(t->ptimer_wd, 760);
 260         if (wd_cnt == 0)
 261                 wd_cnt = 256;
 262         ptimer_set_count(t->ptimer_wd, wd_cnt);
 263         if (new_cmd)
 264                 ptimer_run(t->ptimer_wd, 1);
 265         else
 266                 ptimer_stop(t->ptimer_wd);
 267
 268         t->rw_wd_ctrl = value;
 269 }
 270
 271 static void
 272 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 273 {
 274         struct fs_timer_t *t = opaque;
 275
 276         /* Make addr relative to this instances base.  */
 277         addr -= t->base;
 278         switch (addr)
 279         {
 280                 case RW_TMR0_DIV:
 281                         t->rw_tmr0_div = value;
 282                         break;
 283                 case RW_TMR0_CTRL:
 284                         D(printf ("RW_TMR0_CTRL=%x\n", value));
 285                         t->rw_tmr0_ctrl = value;
 286                         update_ctrl(t, 0);
 287                         break;
 288                 case RW_TMR1_DIV:
 289                         t->rw_tmr1_div = value;
 290                         break;
 291                 case RW_TMR1_CTRL:
 292                         D(printf ("RW_TMR1_CTRL=%x\n", value));
 293                         t->rw_tmr1_ctrl = value;
 294                         update_ctrl(t, 1);
 295                         break;
 296                 case RW_INTR_MASK:
 297                         D(printf ("RW_INTR_MASK=%x\n", value));
 298                         t->rw_intr_mask = value;
 299                         timer_update_irq(t);
 300                         break;
 301                 case RW_WD_CTRL:
 302                         timer_watchdog_update(t, value);
 303                         break;
 304                 case RW_ACK_INTR:
 305                         t->rw_ack_intr = value;
 306                         timer_update_irq(t);
 307                         t->rw_ack_intr = 0;
 308                         break;
 309                 default:
 310                         printf ("%s " TARGET_FMT_plx " %x\n",
 311                                 __func__, addr, value);
 312                         break;
 313         }
 314 }
 315
 316 static CPUReadMemoryFunc *timer_read[] = {
 317         &timer_rinvalid,
 318         &timer_rinvalid,
 319         &timer_readl,
 320 };
 321
 322 static CPUWriteMemoryFunc *timer_write[] = {
 323         &timer_winvalid,
 324         &timer_winvalid,
 325         &timer_writel,
 326 };
 327
 328 static void etraxfs_timer_reset(void *opaque)
 329 {
 330         struct fs_timer_t *t = opaque;
 331
 332         ptimer_stop(t->ptimer_t0);
 333         ptimer_stop(t->ptimer_t1);
 334         ptimer_stop(t->ptimer_wd);
 335         t->rw_wd_ctrl = 0;
 336         t->r_intr = 0;
 337         t->rw_intr_mask = 0;
 338         qemu_irq_lower(t->irq[0]);
 339 }
 340
 341 void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
 342                         target_phys_addr_t base)
 343 {
 344         static struct fs_timer_t *t;
 345         int timer_regs;
 346
 347         t = qemu_mallocz(sizeof *t);
 348         if (!t)
 349                 return;
 350
 351         t->bh_t0 = qemu_bh_new(timer0_hit, t);
 352         t->bh_t1 = qemu_bh_new(timer1_hit, t);
 353         t->bh_wd = qemu_bh_new(watchdog_hit, t);
 354         t->ptimer_t0 = ptimer_init(t->bh_t0);
 355         t->ptimer_t1 = ptimer_init(t->bh_t1);
 356         t->ptimer_wd = ptimer_init(t->bh_wd);
 357         t->irq = irqs;
 358         t->nmi = nmi;
 359         t->env = env;
 360         t->base = base;
 361
 362         timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
 363         cpu_register_physical_memory (base, 0x5c, timer_regs);
 364
 365         qemu_register_reset(etraxfs_timer_reset, t);
 366 }