hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "console.h"
  28
  29 #include "qemu-kvm.h"
  30
  31 /* debug PIC */
  32 //#define DEBUG_PIC
  33
  34 //#define DEBUG_IRQ_LATENCY
  35 //#define DEBUG_IRQ_COUNT
  36
  37 typedef struct PicState {
  38     uint8_t last_irr; /* edge detection */
  39     uint8_t irr; /* interrupt request register */
  40     uint8_t imr; /* interrupt mask register */
  41     uint8_t isr; /* interrupt service register */
  42     uint8_t priority_add; /* highest irq priority */
  43     uint8_t irq_base;
  44     uint8_t read_reg_select;
  45     uint8_t poll;
  46     uint8_t special_mask;
  47     uint8_t init_state;
  48     uint8_t auto_eoi;
  49     uint8_t rotate_on_auto_eoi;
  50     uint8_t special_fully_nested_mode;
  51     uint8_t init4; /* true if 4 byte init */
  52     uint8_t single_mode; /* true if slave pic is not initialized */
  53     uint8_t elcr; /* PIIX edge/trigger selection*/
  54     uint8_t elcr_mask;
  55     PicState2 *pics_state;
  56 } PicState;
  57
  58 struct PicState2 {
  59     /* 0 is master pic, 1 is slave pic */
  60     /* XXX: better separation between the two pics */
  61     PicState pics[2];
  62     qemu_irq parent_irq;
  63     void *irq_request_opaque;
  64     /* IOAPIC callback support */
  65     SetIRQFunc *alt_irq_func;
  66     void *alt_irq_opaque;
  67 };
  68
  69 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  70 static int irq_level[16];
  71 #endif
  72 #ifdef DEBUG_IRQ_COUNT
  73 static uint64_t irq_count[16];
  74 #endif
  75
  76 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  77 static inline void pic_set_irq1(PicState *s, int irq, int level)
  78 {
  79     int mask;
  80     mask = 1 << irq;
  81     if (s->elcr & mask) {
  82         /* level triggered */
  83         if (level) {
  84             s->irr |= mask;
  85             s->last_irr |= mask;
  86         } else {
  87             s->irr &= ~mask;
  88             s->last_irr &= ~mask;
  89         }
  90     } else {
  91         /* edge triggered */
  92         if (level) {
  93             if ((s->last_irr & mask) == 0)
  94                 s->irr |= mask;
  95             s->last_irr |= mask;
  96         } else {
  97             s->last_irr &= ~mask;
  98         }
  99     }
 100 }
 101
 102 /* return the highest priority found in mask (highest = smallest
 103    number). Return 8 if no irq */
 104 static inline int get_priority(PicState *s, int mask)
 105 {
 106     int priority;
 107     if (mask == 0)
 108         return 8;
 109     priority = 0;
 110     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 111         priority++;
 112     return priority;
 113 }
 114
 115 /* return the pic wanted interrupt. return -1 if none */
 116 static int pic_get_irq(PicState *s)
 117 {
 118     int mask, cur_priority, priority;
 119
 120     mask = s->irr & ~s->imr;
 121     priority = get_priority(s, mask);
 122     if (priority == 8)
 123         return -1;
 124     /* compute current priority. If special fully nested mode on the
 125        master, the IRQ coming from the slave is not taken into account
 126        for the priority computation. */
 127     mask = s->isr;
 128     if (s->special_mask)
 129         mask &= ~s->imr;
 130     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 131         mask &= ~(1 << 2);
 132     cur_priority = get_priority(s, mask);
 133     if (priority < cur_priority) {
 134         /* higher priority found: an irq should be generated */
 135         return (priority + s->priority_add) & 7;
 136     } else {
 137         return -1;
 138     }
 139 }
 140
 141 /* raise irq to CPU if necessary. must be called every time the active
 142    irq may change */
 143 /* XXX: should not export it, but it is needed for an APIC kludge */
 144 void pic_update_irq(PicState2 *s)
 145 {
 146     int irq2, irq;
 147
 148     /* first look at slave pic */
 149     irq2 = pic_get_irq(&s->pics[1]);
 150     if (irq2 >= 0) {
 151         /* if irq request by slave pic, signal master PIC */
 152         pic_set_irq1(&s->pics[0], 2, 1);
 153         pic_set_irq1(&s->pics[0], 2, 0);
 154     }
 155     /* look at requested irq */
 156     irq = pic_get_irq(&s->pics[0]);
 157     if (irq >= 0) {
 158 #if defined(DEBUG_PIC)
 159         {
 160             int i;
 161             for(i = 0; i < 2; i++) {
 162                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 163                        i, s->pics[i].imr, s->pics[i].irr,
 164                        s->pics[i].priority_add);
 165
 166             }
 167         }
 168         printf("pic: cpu_interrupt\n");
 169 #endif
 170         qemu_irq_raise(s->parent_irq);
 171     }
 172
 173 /* all targets should do this rather than acking the IRQ in the cpu */
 174 #if defined(TARGET_MIPS) || defined(TARGET_PPC)
 175     else {
 176         qemu_irq_lower(s->parent_irq);
 177     }
 178 #endif
 179 }
 180
 181 #ifdef DEBUG_IRQ_LATENCY
 182 int64_t irq_time[16];
 183 #endif
 184
 185 static void i8259_set_irq(void *opaque, int irq, int level)
 186 {
 187     PicState2 *s = opaque;
 188 #ifdef KVM_CAP_IRQCHIP
 189     if (kvm_enabled())
 190         if (kvm_set_irq(irq, level))
 191             return;
 192 #endif
 193 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 194     if (level != irq_level[irq]) {
 195 #if defined(DEBUG_PIC)
 196         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 197 #endif
 198         irq_level[irq] = level;
 199 #ifdef DEBUG_IRQ_COUNT
 200         if (level == 1)
 201             irq_count[irq]++;
 202 #endif
 203     }
 204 #endif
 205 #ifdef DEBUG_IRQ_LATENCY
 206     if (level) {
 207         irq_time[irq] = qemu_get_clock(vm_clock);
 208     }
 209 #endif
 210     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 211     /* used for IOAPIC irqs */
 212     if (s->alt_irq_func)
 213         s->alt_irq_func(s->alt_irq_opaque, irq, level);
 214     pic_update_irq(s);
 215 }
 216
 217 /* acknowledge interrupt 'irq' */
 218 static inline void pic_intack(PicState *s, int irq)
 219 {
 220     if (s->auto_eoi) {
 221         if (s->rotate_on_auto_eoi)
 222             s->priority_add = (irq + 1) & 7;
 223     } else {
 224         s->isr |= (1 << irq);
 225     }
 226
 227     /* We don't clear a level sensitive interrupt here */
 228     if (!(s->elcr & (1 << irq)))
 229         s->irr &= ~(1 << irq);
 230
 231 }
 232
 233 extern int time_drift_fix;
 234
 235 int pic_read_irq(PicState2 *s)
 236 {
 237     int irq, irq2, intno;
 238
 239     irq = pic_get_irq(&s->pics[0]);
 240     if (irq >= 0) {
 241
 242         pic_intack(&s->pics[0], irq);
 243 #ifndef TARGET_IA64
 244         if (time_drift_fix && irq == 0) {
 245             extern int64_t timer_acks, timer_ints_to_push;
 246             timer_acks++;
 247             if (timer_ints_to_push > 0) {
 248                 timer_ints_to_push--;
 249                 /* simulate an edge irq0, like the one generated by i8254 */
 250                 pic_set_irq1(&s->pics[0], 0, 0);
 251                 pic_set_irq1(&s->pics[0], 0, 1);
 252             }
 253         }
 254 #endif
 255         if (irq == 2) {
 256             irq2 = pic_get_irq(&s->pics[1]);
 257             if (irq2 >= 0) {
 258                 pic_intack(&s->pics[1], irq2);
 259             } else {
 260                 /* spurious IRQ on slave controller */
 261                 irq2 = 7;
 262             }
 263             intno = s->pics[1].irq_base + irq2;
 264             irq = irq2 + 8;
 265         } else {
 266             intno = s->pics[0].irq_base + irq;
 267         }
 268     } else {
 269         /* spurious IRQ on host controller */
 270         irq = 7;
 271         intno = s->pics[0].irq_base + irq;
 272     }
 273     pic_update_irq(s);
 274
 275 #ifdef DEBUG_IRQ_LATENCY
 276     printf("IRQ%d latency=%0.3fus\n",
 277            irq,
 278            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 279 #endif
 280 #if defined(DEBUG_PIC)
 281     printf("pic_interrupt: irq=%d\n", irq);
 282 #endif
 283     return intno;
 284 }
 285
 286 static void pic_reset(void *opaque)
 287 {
 288     PicState *s = opaque;
 289
 290     s->last_irr = 0;
 291     s->irr = 0;
 292     s->imr = 0;
 293     s->isr = 0;
 294     s->priority_add = 0;
 295     s->irq_base = 0;
 296     s->read_reg_select = 0;
 297     s->poll = 0;
 298     s->special_mask = 0;
 299     s->init_state = 0;
 300     s->auto_eoi = 0;
 301     s->rotate_on_auto_eoi = 0;
 302     s->special_fully_nested_mode = 0;
 303     s->init4 = 0;
 304     s->single_mode = 0;
 305     /* Note: ELCR is not reset */
 306 }
 307
 308 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 309 {
 310     PicState *s = opaque;
 311     int priority, cmd, irq;
 312
 313 #ifdef DEBUG_PIC
 314     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 315 #endif
 316     addr &= 1;
 317     if (addr == 0) {
 318         if (val & 0x10) {
 319             /* init */
 320             pic_reset(s);
 321             /* deassert a pending interrupt */
 322             qemu_irq_lower(s->pics_state->parent_irq);
 323             s->init_state = 1;
 324             s->init4 = val & 1;
 325             s->single_mode = val & 2;
 326             if (val & 0x08)
 327                 hw_error("level sensitive irq not supported");
 328         } else if (val & 0x08) {
 329             if (val & 0x04)
 330                 s->poll = 1;
 331             if (val & 0x02)
 332                 s->read_reg_select = val & 1;
 333             if (val & 0x40)
 334                 s->special_mask = (val >> 5) & 1;
 335         } else {
 336             cmd = val >> 5;
 337             switch(cmd) {
 338             case 0:
 339             case 4:
 340                 s->rotate_on_auto_eoi = cmd >> 2;
 341                 break;
 342             case 1: /* end of interrupt */
 343             case 5:
 344                 priority = get_priority(s, s->isr);
 345                 if (priority != 8) {
 346                     irq = (priority + s->priority_add) & 7;
 347                     s->isr &= ~(1 << irq);
 348                     if (cmd == 5)
 349                         s->priority_add = (irq + 1) & 7;
 350                     pic_update_irq(s->pics_state);
 351                 }
 352                 break;
 353             case 3:
 354                 irq = val & 7;
 355                 s->isr &= ~(1 << irq);
 356                 pic_update_irq(s->pics_state);
 357                 break;
 358             case 6:
 359                 s->priority_add = (val + 1) & 7;
 360                 pic_update_irq(s->pics_state);
 361                 break;
 362             case 7:
 363                 irq = val & 7;
 364                 s->isr &= ~(1 << irq);
 365                 s->priority_add = (irq + 1) & 7;
 366                 pic_update_irq(s->pics_state);
 367                 break;
 368             default:
 369                 /* no operation */
 370                 break;
 371             }
 372         }
 373     } else {
 374         switch(s->init_state) {
 375         case 0:
 376             /* normal mode */
 377             s->imr = val;
 378             pic_update_irq(s->pics_state);
 379             break;
 380         case 1:
 381             s->irq_base = val & 0xf8;
 382             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 383             break;
 384         case 2:
 385             if (s->init4) {
 386                 s->init_state = 3;
 387             } else {
 388                 s->init_state = 0;
 389             }
 390             break;
 391         case 3:
 392             s->special_fully_nested_mode = (val >> 4) & 1;
 393             s->auto_eoi = (val >> 1) & 1;
 394             s->init_state = 0;
 395             break;
 396         }
 397     }
 398 }
 399
 400 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 401 {
 402     int ret;
 403
 404     ret = pic_get_irq(s);
 405     if (ret >= 0) {
 406         if (addr1 >> 7) {
 407             s->pics_state->pics[0].isr &= ~(1 << 2);
 408             s->pics_state->pics[0].irr &= ~(1 << 2);
 409         }
 410         s->irr &= ~(1 << ret);
 411         s->isr &= ~(1 << ret);
 412         if (addr1 >> 7 || ret != 2)
 413             pic_update_irq(s->pics_state);
 414     } else {
 415         ret = 0x07;
 416         pic_update_irq(s->pics_state);
 417     }
 418
 419     return ret;
 420 }
 421
 422 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 423 {
 424     PicState *s = opaque;
 425     unsigned int addr;
 426     int ret;
 427
 428     addr = addr1;
 429     addr &= 1;
 430     if (s->poll) {
 431         ret = pic_poll_read(s, addr1);
 432         s->poll = 0;
 433     } else {
 434         if (addr == 0) {
 435             if (s->read_reg_select)
 436                 ret = s->isr;
 437             else
 438                 ret = s->irr;
 439         } else {
 440             ret = s->imr;
 441         }
 442     }
 443 #ifdef DEBUG_PIC
 444     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 445 #endif
 446     return ret;
 447 }
 448
 449 /* memory mapped interrupt status */
 450 /* XXX: may be the same than pic_read_irq() */
 451 uint32_t pic_intack_read(PicState2 *s)
 452 {
 453     int ret;
 454
 455     ret = pic_poll_read(&s->pics[0], 0x00);
 456     if (ret == 2)
 457         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 458     /* Prepare for ISR read */
 459     s->pics[0].read_reg_select = 1;
 460
 461     return ret;
 462 }
 463
 464 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 465 {
 466     PicState *s = opaque;
 467     s->elcr = val & s->elcr_mask;
 468 }
 469
 470 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 471 {
 472     PicState *s = opaque;
 473     return s->elcr;
 474 }
 475
 476 static void kvm_kernel_pic_save_to_user(PicState *s)
 477 {
 478 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 479     struct kvm_irqchip chip;
 480     struct kvm_pic_state *kpic;
 481
 482     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 483                    KVM_IRQCHIP_PIC_MASTER :
 484                    KVM_IRQCHIP_PIC_SLAVE;
 485     kvm_get_irqchip(kvm_context, &chip);
 486     kpic = &chip.chip.pic;
 487
 488     s->last_irr = kpic->last_irr;
 489     s->irr = kpic->irr;
 490     s->imr = kpic->imr;
 491     s->isr = kpic->isr;
 492     s->priority_add = kpic->priority_add;
 493     s->irq_base = kpic->irq_base;
 494     s->read_reg_select = kpic->read_reg_select;
 495     s->poll = kpic->poll;
 496     s->special_mask = kpic->special_mask;
 497     s->init_state = kpic->init_state;
 498     s->auto_eoi = kpic->auto_eoi;
 499     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 500     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 501     s->init4 = kpic->init4;
 502     s->elcr = kpic->elcr;
 503     s->elcr_mask = kpic->elcr_mask;
 504 #endif
 505 }
 506
 507 static void kvm_kernel_pic_load_from_user(PicState *s)
 508 {
 509 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 510     struct kvm_irqchip chip;
 511     struct kvm_pic_state *kpic;
 512
 513     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 514                    KVM_IRQCHIP_PIC_MASTER :
 515                    KVM_IRQCHIP_PIC_SLAVE;
 516     kpic = &chip.chip.pic;
 517
 518     kpic->last_irr = s->last_irr;
 519     kpic->irr = s->irr;
 520     kpic->imr = s->imr;
 521     kpic->isr = s->isr;
 522     kpic->priority_add = s->priority_add;
 523     kpic->irq_base = s->irq_base;
 524     kpic->read_reg_select = s->read_reg_select;
 525     kpic->poll = s->poll;
 526     kpic->special_mask = s->special_mask;
 527     kpic->init_state = s->init_state;
 528     kpic->auto_eoi = s->auto_eoi;
 529     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 530     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 531     kpic->init4 = s->init4;
 532     kpic->elcr = s->elcr;
 533     kpic->elcr_mask = s->elcr_mask;
 534
 535     kvm_set_irqchip(kvm_context, &chip);
 536 #endif
 537 }
 538
 539 static void pic_save(QEMUFile *f, void *opaque)
 540 {
 541     PicState *s = opaque;
 542
 543     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 544         kvm_kernel_pic_save_to_user(s);
 545     }
 546
 547     qemu_put_8s(f, &s->last_irr);
 548     qemu_put_8s(f, &s->irr);
 549     qemu_put_8s(f, &s->imr);
 550     qemu_put_8s(f, &s->isr);
 551     qemu_put_8s(f, &s->priority_add);
 552     qemu_put_8s(f, &s->irq_base);
 553     qemu_put_8s(f, &s->read_reg_select);
 554     qemu_put_8s(f, &s->poll);
 555     qemu_put_8s(f, &s->special_mask);
 556     qemu_put_8s(f, &s->init_state);
 557     qemu_put_8s(f, &s->auto_eoi);
 558     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 559     qemu_put_8s(f, &s->special_fully_nested_mode);
 560     qemu_put_8s(f, &s->init4);
 561     qemu_put_8s(f, &s->single_mode);
 562     qemu_put_8s(f, &s->elcr);
 563 }
 564
 565 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 566 {
 567     PicState *s = opaque;
 568
 569     if (version_id != 1)
 570         return -EINVAL;
 571
 572     qemu_get_8s(f, &s->last_irr);
 573     qemu_get_8s(f, &s->irr);
 574     qemu_get_8s(f, &s->imr);
 575     qemu_get_8s(f, &s->isr);
 576     qemu_get_8s(f, &s->priority_add);
 577     qemu_get_8s(f, &s->irq_base);
 578     qemu_get_8s(f, &s->read_reg_select);
 579     qemu_get_8s(f, &s->poll);
 580     qemu_get_8s(f, &s->special_mask);
 581     qemu_get_8s(f, &s->init_state);
 582     qemu_get_8s(f, &s->auto_eoi);
 583     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 584     qemu_get_8s(f, &s->special_fully_nested_mode);
 585     qemu_get_8s(f, &s->init4);
 586     qemu_get_8s(f, &s->single_mode);
 587     qemu_get_8s(f, &s->elcr);
 588
 589     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 590         kvm_kernel_pic_load_from_user(s);
 591     }
 592
 593     return 0;
 594 }
 595
 596 /* XXX: add generic master/slave system */
 597 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 598 {
 599     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 600     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 601     if (elcr_addr >= 0) {
 602         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 603         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 604     }
 605     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 606     qemu_register_reset(pic_reset, s);
 607 }
 608
 609 void pic_info(void)
 610 {
 611     int i;
 612     PicState *s;
 613
 614     if (!isa_pic)
 615         return;
 616
 617     for(i=0;i<2;i++) {
 618         s = &isa_pic->pics[i];
 619         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 620                     i, s->irr, s->imr, s->isr, s->priority_add,
 621                     s->irq_base, s->read_reg_select, s->elcr,
 622                     s->special_fully_nested_mode);
 623     }
 624 }
 625
 626 void irq_info(void)
 627 {
 628 #ifndef DEBUG_IRQ_COUNT
 629     term_printf("irq statistic code not compiled.\n");
 630 #else
 631     int i;
 632     int64_t count;
 633
 634     term_printf("IRQ statistics:\n");
 635     for (i = 0; i < 16; i++) {
 636         count = irq_count[i];
 637         if (count > 0)
 638             term_printf("%2d: %" PRId64 "\n", i, count);
 639     }
 640 #endif
 641 }
 642
 643 qemu_irq *i8259_init(qemu_irq parent_irq)
 644 {
 645     PicState2 *s;
 646
 647     s = qemu_mallocz(sizeof(PicState2));
 648     if (!s)
 649         return NULL;
 650     pic_init1(0x20, 0x4d0, &s->pics[0]);
 651     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 652     s->pics[0].elcr_mask = 0xf8;
 653     s->pics[1].elcr_mask = 0xde;
 654     s->parent_irq = parent_irq;
 655     s->pics[0].pics_state = s;
 656     s->pics[1].pics_state = s;
 657     isa_pic = s;
 658     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 659 }
 660
 661 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 662                           void *alt_irq_opaque)
 663 {
 664     s->alt_irq_func = alt_irq_func;
 665     s->alt_irq_opaque = alt_irq_opaque;
 666 }