hw/sun4c_intctl.c

   1 /*
   2  * QEMU Sparc Sun4c interrupt controller emulation
   3  *
   4  * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27 //#define DEBUG_IRQ_COUNT
  28 //#define DEBUG_IRQ
  29
  30 #ifdef DEBUG_IRQ
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("IRQ: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 /*
  38  * Registers of interrupt controller in sun4c.
  39  *
  40  */
  41
  42 #define MAX_PILS 16
  43
  44 typedef struct Sun4c_INTCTLState {
  45 #ifdef DEBUG_IRQ_COUNT
  46     uint64_t irq_count;
  47 #endif
  48     qemu_irq *cpu_irqs;
  49     const uint32_t *intbit_to_level;
  50     uint32_t pil_out;
  51     uint8_t reg;
  52     uint8_t pending;
  53 } Sun4c_INTCTLState;
  54
  55 #define INTCTL_MAXADDR 0
  56 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  57
  58 static void sun4c_check_interrupts(void *opaque);
  59
  60 static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
  61 {
  62     Sun4c_INTCTLState *s = opaque;
  63     uint32_t ret;
  64
  65     ret = s->reg;
  66     DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
  67
  68     return ret;
  69 }
  70
  71 static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
  72                                     uint32_t val)
  73 {
  74     Sun4c_INTCTLState *s = opaque;
  75
  76     DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
  77     val &= 0xbf;
  78     s->reg = val;
  79     sun4c_check_interrupts(s);
  80 }
  81
  82 static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
  83     sun4c_intctl_mem_readb,
  84     NULL,
  85     NULL,
  86 };
  87
  88 static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
  89     sun4c_intctl_mem_writeb,
  90     NULL,
  91     NULL,
  92 };
  93
  94 void sun4c_pic_info(void *opaque)
  95 {
  96     Sun4c_INTCTLState *s = opaque;
  97
  98     term_printf("master: pending 0x%2.2x, enabled 0x%2.2x\n", s->pending,
  99                 s->reg);
 100 }
 101
 102 void sun4c_irq_info(void *opaque)
 103 {
 104 #ifndef DEBUG_IRQ_COUNT
 105     term_printf("irq statistic code not compiled.\n");
 106 #else
 107     Sun4c_INTCTLState *s = opaque;
 108     int64_t count;
 109
 110     term_printf("IRQ statistics:\n");
 111     count = s->irq_count[i];
 112     if (count > 0)
 113         term_printf("%2d: %" PRId64 "\n", i, count);
 114 #endif
 115 }
 116
 117 static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
 118
 119 static void sun4c_check_interrupts(void *opaque)
 120 {
 121     Sun4c_INTCTLState *s = opaque;
 122     uint32_t pil_pending;
 123     unsigned int i;
 124
 125     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 126     pil_pending = 0;
 127     if (s->pending && !(s->reg & 0x80000000)) {
 128         for (i = 0; i < 8; i++) {
 129             if (s->pending & (1 << i))
 130                 pil_pending |= 1 << intbit_to_level[i];
 131         }
 132     }
 133
 134     for (i = 0; i < MAX_PILS; i++) {
 135         if (pil_pending & (1 << i)) {
 136             if (!(s->pil_out & (1 << i)))
 137                 qemu_irq_raise(s->cpu_irqs[i]);
 138         } else {
 139             if (s->pil_out & (1 << i))
 140                 qemu_irq_lower(s->cpu_irqs[i]);
 141         }
 142     }
 143     s->pil_out = pil_pending;
 144 }
 145
 146 /*
 147  * "irq" here is the bit number in the system interrupt register
 148  */
 149 static void sun4c_set_irq(void *opaque, int irq, int level)
 150 {
 151     Sun4c_INTCTLState *s = opaque;
 152     uint32_t mask = 1 << irq;
 153     uint32_t pil = intbit_to_level[irq];
 154
 155     DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
 156             level);
 157     if (pil > 0) {
 158         if (level) {
 159 #ifdef DEBUG_IRQ_COUNT
 160             s->irq_count[pil]++;
 161 #endif
 162             s->pending |= mask;
 163         } else {
 164             s->pending &= ~mask;
 165         }
 166         sun4c_check_interrupts(s);
 167     }
 168 }
 169
 170 static void sun4c_intctl_save(QEMUFile *f, void *opaque)
 171 {
 172     Sun4c_INTCTLState *s = opaque;
 173
 174     qemu_put_8s(f, &s->reg);
 175     qemu_put_8s(f, &s->pending);
 176 }
 177
 178 static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
 179 {
 180     Sun4c_INTCTLState *s = opaque;
 181
 182     if (version_id != 1)
 183         return -EINVAL;
 184
 185     qemu_get_8s(f, &s->reg);
 186     qemu_get_8s(f, &s->pending);
 187     sun4c_check_interrupts(s);
 188
 189     return 0;
 190 }
 191
 192 static void sun4c_intctl_reset(void *opaque)
 193 {
 194     Sun4c_INTCTLState *s = opaque;
 195
 196     s->reg = 1;
 197     s->pending = 0;
 198     sun4c_check_interrupts(s);
 199 }
 200
 201 void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
 202                         qemu_irq *parent_irq)
 203 {
 204     int sun4c_intctl_io_memory;
 205     Sun4c_INTCTLState *s;
 206
 207     s = qemu_mallocz(sizeof(Sun4c_INTCTLState));
 208     if (!s)
 209         return NULL;
 210
 211     sun4c_intctl_io_memory = cpu_register_io_memory(0, sun4c_intctl_mem_read,
 212                                                     sun4c_intctl_mem_write, s);
 213     cpu_register_physical_memory(addr, INTCTL_SIZE, sun4c_intctl_io_memory);
 214     s->cpu_irqs = parent_irq;
 215
 216     register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,
 217                     sun4c_intctl_load, s);
 218
 219     qemu_register_reset(sun4c_intctl_reset, s);
 220     *irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);
 221
 222     sun4c_intctl_reset(s);
 223     return s;
 224 }
 225