gdbstub.c

   1 /*
   2  * gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #ifdef CONFIG_USER_ONLY
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <stdarg.h>
  25 #include <string.h>
  26 #include <errno.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "qemu.h"
  31 #else
  32 #include "qemu-common.h"
  33 #include "qemu-char.h"
  34 #include "sysemu.h"
  35 #include "gdbstub.h"
  36 #include "qemu-kvm.h"
  37 #endif
  38
  39 #include "qemu_socket.h"
  40 #ifdef _WIN32
  41 /* XXX: these constants may be independent of the host ones even for Unix */
  42 #ifndef SIGTRAP
  43 #define SIGTRAP 5
  44 #endif
  45 #ifndef SIGINT
  46 #define SIGINT 2
  47 #endif
  48 #else
  49 #include <signal.h>
  50 #endif
  51
  52 //#define DEBUG_GDB
  53
  54 enum RSState {
  55     RS_IDLE,
  56     RS_GETLINE,
  57     RS_CHKSUM1,
  58     RS_CHKSUM2,
  59     RS_SYSCALL,
  60 };
  61 typedef struct GDBState {
  62     CPUState *env; /* current CPU */
  63     enum RSState state; /* parsing state */
  64     char line_buf[4096];
  65     int line_buf_index;
  66     int line_csum;
  67     uint8_t last_packet[4100];
  68     int last_packet_len;
  69     int signal;
  70 #ifdef CONFIG_USER_ONLY
  71     int fd;
  72     int running_state;
  73 #else
  74     CharDriverState *chr;
  75 #endif
  76 } GDBState;
  77
  78 /* By default use no IRQs and no timers while single stepping so as to
  79  * make single stepping like an ICE HW step.
  80  */
  81 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
  82
  83 #ifdef CONFIG_USER_ONLY
  84 /* XXX: This is not thread safe.  Do we care?  */
  85 static int gdbserver_fd = -1;
  86
  87 /* XXX: remove this hack.  */
  88 static GDBState gdbserver_state;
  89
  90 static int get_char(GDBState *s)
  91 {
  92     uint8_t ch;
  93     int ret;
  94
  95     for(;;) {
  96         ret = recv(s->fd, &ch, 1, 0);
  97         if (ret < 0) {
  98             if (errno == ECONNRESET)
  99                 s->fd = -1;
 100             if (errno != EINTR && errno != EAGAIN)
 101                 return -1;
 102         } else if (ret == 0) {
 103             close(s->fd);
 104             s->fd = -1;
 105             return -1;
 106         } else {
 107             break;
 108         }
 109     }
 110     return ch;
 111 }
 112 #endif
 113
 114 /* GDB stub state for use by semihosting syscalls.  */
 115 static GDBState *gdb_syscall_state;
 116 static gdb_syscall_complete_cb gdb_current_syscall_cb;
 117
 118 enum {
 119     GDB_SYS_UNKNOWN,
 120     GDB_SYS_ENABLED,
 121     GDB_SYS_DISABLED,
 122 } gdb_syscall_mode;
 123
 124 /* If gdb is connected when the first semihosting syscall occurs then use
 125    remote gdb syscalls.  Otherwise use native file IO.  */
 126 int use_gdb_syscalls(void)
 127 {
 128     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
 129         gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
 130                                               : GDB_SYS_DISABLED);
 131     }
 132     return gdb_syscall_mode == GDB_SYS_ENABLED;
 133 }
 134
 135 /* Resume execution.  */
 136 static inline void gdb_continue(GDBState *s)
 137 {
 138 #ifdef CONFIG_USER_ONLY
 139     s->running_state = 1;
 140 #else
 141     vm_start();
 142 #endif
 143 }
 144
 145 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
 146 {
 147 #ifdef CONFIG_USER_ONLY
 148     int ret;
 149
 150     while (len > 0) {
 151         ret = send(s->fd, buf, len, 0);
 152         if (ret < 0) {
 153             if (errno != EINTR && errno != EAGAIN)
 154                 return;
 155         } else {
 156             buf += ret;
 157             len -= ret;
 158         }
 159     }
 160 #else
 161     qemu_chr_write(s->chr, buf, len);
 162 #endif
 163 }
 164
 165 static inline int fromhex(int v)
 166 {
 167     if (v >= '0' && v <= '9')
 168         return v - '0';
 169     else if (v >= 'A' && v <= 'F')
 170         return v - 'A' + 10;
 171     else if (v >= 'a' && v <= 'f')
 172         return v - 'a' + 10;
 173     else
 174         return 0;
 175 }
 176
 177 static inline int tohex(int v)
 178 {
 179     if (v < 10)
 180         return v + '0';
 181     else
 182         return v - 10 + 'a';
 183 }
 184
 185 static void memtohex(char *buf, const uint8_t *mem, int len)
 186 {
 187     int i, c;
 188     char *q;
 189     q = buf;
 190     for(i = 0; i < len; i++) {
 191         c = mem[i];
 192         *q++ = tohex(c >> 4);
 193         *q++ = tohex(c & 0xf);
 194     }
 195     *q = '\0';
 196 }
 197
 198 static void hextomem(uint8_t *mem, const char *buf, int len)
 199 {
 200     int i;
 201
 202     for(i = 0; i < len; i++) {
 203         mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
 204         buf += 2;
 205     }
 206 }
 207
 208 /* return -1 if error, 0 if OK */
 209 static int put_packet(GDBState *s, char *buf)
 210 {
 211     int len, csum, i;
 212     uint8_t *p;
 213
 214 #ifdef DEBUG_GDB
 215     printf("reply='%s'\n", buf);
 216 #endif
 217
 218     for(;;) {
 219         p = s->last_packet;
 220         *(p++) = '$';
 221         len = strlen(buf);
 222         memcpy(p, buf, len);
 223         p += len;
 224         csum = 0;
 225         for(i = 0; i < len; i++) {
 226             csum += buf[i];
 227         }
 228         *(p++) = '#';
 229         *(p++) = tohex((csum >> 4) & 0xf);
 230         *(p++) = tohex((csum) & 0xf);
 231
 232         s->last_packet_len = p - s->last_packet;
 233         put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
 234
 235 #ifdef CONFIG_USER_ONLY
 236         i = get_char(s);
 237         if (i < 0)
 238             return -1;
 239         if (i == '+')
 240             break;
 241 #else
 242         break;
 243 #endif
 244     }
 245     return 0;
 246 }
 247
 248 #if defined(TARGET_I386)
 249
 250 #ifdef TARGET_X86_64
 251 static const uint8_t gdb_x86_64_regs[16] = {
 252     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
 253     8, 9, 10, 11, 12, 13, 14, 15,
 254 };
 255 #endif
 256
 257 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 258 {
 259     int i, fpus, nb_regs;
 260     uint8_t *p;
 261
 262     p = mem_buf;
 263 #ifdef TARGET_X86_64
 264     if (env->hflags & HF_CS64_MASK) {
 265         nb_regs = 16;
 266         for(i = 0; i < 16; i++) {
 267             *(uint64_t *)p = tswap64(env->regs[gdb_x86_64_regs[i]]);
 268             p += 8;
 269         }
 270         *(uint64_t *)p = tswap64(env->eip);
 271         p += 8;
 272     } else
 273 #endif
 274     {
 275         nb_regs = 8;
 276         for(i = 0; i < 8; i++) {
 277             *(uint32_t *)p = tswap32(env->regs[i]);
 278             p += 4;
 279         }
 280         *(uint32_t *)p = tswap32(env->eip);
 281         p += 4;
 282     }
 283
 284     *(uint32_t *)p = tswap32(env->eflags);
 285     p += 4;
 286     *(uint32_t *)p = tswap32(env->segs[R_CS].selector);
 287     p += 4;
 288     *(uint32_t *)p = tswap32(env->segs[R_SS].selector);
 289     p += 4;
 290     *(uint32_t *)p = tswap32(env->segs[R_DS].selector);
 291     p += 4;
 292     *(uint32_t *)p = tswap32(env->segs[R_ES].selector);
 293     p += 4;
 294     *(uint32_t *)p = tswap32(env->segs[R_FS].selector);
 295     p += 4;
 296     *(uint32_t *)p = tswap32(env->segs[R_GS].selector);
 297     p += 4;
 298     for(i = 0; i < 8; i++) {
 299         /* XXX: convert floats */
 300 #ifdef USE_X86LDOUBLE
 301         memcpy(p, &env->fpregs[i], 10);
 302 #else
 303         memset(p, 0, 10);
 304 #endif
 305         p += 10;
 306     }
 307     *(uint32_t *)p = tswap32(env->fpuc); /* fctrl */
 308     p += 4;
 309     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 310     *(uint32_t *)p = tswap32(fpus); /* fstat */
 311     p += 4;
 312     *(uint32_t *)p = 0; /* ftag */
 313     p += 4;
 314     *(uint32_t *)p = 0; /* fiseg */
 315     p += 4;
 316     *(uint32_t *)p = 0; /* fioff */
 317     p += 4;
 318     *(uint32_t *)p = 0; /* foseg */
 319     p += 4;
 320     *(uint32_t *)p = 0; /* fooff */
 321     p += 4;
 322     *(uint32_t *)p = 0; /* fop */
 323     p += 4;
 324     for(i = 0; i < nb_regs; i++) {
 325         *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(0));
 326         p += 8;
 327         *(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(1));
 328         p += 8;
 329     }
 330     *(uint32_t *)p = tswap32(env->mxcsr);
 331     p += 4;
 332     return p - mem_buf;
 333 }
 334
 335 static inline void cpu_gdb_load_seg(CPUState *env, const uint8_t **pp,
 336                                     int sreg)
 337 {
 338     const uint8_t *p;
 339     uint32_t sel;
 340     p = *pp;
 341     sel = tswap32(*(uint32_t *)p);
 342     p += 4;
 343     if (sel != env->segs[sreg].selector) {
 344 #if defined(CONFIG_USER_ONLY)
 345         cpu_x86_load_seg(env, sreg, sel);
 346 #else
 347         /* XXX: do it with a debug function which does not raise an
 348            exception */
 349 #endif
 350     }
 351     *pp = p;
 352 }
 353
 354 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 355 {
 356     const uint8_t *p = mem_buf;
 357     int i, nb_regs;
 358     uint16_t fpus;
 359
 360 #ifdef TARGET_X86_64
 361     if (env->hflags & HF_CS64_MASK) {
 362         nb_regs = 16;
 363         for(i = 0; i < 16; i++) {
 364             env->regs[gdb_x86_64_regs[i]] = tswap64(*(uint64_t *)p);
 365             p += 8;
 366         }
 367         env->eip = tswap64(*(uint64_t *)p);
 368         p += 8;
 369     } else
 370 #endif
 371     {
 372         nb_regs = 8;
 373         for(i = 0; i < 8; i++) {
 374             env->regs[i] = tswap32(*(uint32_t *)p);
 375             p += 4;
 376         }
 377         env->eip = tswap32(*(uint32_t *)p);
 378         p += 4;
 379     }
 380     env->eflags = tswap32(*(uint32_t *)p);
 381     p += 4;
 382     cpu_gdb_load_seg(env, &p, R_CS);
 383     cpu_gdb_load_seg(env, &p, R_SS);
 384     cpu_gdb_load_seg(env, &p, R_DS);
 385     cpu_gdb_load_seg(env, &p, R_ES);
 386     cpu_gdb_load_seg(env, &p, R_FS);
 387     cpu_gdb_load_seg(env, &p, R_GS);
 388
 389     /* FPU state */
 390     for(i = 0; i < 8; i++) {
 391         /* XXX: convert floats */
 392 #ifdef USE_X86LDOUBLE
 393         memcpy(&env->fpregs[i], p, 10);
 394 #endif
 395         p += 10;
 396     }
 397     env->fpuc = tswap32(*(uint32_t *)p); /* fctrl */
 398     p += 4;
 399     fpus = tswap32(*(uint32_t *)p);
 400     p += 4;
 401     env->fpstt = (fpus >> 11) & 7;
 402     env->fpus = fpus & ~0x3800;
 403     p += 4 * 6;
 404
 405     if (size >= ((p - mem_buf) + 16 * nb_regs + 4)) {
 406         /* SSE state */
 407         for(i = 0; i < nb_regs; i++) {
 408             env->xmm_regs[i].XMM_Q(0) = tswap64(*(uint64_t *)p);
 409             p += 8;
 410             env->xmm_regs[i].XMM_Q(1) = tswap64(*(uint64_t *)p);
 411             p += 8;
 412         }
 413         env->mxcsr = tswap32(*(uint32_t *)p);
 414         p += 4;
 415     }
 416 }
 417
 418 #elif defined (TARGET_PPC)
 419 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 420 {
 421     uint32_t *registers = (uint32_t *)mem_buf, tmp;
 422     int i;
 423
 424     /* fill in gprs */
 425     for(i = 0; i < 32; i++) {
 426         registers[i] = tswapl(env->gpr[i]);
 427     }
 428     /* fill in fprs */
 429     for (i = 0; i < 32; i++) {
 430         registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
 431         registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
 432     }
 433     /* nip, msr, ccr, lnk, ctr, xer, mq */
 434     registers[96] = tswapl(env->nip);
 435     registers[97] = tswapl(env->msr);
 436     tmp = 0;
 437     for (i = 0; i < 8; i++)
 438         tmp |= env->crf[i] << (32 - ((i + 1) * 4));
 439     registers[98] = tswapl(tmp);
 440     registers[99] = tswapl(env->lr);
 441     registers[100] = tswapl(env->ctr);
 442     registers[101] = tswapl(ppc_load_xer(env));
 443     registers[102] = 0;
 444
 445     return 103 * 4;
 446 }
 447
 448 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 449 {
 450     uint32_t *registers = (uint32_t *)mem_buf;
 451     int i;
 452
 453     /* fill in gprs */
 454     for (i = 0; i < 32; i++) {
 455         env->gpr[i] = tswapl(registers[i]);
 456     }
 457     /* fill in fprs */
 458     for (i = 0; i < 32; i++) {
 459         *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
 460         *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
 461     }
 462     /* nip, msr, ccr, lnk, ctr, xer, mq */
 463     env->nip = tswapl(registers[96]);
 464     ppc_store_msr(env, tswapl(registers[97]));
 465     registers[98] = tswapl(registers[98]);
 466     for (i = 0; i < 8; i++)
 467         env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
 468     env->lr = tswapl(registers[99]);
 469     env->ctr = tswapl(registers[100]);
 470     ppc_store_xer(env, tswapl(registers[101]));
 471 }
 472 #elif defined (TARGET_SPARC)
 473 #ifdef TARGET_ABI32
 474 #define tswap_abi(val) tswap32(val &0xffffffff)
 475 #else
 476 #define tswap_abi(val) tswapl(val)
 477 #endif
 478 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 479 {
 480 #ifdef TARGET_ABI32
 481     abi_ulong *registers = (abi_ulong *)mem_buf;
 482 #else
 483     target_ulong *registers = (target_ulong *)mem_buf;
 484 #endif
 485     int i;
 486
 487     /* fill in g0..g7 */
 488     for(i = 0; i < 8; i++) {
 489         registers[i] = tswap_abi(env->gregs[i]);
 490     }
 491     /* fill in register window */
 492     for(i = 0; i < 24; i++) {
 493         registers[i + 8] = tswap_abi(env->regwptr[i]);
 494     }
 495 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 496     /* fill in fprs */
 497     for (i = 0; i < 32; i++) {
 498         registers[i + 32] = tswap_abi(*((uint32_t *)&env->fpr[i]));
 499     }
 500     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 501     registers[64] = tswap_abi(env->y);
 502     {
 503         uint32_t tmp;
 504
 505         tmp = GET_PSR(env);
 506         registers[65] = tswap32(tmp);
 507     }
 508     registers[66] = tswap_abi(env->wim);
 509     registers[67] = tswap_abi(env->tbr);
 510     registers[68] = tswap_abi(env->pc);
 511     registers[69] = tswap_abi(env->npc);
 512     registers[70] = tswap_abi(env->fsr);
 513     registers[71] = 0; /* csr */
 514     registers[72] = 0;
 515     return 73 * sizeof(uint32_t);
 516 #else
 517     /* fill in fprs */
 518     for (i = 0; i < 64; i += 2) {
 519         uint64_t tmp;
 520
 521         tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
 522         tmp |= *(uint32_t *)&env->fpr[i + 1];
 523         registers[i / 2 + 32] = tswap64(tmp);
 524     }
 525     registers[64] = tswapl(env->pc);
 526     registers[65] = tswapl(env->npc);
 527     registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
 528                            ((env->asi & 0xff) << 24) |
 529                            ((env->pstate & 0xfff) << 8) |
 530                            GET_CWP64(env));
 531     registers[67] = tswapl(env->fsr);
 532     registers[68] = tswapl(env->fprs);
 533     registers[69] = tswapl(env->y);
 534     return 70 * sizeof(target_ulong);
 535 #endif
 536 }
 537
 538 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 539 {
 540 #ifdef TARGET_ABI32
 541     abi_ulong *registers = (abi_ulong *)mem_buf;
 542 #else
 543     target_ulong *registers = (target_ulong *)mem_buf;
 544 #endif
 545     int i;
 546
 547     /* fill in g0..g7 */
 548     for(i = 0; i < 7; i++) {
 549         env->gregs[i] = tswap_abi(registers[i]);
 550     }
 551     /* fill in register window */
 552     for(i = 0; i < 24; i++) {
 553         env->regwptr[i] = tswap_abi(registers[i + 8]);
 554     }
 555 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 556     /* fill in fprs */
 557     for (i = 0; i < 32; i++) {
 558         *((uint32_t *)&env->fpr[i]) = tswap_abi(registers[i + 32]);
 559     }
 560     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 561     env->y = tswap_abi(registers[64]);
 562     PUT_PSR(env, tswap_abi(registers[65]));
 563     env->wim = tswap_abi(registers[66]);
 564     env->tbr = tswap_abi(registers[67]);
 565     env->pc = tswap_abi(registers[68]);
 566     env->npc = tswap_abi(registers[69]);
 567     env->fsr = tswap_abi(registers[70]);
 568 #else
 569     for (i = 0; i < 64; i += 2) {
 570         uint64_t tmp;
 571
 572         tmp = tswap64(registers[i / 2 + 32]);
 573         *((uint32_t *)&env->fpr[i]) = tmp >> 32;
 574         *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
 575     }
 576     env->pc = tswapl(registers[64]);
 577     env->npc = tswapl(registers[65]);
 578     {
 579         uint64_t tmp = tswapl(registers[66]);
 580
 581         PUT_CCR(env, tmp >> 32);
 582         env->asi = (tmp >> 24) & 0xff;
 583         env->pstate = (tmp >> 8) & 0xfff;
 584         PUT_CWP64(env, tmp & 0xff);
 585     }
 586     env->fsr = tswapl(registers[67]);
 587     env->fprs = tswapl(registers[68]);
 588     env->y = tswapl(registers[69]);
 589 #endif
 590 }
 591 #undef tswap_abi
 592 #elif defined (TARGET_ARM)
 593 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 594 {
 595     int i;
 596     uint8_t *ptr;
 597
 598     ptr = mem_buf;
 599     /* 16 core integer registers (4 bytes each).  */
 600     for (i = 0; i < 16; i++)
 601       {
 602         *(uint32_t *)ptr = tswapl(env->regs[i]);
 603         ptr += 4;
 604       }
 605     /* 8 FPA registers (12 bytes each), FPS (4 bytes).
 606        Not yet implemented.  */
 607     memset (ptr, 0, 8 * 12 + 4);
 608     ptr += 8 * 12 + 4;
 609     /* CPSR (4 bytes).  */
 610     *(uint32_t *)ptr = tswapl (cpsr_read(env));
 611     ptr += 4;
 612
 613     return ptr - mem_buf;
 614 }
 615
 616 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 617 {
 618     int i;
 619     uint8_t *ptr;
 620
 621     ptr = mem_buf;
 622     /* Core integer registers.  */
 623     for (i = 0; i < 16; i++)
 624       {
 625         env->regs[i] = tswapl(*(uint32_t *)ptr);
 626         ptr += 4;
 627       }
 628     /* Ignore FPA regs and scr.  */
 629     ptr += 8 * 12 + 4;
 630     cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
 631 }
 632 #elif defined (TARGET_M68K)
 633 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 634 {
 635     int i;
 636     uint8_t *ptr;
 637     CPU_DoubleU u;
 638
 639     ptr = mem_buf;
 640     /* D0-D7 */
 641     for (i = 0; i < 8; i++) {
 642         *(uint32_t *)ptr = tswapl(env->dregs[i]);
 643         ptr += 4;
 644     }
 645     /* A0-A7 */
 646     for (i = 0; i < 8; i++) {
 647         *(uint32_t *)ptr = tswapl(env->aregs[i]);
 648         ptr += 4;
 649     }
 650     *(uint32_t *)ptr = tswapl(env->sr);
 651     ptr += 4;
 652     *(uint32_t *)ptr = tswapl(env->pc);
 653     ptr += 4;
 654     /* F0-F7.  The 68881/68040 have 12-bit extended precision registers.
 655        ColdFire has 8-bit double precision registers.  */
 656     for (i = 0; i < 8; i++) {
 657         u.d = env->fregs[i];
 658         *(uint32_t *)ptr = tswap32(u.l.upper);
 659         *(uint32_t *)ptr = tswap32(u.l.lower);
 660     }
 661     /* FP control regs (not implemented).  */
 662     memset (ptr, 0, 3 * 4);
 663     ptr += 3 * 4;
 664
 665     return ptr - mem_buf;
 666 }
 667
 668 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 669 {
 670     int i;
 671     uint8_t *ptr;
 672     CPU_DoubleU u;
 673
 674     ptr = mem_buf;
 675     /* D0-D7 */
 676     for (i = 0; i < 8; i++) {
 677         env->dregs[i] = tswapl(*(uint32_t *)ptr);
 678         ptr += 4;
 679     }
 680     /* A0-A7 */
 681     for (i = 0; i < 8; i++) {
 682         env->aregs[i] = tswapl(*(uint32_t *)ptr);
 683         ptr += 4;
 684     }
 685     env->sr = tswapl(*(uint32_t *)ptr);
 686     ptr += 4;
 687     env->pc = tswapl(*(uint32_t *)ptr);
 688     ptr += 4;
 689     /* F0-F7.  The 68881/68040 have 12-bit extended precision registers.
 690        ColdFire has 8-bit double precision registers.  */
 691     for (i = 0; i < 8; i++) {
 692         u.l.upper = tswap32(*(uint32_t *)ptr);
 693         u.l.lower = tswap32(*(uint32_t *)ptr);
 694         env->fregs[i] = u.d;
 695     }
 696     /* FP control regs (not implemented).  */
 697     ptr += 3 * 4;
 698 }
 699 #elif defined (TARGET_MIPS)
 700 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 701 {
 702     int i;
 703     uint8_t *ptr;
 704
 705     ptr = mem_buf;
 706     for (i = 0; i < 32; i++)
 707       {
 708         *(target_ulong *)ptr = tswapl(env->active_tc.gpr[i]);
 709         ptr += sizeof(target_ulong);
 710       }
 711
 712     *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
 713     ptr += sizeof(target_ulong);
 714
 715     *(target_ulong *)ptr = tswapl(env->active_tc.LO[0]);
 716     ptr += sizeof(target_ulong);
 717
 718     *(target_ulong *)ptr = tswapl(env->active_tc.HI[0]);
 719     ptr += sizeof(target_ulong);
 720
 721     *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
 722     ptr += sizeof(target_ulong);
 723
 724     *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
 725     ptr += sizeof(target_ulong);
 726
 727     *(target_ulong *)ptr = tswapl(env->active_tc.PC);
 728     ptr += sizeof(target_ulong);
 729
 730     if (env->CP0_Config1 & (1 << CP0C1_FP))
 731       {
 732         for (i = 0; i < 32; i++)
 733           {
 734             if (env->CP0_Status & (1 << CP0St_FR))
 735               *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
 736             else
 737               *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
 738             ptr += sizeof(target_ulong);
 739           }
 740
 741         *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
 742         ptr += sizeof(target_ulong);
 743
 744         *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
 745         ptr += sizeof(target_ulong);
 746       }
 747
 748     /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
 749     *(target_ulong *)ptr = 0;
 750     ptr += sizeof(target_ulong);
 751
 752     /* Registers for embedded use, we just pad them. */
 753     for (i = 0; i < 16; i++)
 754       {
 755         *(target_ulong *)ptr = 0;
 756         ptr += sizeof(target_ulong);
 757       }
 758
 759     /* Processor ID. */
 760     *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
 761     ptr += sizeof(target_ulong);
 762
 763     return ptr - mem_buf;
 764 }
 765
 766 /* convert MIPS rounding mode in FCR31 to IEEE library */
 767 static unsigned int ieee_rm[] =
 768   {
 769     float_round_nearest_even,
 770     float_round_to_zero,
 771     float_round_up,
 772     float_round_down
 773   };
 774 #define RESTORE_ROUNDING_MODE \
 775     set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
 776
 777 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 778 {
 779     int i;
 780     uint8_t *ptr;
 781
 782     ptr = mem_buf;
 783     for (i = 0; i < 32; i++)
 784       {
 785         env->active_tc.gpr[i] = tswapl(*(target_ulong *)ptr);
 786         ptr += sizeof(target_ulong);
 787       }
 788
 789     env->CP0_Status = tswapl(*(target_ulong *)ptr);
 790     ptr += sizeof(target_ulong);
 791
 792     env->active_tc.LO[0] = tswapl(*(target_ulong *)ptr);
 793     ptr += sizeof(target_ulong);
 794
 795     env->active_tc.HI[0] = tswapl(*(target_ulong *)ptr);
 796     ptr += sizeof(target_ulong);
 797
 798     env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
 799     ptr += sizeof(target_ulong);
 800
 801     env->CP0_Cause = tswapl(*(target_ulong *)ptr);
 802     ptr += sizeof(target_ulong);
 803
 804     env->active_tc.PC = tswapl(*(target_ulong *)ptr);
 805     ptr += sizeof(target_ulong);
 806
 807     if (env->CP0_Config1 & (1 << CP0C1_FP))
 808       {
 809         for (i = 0; i < 32; i++)
 810           {
 811             if (env->CP0_Status & (1 << CP0St_FR))
 812               env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
 813             else
 814               env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
 815             ptr += sizeof(target_ulong);
 816           }
 817
 818         env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
 819         ptr += sizeof(target_ulong);
 820
 821         /* The remaining registers are assumed to be read-only. */
 822
 823         /* set rounding mode */
 824         RESTORE_ROUNDING_MODE;
 825
 826 #ifndef CONFIG_SOFTFLOAT
 827         /* no floating point exception for native float */
 828         SET_FP_ENABLE(env->fcr31, 0);
 829 #endif
 830       }
 831 }
 832 #elif defined (TARGET_SH4)
 833
 834 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
 835
 836 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 837 {
 838   uint32_t *ptr = (uint32_t *)mem_buf;
 839   int i;
 840
 841 #define SAVE(x) *ptr++=tswapl(x)
 842   if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
 843       for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
 844   } else {
 845       for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
 846   }
 847   for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
 848   SAVE (env->pc);
 849   SAVE (env->pr);
 850   SAVE (env->gbr);
 851   SAVE (env->vbr);
 852   SAVE (env->mach);
 853   SAVE (env->macl);
 854   SAVE (env->sr);
 855   SAVE (env->fpul);
 856   SAVE (env->fpscr);
 857   for (i = 0; i < 16; i++)
 858       SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
 859   SAVE (env->ssr);
 860   SAVE (env->spc);
 861   for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
 862   for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
 863   return ((uint8_t *)ptr - mem_buf);
 864 }
 865
 866 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 867 {
 868   uint32_t *ptr = (uint32_t *)mem_buf;
 869   int i;
 870
 871 #define LOAD(x) (x)=*ptr++;
 872   if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
 873       for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
 874   } else {
 875       for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
 876   }
 877   for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
 878   LOAD (env->pc);
 879   LOAD (env->pr);
 880   LOAD (env->gbr);
 881   LOAD (env->vbr);
 882   LOAD (env->mach);
 883   LOAD (env->macl);
 884   LOAD (env->sr);
 885   LOAD (env->fpul);
 886   LOAD (env->fpscr);
 887   for (i = 0; i < 16; i++)
 888       LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
 889   LOAD (env->ssr);
 890   LOAD (env->spc);
 891   for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
 892   for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
 893 }
 894 #elif defined (TARGET_CRIS)
 895
 896 static int cris_save_32 (unsigned char *d, uint32_t value)
 897 {
 898         *d++ = (value);
 899         *d++ = (value >>= 8);
 900         *d++ = (value >>= 8);
 901         *d++ = (value >>= 8);
 902         return 4;
 903 }
 904 static int cris_save_16 (unsigned char *d, uint32_t value)
 905 {
 906         *d++ = (value);
 907         *d++ = (value >>= 8);
 908         return 2;
 909 }
 910 static int cris_save_8 (unsigned char *d, uint32_t value)
 911 {
 912         *d++ = (value);
 913         return 1;
 914 }
 915
 916 /* FIXME: this will bug on archs not supporting unaligned word accesses.  */
 917 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 918 {
 919   uint8_t *ptr = mem_buf;
 920   uint8_t srs;
 921   int i;
 922
 923   for (i = 0; i < 16; i++)
 924           ptr += cris_save_32 (ptr, env->regs[i]);
 925
 926   srs = env->pregs[PR_SRS];
 927
 928   ptr += cris_save_8 (ptr, env->pregs[0]);
 929   ptr += cris_save_8 (ptr, env->pregs[1]);
 930   ptr += cris_save_32 (ptr, env->pregs[2]);
 931   ptr += cris_save_8 (ptr, srs);
 932   ptr += cris_save_16 (ptr, env->pregs[4]);
 933
 934   for (i = 5; i < 16; i++)
 935           ptr += cris_save_32 (ptr, env->pregs[i]);
 936
 937   ptr += cris_save_32 (ptr, env->pc);
 938
 939   for (i = 0; i < 16; i++)
 940           ptr += cris_save_32 (ptr, env->sregs[srs][i]);
 941
 942   return ((uint8_t *)ptr - mem_buf);
 943 }
 944
 945 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 946 {
 947   uint32_t *ptr = (uint32_t *)mem_buf;
 948   int i;
 949
 950 #define LOAD(x) (x)=*ptr++;
 951   for (i = 0; i < 16; i++) LOAD(env->regs[i]);
 952   LOAD (env->pc);
 953 }
 954 #else
 955 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
 956 {
 957     return 0;
 958 }
 959
 960 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
 961 {
 962 }
 963
 964 #endif
 965
 966 static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
 967 {
 968     const char *p;
 969     int ch, reg_size, type;
 970     char buf[4096];
 971     uint8_t mem_buf[4096];
 972     uint32_t *registers;
 973     target_ulong addr, len;
 974
 975 #ifdef DEBUG_GDB
 976     printf("command='%s'\n", line_buf);
 977 #endif
 978     p = line_buf;
 979     ch = *p++;
 980     switch(ch) {
 981     case '?':
 982         /* TODO: Make this return the correct value for user-mode.  */
 983         snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
 984         put_packet(s, buf);
 985         /* Remove all the breakpoints when this query is issued,
 986          * because gdb is doing and initial connect and the state
 987          * should be cleaned up.
 988          */
 989         cpu_breakpoint_remove_all(env);
 990         cpu_watchpoint_remove_all(env);
 991         break;
 992     case 'c':
 993         if (*p != '\0') {
 994             addr = strtoull(p, (char **)&p, 16);
 995 #if defined(TARGET_I386)
 996             env->eip = addr;
 997             kvm_load_registers(env);
 998 #elif defined (TARGET_PPC)
 999             env->nip = addr;
1000             kvm_load_registers(env);
1001 #elif defined (TARGET_SPARC)
1002             env->pc = addr;
1003             env->npc = addr + 4;
1004 #elif defined (TARGET_ARM)
1005             env->regs[15] = addr;
1006 #elif defined (TARGET_SH4)
1007             env->pc = addr;
1008 #elif defined (TARGET_MIPS)
1009             env->active_tc.PC = addr;
1010 #elif defined (TARGET_CRIS)
1011             env->pc = addr;
1012 #endif
1013         }
1014         gdb_continue(s);
1015         return RS_IDLE;
1016     case 'C':
1017         s->signal = strtoul(p, (char **)&p, 16);
1018         gdb_continue(s);
1019         return RS_IDLE;
1020     case 'k':
1021         /* Kill the target */
1022         fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1023         exit(0);
1024     case 'D':
1025         /* Detach packet */
1026         cpu_breakpoint_remove_all(env);
1027         cpu_watchpoint_remove_all(env);
1028         gdb_continue(s);
1029         put_packet(s, "OK");
1030         break;
1031     case 's':
1032         if (*p != '\0') {
1033             addr = strtoull(p, (char **)&p, 16);
1034 #if defined(TARGET_I386)
1035             env->eip = addr;
1036             kvm_load_registers(env);
1037 #elif defined (TARGET_PPC)
1038             env->nip = addr;
1039             kvm_load_registers(env);
1040 #elif defined (TARGET_SPARC)
1041             env->pc = addr;
1042             env->npc = addr + 4;
1043 #elif defined (TARGET_ARM)
1044             env->regs[15] = addr;
1045 #elif defined (TARGET_SH4)
1046             env->pc = addr;
1047 #elif defined (TARGET_MIPS)
1048             env->active_tc.PC = addr;
1049 #elif defined (TARGET_CRIS)
1050             env->pc = addr;
1051 #endif
1052         }
1053         cpu_single_step(env, sstep_flags);
1054         gdb_continue(s);
1055         return RS_IDLE;
1056     case 'F':
1057         {
1058             target_ulong ret;
1059             target_ulong err;
1060
1061             ret = strtoull(p, (char **)&p, 16);
1062             if (*p == ',') {
1063                 p++;
1064                 err = strtoull(p, (char **)&p, 16);
1065             } else {
1066                 err = 0;
1067             }
1068             if (*p == ',')
1069                 p++;
1070             type = *p;
1071             if (gdb_current_syscall_cb)
1072                 gdb_current_syscall_cb(s->env, ret, err);
1073             if (type == 'C') {
1074                 put_packet(s, "T02");
1075             } else {
1076                 gdb_continue(s);
1077             }
1078         }
1079         break;
1080     case 'g':
1081         kvm_save_registers(env);
1082         reg_size = cpu_gdb_read_registers(env, mem_buf);
1083         memtohex(buf, mem_buf, reg_size);
1084         put_packet(s, buf);
1085         break;
1086     case 'G':
1087         registers = (void *)mem_buf;
1088         len = strlen(p) / 2;
1089         hextomem((uint8_t *)registers, p, len);
1090         cpu_gdb_write_registers(env, mem_buf, len);
1091         kvm_load_registers(env);
1092         put_packet(s, "OK");
1093         break;
1094     case 'm':
1095         addr = strtoull(p, (char **)&p, 16);
1096         if (*p == ',')
1097             p++;
1098         len = strtoull(p, NULL, 16);
1099         if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
1100             put_packet (s, "E14");
1101         } else {
1102             memtohex(buf, mem_buf, len);
1103             put_packet(s, buf);
1104         }
1105         break;
1106     case 'M':
1107         addr = strtoull(p, (char **)&p, 16);
1108         if (*p == ',')
1109             p++;
1110         len = strtoull(p, (char **)&p, 16);
1111         if (*p == ':')
1112             p++;
1113         hextomem(mem_buf, p, len);
1114         if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
1115             put_packet(s, "E14");
1116         else
1117             put_packet(s, "OK");
1118         break;
1119     case 'Z':
1120         type = strtoul(p, (char **)&p, 16);
1121         if (*p == ',')
1122             p++;
1123         addr = strtoull(p, (char **)&p, 16);
1124         if (*p == ',')
1125             p++;
1126         len = strtoull(p, (char **)&p, 16);
1127         switch (type) {
1128         case 0:
1129         case 1:
1130             if (cpu_breakpoint_insert(env, addr) < 0)
1131                 goto breakpoint_error;
1132             put_packet(s, "OK");
1133             break;
1134 #ifndef CONFIG_USER_ONLY
1135         case 2:
1136             type = PAGE_WRITE;
1137             goto insert_watchpoint;
1138         case 3:
1139             type = PAGE_READ;
1140             goto insert_watchpoint;
1141         case 4:
1142             type = PAGE_READ | PAGE_WRITE;
1143         insert_watchpoint:
1144             if (cpu_watchpoint_insert(env, addr, type) < 0)
1145                 goto breakpoint_error;
1146             put_packet(s, "OK");
1147             break;
1148 #endif
1149         default:
1150             put_packet(s, "");
1151             break;
1152         }
1153         break;
1154     breakpoint_error:
1155         put_packet(s, "E22");
1156         break;
1157
1158     case 'z':
1159         type = strtoul(p, (char **)&p, 16);
1160         if (*p == ',')
1161             p++;
1162         addr = strtoull(p, (char **)&p, 16);
1163         if (*p == ',')
1164             p++;
1165         len = strtoull(p, (char **)&p, 16);
1166         if (type == 0 || type == 1) {
1167             cpu_breakpoint_remove(env, addr);
1168             put_packet(s, "OK");
1169 #ifndef CONFIG_USER_ONLY
1170         } else if (type >= 2 || type <= 4) {
1171             cpu_watchpoint_remove(env, addr);
1172             put_packet(s, "OK");
1173 #endif
1174         } else {
1175             put_packet(s, "");
1176         }
1177         break;
1178     case 'q':
1179     case 'Q':
1180         /* parse any 'q' packets here */
1181         if (!strcmp(p,"qemu.sstepbits")) {
1182             /* Query Breakpoint bit definitions */
1183             sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1184                     SSTEP_ENABLE,
1185                     SSTEP_NOIRQ,
1186                     SSTEP_NOTIMER);
1187             put_packet(s, buf);
1188             break;
1189         } else if (strncmp(p,"qemu.sstep",10) == 0) {
1190             /* Display or change the sstep_flags */
1191             p += 10;
1192             if (*p != '=') {
1193                 /* Display current setting */
1194                 sprintf(buf,"0x%x", sstep_flags);
1195                 put_packet(s, buf);
1196                 break;
1197             }
1198             p++;
1199             type = strtoul(p, (char **)&p, 16);
1200             sstep_flags = type;
1201             put_packet(s, "OK");
1202             break;
1203         }
1204 #ifdef CONFIG_LINUX_USER
1205         else if (strncmp(p, "Offsets", 7) == 0) {
1206             TaskState *ts = env->opaque;
1207
1208             sprintf(buf,
1209                     "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1210                     ";Bss=" TARGET_ABI_FMT_lx,
1211                     ts->info->code_offset,
1212                     ts->info->data_offset,
1213                     ts->info->data_offset);
1214             put_packet(s, buf);
1215             break;
1216         }
1217 #endif
1218         /* Fall through.  */
1219     default:
1220         /* put empty packet */
1221         buf[0] = '\0';
1222         put_packet(s, buf);
1223         break;
1224     }
1225     return RS_IDLE;
1226 }
1227
1228 extern void tb_flush(CPUState *env);
1229
1230 #ifndef CONFIG_USER_ONLY
1231 static void gdb_vm_stopped(void *opaque, int reason)
1232 {
1233     GDBState *s = opaque;
1234     char buf[256];
1235     int ret;
1236
1237     if (s->state == RS_SYSCALL)
1238         return;
1239
1240     /* disable single step if it was enable */
1241     cpu_single_step(s->env, 0);
1242
1243     if (reason == EXCP_DEBUG) {
1244         if (s->env->watchpoint_hit) {
1245             snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1246                      SIGTRAP,
1247                      s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1248             put_packet(s, buf);
1249             s->env->watchpoint_hit = 0;
1250             return;
1251         }
1252         tb_flush(s->env);
1253         ret = SIGTRAP;
1254     } else if (reason == EXCP_INTERRUPT) {
1255         ret = SIGINT;
1256     } else {
1257         ret = 0;
1258     }
1259     snprintf(buf, sizeof(buf), "S%02x", ret);
1260     put_packet(s, buf);
1261 }
1262 #endif
1263
1264 /* Send a gdb syscall request.
1265    This accepts limited printf-style format specifiers, specifically:
1266     %x  - target_ulong argument printed in hex.
1267     %lx - 64-bit argument printed in hex.
1268     %s  - string pointer (target_ulong) and length (int) pair.  */
1269 void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
1270 {
1271     va_list va;
1272     char buf[256];
1273     char *p;
1274     target_ulong addr;
1275     uint64_t i64;
1276     GDBState *s;
1277
1278     s = gdb_syscall_state;
1279     if (!s)
1280         return;
1281     gdb_current_syscall_cb = cb;
1282     s->state = RS_SYSCALL;
1283 #ifndef CONFIG_USER_ONLY
1284     vm_stop(EXCP_DEBUG);
1285 #endif
1286     s->state = RS_IDLE;
1287     va_start(va, fmt);
1288     p = buf;
1289     *(p++) = 'F';
1290     while (*fmt) {
1291         if (*fmt == '%') {
1292             fmt++;
1293             switch (*fmt++) {
1294             case 'x':
1295                 addr = va_arg(va, target_ulong);
1296                 p += sprintf(p, TARGET_FMT_lx, addr);
1297                 break;
1298             case 'l':
1299                 if (*(fmt++) != 'x')
1300                     goto bad_format;
1301                 i64 = va_arg(va, uint64_t);
1302                 p += sprintf(p, "%" PRIx64, i64);
1303                 break;
1304             case 's':
1305                 addr = va_arg(va, target_ulong);
1306                 p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
1307                 break;
1308             default:
1309             bad_format:
1310                 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1311                         fmt - 1);
1312                 break;
1313             }
1314         } else {
1315             *(p++) = *(fmt++);
1316         }
1317     }
1318     *p = 0;
1319     va_end(va);
1320     put_packet(s, buf);
1321 #ifdef CONFIG_USER_ONLY
1322     gdb_handlesig(s->env, 0);
1323 #else
1324     cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1325 #endif
1326 }
1327
1328 static void gdb_read_byte(GDBState *s, int ch)
1329 {
1330     CPUState *env = s->env;
1331     int i, csum;
1332     uint8_t reply;
1333
1334 #ifndef CONFIG_USER_ONLY
1335     if (s->last_packet_len) {
1336         /* Waiting for a response to the last packet.  If we see the start
1337            of a new command then abandon the previous response.  */
1338         if (ch == '-') {
1339 #ifdef DEBUG_GDB
1340             printf("Got NACK, retransmitting\n");
1341 #endif
1342             put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
1343         }
1344 #ifdef DEBUG_GDB
1345         else if (ch == '+')
1346             printf("Got ACK\n");
1347         else
1348             printf("Got '%c' when expecting ACK/NACK\n", ch);
1349 #endif
1350         if (ch == '+' || ch == '$')
1351             s->last_packet_len = 0;
1352         if (ch != '$')
1353             return;
1354     }
1355     if (vm_running) {
1356         /* when the CPU is running, we cannot do anything except stop
1357            it when receiving a char */
1358         vm_stop(EXCP_INTERRUPT);
1359     } else
1360 #endif
1361     {
1362         switch(s->state) {
1363         case RS_IDLE:
1364             if (ch == '$') {
1365                 s->line_buf_index = 0;
1366                 s->state = RS_GETLINE;
1367             }
1368             break;
1369         case RS_GETLINE:
1370             if (ch == '#') {
1371             s->state = RS_CHKSUM1;
1372             } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1373                 s->state = RS_IDLE;
1374             } else {
1375             s->line_buf[s->line_buf_index++] = ch;
1376             }
1377             break;
1378         case RS_CHKSUM1:
1379             s->line_buf[s->line_buf_index] = '\0';
1380             s->line_csum = fromhex(ch) << 4;
1381             s->state = RS_CHKSUM2;
1382             break;
1383         case RS_CHKSUM2:
1384             s->line_csum |= fromhex(ch);
1385             csum = 0;
1386             for(i = 0; i < s->line_buf_index; i++) {
1387                 csum += s->line_buf[i];
1388             }
1389             if (s->line_csum != (csum & 0xff)) {
1390                 reply = '-';
1391                 put_buffer(s, &reply, 1);
1392                 s->state = RS_IDLE;
1393             } else {
1394                 reply = '+';
1395                 put_buffer(s, &reply, 1);
1396                 s->state = gdb_handle_packet(s, env, s->line_buf);
1397             }
1398             break;
1399         default:
1400             abort();
1401         }
1402     }
1403 }
1404
1405 #ifdef CONFIG_USER_ONLY
1406 int
1407 gdb_handlesig (CPUState *env, int sig)
1408 {
1409   GDBState *s;
1410   char buf[256];
1411   int n;
1412
1413   s = &gdbserver_state;
1414   if (gdbserver_fd < 0 || s->fd < 0)
1415     return sig;
1416
1417   /* disable single step if it was enabled */
1418   cpu_single_step(env, 0);
1419   tb_flush(env);
1420
1421   if (sig != 0)
1422     {
1423       snprintf(buf, sizeof(buf), "S%02x", sig);
1424       put_packet(s, buf);
1425     }
1426   /* put_packet() might have detected that the peer terminated the
1427      connection.  */
1428   if (s->fd < 0)
1429       return sig;
1430
1431   sig = 0;
1432   s->state = RS_IDLE;
1433   s->running_state = 0;
1434   while (s->running_state == 0) {
1435       n = read (s->fd, buf, 256);
1436       if (n > 0)
1437         {
1438           int i;
1439
1440           for (i = 0; i < n; i++)
1441             gdb_read_byte (s, buf[i]);
1442         }
1443       else if (n == 0 || errno != EAGAIN)
1444         {
1445           /* XXX: Connection closed.  Should probably wait for annother
1446              connection before continuing.  */
1447           return sig;
1448         }
1449   }
1450   sig = s->signal;
1451   s->signal = 0;
1452   return sig;
1453 }
1454
1455 /* Tell the remote gdb that the process has exited.  */
1456 void gdb_exit(CPUState *env, int code)
1457 {
1458   GDBState *s;
1459   char buf[4];
1460
1461   s = &gdbserver_state;
1462   if (gdbserver_fd < 0 || s->fd < 0)
1463     return;
1464
1465   snprintf(buf, sizeof(buf), "W%02x", code);
1466   put_packet(s, buf);
1467 }
1468
1469
1470 static void gdb_accept(void *opaque)
1471 {
1472     GDBState *s;
1473     struct sockaddr_in sockaddr;
1474     socklen_t len;
1475     int val, fd;
1476
1477     for(;;) {
1478         len = sizeof(sockaddr);
1479         fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1480         if (fd < 0 && errno != EINTR) {
1481             perror("accept");
1482             return;
1483         } else if (fd >= 0) {
1484             break;
1485         }
1486     }
1487
1488     /* set short latency */
1489     val = 1;
1490     setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
1491
1492     s = &gdbserver_state;
1493     memset (s, 0, sizeof (GDBState));
1494     s->env = first_cpu; /* XXX: allow to change CPU */
1495     s->fd = fd;
1496
1497     gdb_syscall_state = s;
1498
1499     fcntl(fd, F_SETFL, O_NONBLOCK);
1500 }
1501
1502 static int gdbserver_open(int port)
1503 {
1504     struct sockaddr_in sockaddr;
1505     int fd, val, ret;
1506
1507     fd = socket(PF_INET, SOCK_STREAM, 0);
1508     if (fd < 0) {
1509         perror("socket");
1510         return -1;
1511     }
1512
1513     /* allow fast reuse */
1514     val = 1;
1515     setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
1516
1517     sockaddr.sin_family = AF_INET;
1518     sockaddr.sin_port = htons(port);
1519     sockaddr.sin_addr.s_addr = 0;
1520     ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1521     if (ret < 0) {
1522         perror("bind");
1523         return -1;
1524     }
1525     ret = listen(fd, 0);
1526     if (ret < 0) {
1527         perror("listen");
1528         return -1;
1529     }
1530     return fd;
1531 }
1532
1533 int gdbserver_start(int port)
1534 {
1535     gdbserver_fd = gdbserver_open(port);
1536     if (gdbserver_fd < 0)
1537         return -1;
1538     /* accept connections */
1539     gdb_accept (NULL);
1540     return 0;
1541 }
1542 #else
1543 static int gdb_chr_can_receive(void *opaque)
1544 {
1545   return 1;
1546 }
1547
1548 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
1549 {
1550     GDBState *s = opaque;
1551     int i;
1552
1553     for (i = 0; i < size; i++) {
1554         gdb_read_byte(s, buf[i]);
1555     }
1556 }
1557
1558 static void gdb_chr_event(void *opaque, int event)
1559 {
1560     switch (event) {
1561     case CHR_EVENT_RESET:
1562         vm_stop(EXCP_INTERRUPT);
1563         gdb_syscall_state = opaque;
1564         break;
1565     default:
1566         break;
1567     }
1568 }
1569
1570 int gdbserver_start(const char *port)
1571 {
1572     GDBState *s;
1573     char gdbstub_port_name[128];
1574     int port_num;
1575     char *p;
1576     CharDriverState *chr;
1577
1578     if (!port || !*port)
1579       return -1;
1580
1581     port_num = strtol(port, &p, 10);
1582     if (*p == 0) {
1583         /* A numeric value is interpreted as a port number.  */
1584         snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1585                  "tcp::%d,nowait,nodelay,server", port_num);
1586         port = gdbstub_port_name;
1587     }
1588
1589     chr = qemu_chr_open(port);
1590     if (!chr)
1591         return -1;
1592
1593     s = qemu_mallocz(sizeof(GDBState));
1594     if (!s) {
1595         return -1;
1596     }
1597     s->env = first_cpu; /* XXX: allow to change CPU */
1598     s->chr = chr;
1599     qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
1600                           gdb_chr_event, s);
1601     qemu_add_vm_stop_handler(gdb_vm_stopped, s);
1602     return 0;
1603 }
1604 #endif