hw/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - chip erase
  29  * - unlock bypass command
  30  * - CFI queries
  31  *
  32  * It does not support flash interleaving.
  33  * It does not implement boot blocs with reduced size
  34  * It does not implement software data protection as found in many real chips
  35  * It does not implement erase suspend/resume commands
  36  * It does not implement multiple sectors erase
  37  */
  38
  39 #include "hw.h"
  40 #include "flash.h"
  41 #include "qemu-timer.h"
  42 #include "block.h"
  43
  44 //#define PFLASH_DEBUG
  45 #ifdef PFLASH_DEBUG
  46 #define DPRINTF(fmt, args...)                      \
  47 do {                                               \
  48         printf("PFLASH: " fmt , ##args);           \
  49 } while (0)
  50 #else
  51 #define DPRINTF(fmt, args...) do { } while (0)
  52 #endif
  53
  54 struct pflash_t {
  55     BlockDriverState *bs;
  56     target_phys_addr_t base;
  57     uint32_t sector_len;
  58     uint32_t chip_len;
  59     int mappings;
  60     int width;
  61     int wcycle; /* if 0, the flash is read normally */
  62     int bypass;
  63     int ro;
  64     uint8_t cmd;
  65     uint8_t status;
  66     uint16_t ident[4];
  67     uint16_t unlock_addr[2];
  68     uint8_t cfi_len;
  69     uint8_t cfi_table[0x52];
  70     QEMUTimer *timer;
  71     ram_addr_t off;
  72     int fl_mem;
  73     int rom_mode;
  74     void *storage;
  75 };
  76
  77 static void pflash_register_memory(pflash_t *pfl, int rom_mode)
  78 {
  79     unsigned long phys_offset = pfl->fl_mem;
  80     int i;
  81
  82     if (rom_mode)
  83         phys_offset |= pfl->off | IO_MEM_ROMD;
  84     pfl->rom_mode = rom_mode;
  85
  86     for (i = 0; i < pfl->mappings; i++)
  87         cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
  88                                      pfl->chip_len, phys_offset);
  89 }
  90
  91 static void pflash_timer (void *opaque)
  92 {
  93     pflash_t *pfl = opaque;
  94
  95     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  96     /* Reset flash */
  97     pfl->status ^= 0x80;
  98     if (pfl->bypass) {
  99         pfl->wcycle = 2;
 100     } else {
 101         pflash_register_memory(pfl, 1);
 102         pfl->wcycle = 0;
 103     }
 104     pfl->cmd = 0;
 105 }
 106
 107 static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
 108 {
 109     uint32_t boff;
 110     uint32_t ret;
 111     uint8_t *p;
 112
 113     DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
 114     ret = -1;
 115     offset -= pfl->base;
 116     if (pfl->rom_mode) {
 117         /* Lazy reset of to ROMD mode */
 118         if (pfl->wcycle == 0)
 119             pflash_register_memory(pfl, 1);
 120     }
 121     offset &= pfl->chip_len - 1;
 122     boff = offset & 0xFF;
 123     if (pfl->width == 2)
 124         boff = boff >> 1;
 125     else if (pfl->width == 4)
 126         boff = boff >> 2;
 127     switch (pfl->cmd) {
 128     default:
 129         /* This should never happen : reset state & treat it as a read*/
 130         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 131         pfl->wcycle = 0;
 132         pfl->cmd = 0;
 133     case 0x80:
 134         /* We accept reads during second unlock sequence... */
 135     case 0x00:
 136     flash_read:
 137         /* Flash area read */
 138         p = pfl->storage;
 139         switch (width) {
 140         case 1:
 141             ret = p[offset];
 142 //            DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
 143             break;
 144         case 2:
 145 #if defined(TARGET_WORDS_BIGENDIAN)
 146             ret = p[offset] << 8;
 147             ret |= p[offset + 1];
 148 #else
 149             ret = p[offset];
 150             ret |= p[offset + 1] << 8;
 151 #endif
 152 //            DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
 153             break;
 154         case 4:
 155 #if defined(TARGET_WORDS_BIGENDIAN)
 156             ret = p[offset] << 24;
 157             ret |= p[offset + 1] << 16;
 158             ret |= p[offset + 2] << 8;
 159             ret |= p[offset + 3];
 160 #else
 161             ret = p[offset];
 162             ret |= p[offset + 1] << 8;
 163             ret |= p[offset + 2] << 16;
 164             ret |= p[offset + 3] << 24;
 165 #endif
 166 //            DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
 167             break;
 168         }
 169         break;
 170     case 0x90:
 171         /* flash ID read */
 172         switch (boff) {
 173         case 0x00:
 174         case 0x01:
 175             ret = pfl->ident[boff & 0x01];
 176             break;
 177         case 0x02:
 178             ret = 0x00; /* Pretend all sectors are unprotected */
 179             break;
 180         case 0x0E:
 181         case 0x0F:
 182             if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
 183                 goto flash_read;
 184             ret = pfl->ident[2 + (boff & 0x01)];
 185             break;
 186         default:
 187             goto flash_read;
 188         }
 189         DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
 190         break;
 191     case 0xA0:
 192     case 0x10:
 193     case 0x30:
 194         /* Status register read */
 195         ret = pfl->status;
 196         DPRINTF("%s: status %x\n", __func__, ret);
 197         /* Toggle bit 6 */
 198         pfl->status ^= 0x40;
 199         break;
 200     case 0x98:
 201         /* CFI query mode */
 202         if (boff > pfl->cfi_len)
 203             ret = 0;
 204         else
 205             ret = pfl->cfi_table[boff];
 206         break;
 207     }
 208
 209     return ret;
 210 }
 211
 212 /* update flash content on disk */
 213 static void pflash_update(pflash_t *pfl, int offset,
 214                           int size)
 215 {
 216     int offset_end;
 217     if (pfl->bs) {
 218         offset_end = offset + size;
 219         /* round to sectors */
 220         offset = offset >> 9;
 221         offset_end = (offset_end + 511) >> 9;
 222         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 223                    offset_end - offset);
 224     }
 225 }
 226
 227 static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
 228                           int width)
 229 {
 230     uint32_t boff;
 231     uint8_t *p;
 232     uint8_t cmd;
 233
 234     cmd = value;
 235     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 236 #if 0
 237         DPRINTF("%s: flash reset asked (%02x %02x)\n",
 238                 __func__, pfl->cmd, cmd);
 239 #endif
 240         goto reset_flash;
 241     }
 242     DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__,
 243             offset, value, width, pfl->wcycle);
 244     offset -= pfl->base;
 245     offset &= pfl->chip_len - 1;
 246
 247     DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
 248             offset, value, width);
 249     boff = offset & (pfl->sector_len - 1);
 250     if (pfl->width == 2)
 251         boff = boff >> 1;
 252     else if (pfl->width == 4)
 253         boff = boff >> 2;
 254     switch (pfl->wcycle) {
 255     case 0:
 256         /* Set the device in I/O access mode if required */
 257         if (pfl->rom_mode)
 258             pflash_register_memory(pfl, 0);
 259         /* We're in read mode */
 260     check_unlock0:
 261         if (boff == 0x55 && cmd == 0x98) {
 262         enter_CFI_mode:
 263             /* Enter CFI query mode */
 264             pfl->wcycle = 7;
 265             pfl->cmd = 0x98;
 266             return;
 267         }
 268         if (boff != pfl->unlock_addr[0] || cmd != 0xAA) {
 269             DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
 270                     __func__, boff, cmd, pfl->unlock_addr[0]);
 271             goto reset_flash;
 272         }
 273         DPRINTF("%s: unlock sequence started\n", __func__);
 274         break;
 275     case 1:
 276         /* We started an unlock sequence */
 277     check_unlock1:
 278         if (boff != pfl->unlock_addr[1] || cmd != 0x55) {
 279             DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
 280                     boff, cmd);
 281             goto reset_flash;
 282         }
 283         DPRINTF("%s: unlock sequence done\n", __func__);
 284         break;
 285     case 2:
 286         /* We finished an unlock sequence */
 287         if (!pfl->bypass && boff != pfl->unlock_addr[0]) {
 288             DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
 289                     boff, cmd);
 290             goto reset_flash;
 291         }
 292         switch (cmd) {
 293         case 0x20:
 294             pfl->bypass = 1;
 295             goto do_bypass;
 296         case 0x80:
 297         case 0x90:
 298         case 0xA0:
 299             pfl->cmd = cmd;
 300             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 301             break;
 302         default:
 303             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 304             goto reset_flash;
 305         }
 306         break;
 307     case 3:
 308         switch (pfl->cmd) {
 309         case 0x80:
 310             /* We need another unlock sequence */
 311             goto check_unlock0;
 312         case 0xA0:
 313             DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
 314                     __func__, offset, value, width);
 315             p = pfl->storage;
 316             switch (width) {
 317             case 1:
 318                 p[offset] &= value;
 319                 pflash_update(pfl, offset, 1);
 320                 break;
 321             case 2:
 322 #if defined(TARGET_WORDS_BIGENDIAN)
 323                 p[offset] &= value >> 8;
 324                 p[offset + 1] &= value;
 325 #else
 326                 p[offset] &= value;
 327                 p[offset + 1] &= value >> 8;
 328 #endif
 329                 pflash_update(pfl, offset, 2);
 330                 break;
 331             case 4:
 332 #if defined(TARGET_WORDS_BIGENDIAN)
 333                 p[offset] &= value >> 24;
 334                 p[offset + 1] &= value >> 16;
 335                 p[offset + 2] &= value >> 8;
 336                 p[offset + 3] &= value;
 337 #else
 338                 p[offset] &= value;
 339                 p[offset + 1] &= value >> 8;
 340                 p[offset + 2] &= value >> 16;
 341                 p[offset + 3] &= value >> 24;
 342 #endif
 343                 pflash_update(pfl, offset, 4);
 344                 break;
 345             }
 346             pfl->status = 0x00 | ~(value & 0x80);
 347             /* Let's pretend write is immediate */
 348             if (pfl->bypass)
 349                 goto do_bypass;
 350             goto reset_flash;
 351         case 0x90:
 352             if (pfl->bypass && cmd == 0x00) {
 353                 /* Unlock bypass reset */
 354                 goto reset_flash;
 355             }
 356             /* We can enter CFI query mode from autoselect mode */
 357             if (boff == 0x55 && cmd == 0x98)
 358                 goto enter_CFI_mode;
 359             /* No break here */
 360         default:
 361             DPRINTF("%s: invalid write for command %02x\n",
 362                     __func__, pfl->cmd);
 363             goto reset_flash;
 364         }
 365     case 4:
 366         switch (pfl->cmd) {
 367         case 0xA0:
 368             /* Ignore writes while flash data write is occuring */
 369             /* As we suppose write is immediate, this should never happen */
 370             return;
 371         case 0x80:
 372             goto check_unlock1;
 373         default:
 374             /* Should never happen */
 375             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 376                     __func__, pfl->cmd);
 377             goto reset_flash;
 378         }
 379         break;
 380     case 5:
 381         switch (cmd) {
 382         case 0x10:
 383             if (boff != pfl->unlock_addr[0]) {
 384                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
 385                         __func__, offset);
 386                 goto reset_flash;
 387             }
 388             /* Chip erase */
 389             DPRINTF("%s: start chip erase\n", __func__);
 390             memset(pfl->storage, 0xFF, pfl->chip_len);
 391             pfl->status = 0x00;
 392             pflash_update(pfl, 0, pfl->chip_len);
 393             /* Let's wait 5 seconds before chip erase is done */
 394             qemu_mod_timer(pfl->timer,
 395                            qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
 396             break;
 397         case 0x30:
 398             /* Sector erase */
 399             p = pfl->storage;
 400             offset &= ~(pfl->sector_len - 1);
 401             DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
 402                     offset);
 403             memset(p + offset, 0xFF, pfl->sector_len);
 404             pflash_update(pfl, offset, pfl->sector_len);
 405             pfl->status = 0x00;
 406             /* Let's wait 1/2 second before sector erase is done */
 407             qemu_mod_timer(pfl->timer,
 408                            qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
 409             break;
 410         default:
 411             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 412             goto reset_flash;
 413         }
 414         pfl->cmd = cmd;
 415         break;
 416     case 6:
 417         switch (pfl->cmd) {
 418         case 0x10:
 419             /* Ignore writes during chip erase */
 420             return;
 421         case 0x30:
 422             /* Ignore writes during sector erase */
 423             return;
 424         default:
 425             /* Should never happen */
 426             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 427                     __func__, pfl->cmd);
 428             goto reset_flash;
 429         }
 430         break;
 431     case 7: /* Special value for CFI queries */
 432         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 433         goto reset_flash;
 434     default:
 435         /* Should never happen */
 436         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 437         goto reset_flash;
 438     }
 439     pfl->wcycle++;
 440
 441     return;
 442
 443     /* Reset flash */
 444  reset_flash:
 445     pfl->bypass = 0;
 446     pfl->wcycle = 0;
 447     pfl->cmd = 0;
 448     return;
 449
 450  do_bypass:
 451     pfl->wcycle = 2;
 452     pfl->cmd = 0;
 453     return;
 454 }
 455
 456
 457 static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
 458 {
 459     return pflash_read(opaque, addr, 1);
 460 }
 461
 462 static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
 463 {
 464     pflash_t *pfl = opaque;
 465
 466     return pflash_read(pfl, addr, 2);
 467 }
 468
 469 static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
 470 {
 471     pflash_t *pfl = opaque;
 472
 473     return pflash_read(pfl, addr, 4);
 474 }
 475
 476 static void pflash_writeb (void *opaque, target_phys_addr_t addr,
 477                            uint32_t value)
 478 {
 479     pflash_write(opaque, addr, value, 1);
 480 }
 481
 482 static void pflash_writew (void *opaque, target_phys_addr_t addr,
 483                            uint32_t value)
 484 {
 485     pflash_t *pfl = opaque;
 486
 487     pflash_write(pfl, addr, value, 2);
 488 }
 489
 490 static void pflash_writel (void *opaque, target_phys_addr_t addr,
 491                            uint32_t value)
 492 {
 493     pflash_t *pfl = opaque;
 494
 495     pflash_write(pfl, addr, value, 4);
 496 }
 497
 498 static CPUWriteMemoryFunc *pflash_write_ops[] = {
 499     &pflash_writeb,
 500     &pflash_writew,
 501     &pflash_writel,
 502 };
 503
 504 static CPUReadMemoryFunc *pflash_read_ops[] = {
 505     &pflash_readb,
 506     &pflash_readw,
 507     &pflash_readl,
 508 };
 509
 510 /* Count trailing zeroes of a 32 bits quantity */
 511 static int ctz32 (uint32_t n)
 512 {
 513     int ret;
 514
 515     ret = 0;
 516     if (!(n & 0xFFFF)) {
 517         ret += 16;
 518         n = n >> 16;
 519     }
 520     if (!(n & 0xFF)) {
 521         ret += 8;
 522         n = n >> 8;
 523     }
 524     if (!(n & 0xF)) {
 525         ret += 4;
 526         n = n >> 4;
 527     }
 528     if (!(n & 0x3)) {
 529         ret += 2;
 530         n = n >> 2;
 531     }
 532     if (!(n & 0x1)) {
 533         ret++;
 534         n = n >> 1;
 535     }
 536 #if 0 /* This is not necessary as n is never 0 */
 537     if (!n)
 538         ret++;
 539 #endif
 540
 541     return ret;
 542 }
 543
 544 pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
 545                                 BlockDriverState *bs, uint32_t sector_len,
 546                                 int nb_blocs, int nb_mappings, int width,
 547                                 uint16_t id0, uint16_t id1,
 548                                 uint16_t id2, uint16_t id3,
 549                                 uint16_t unlock_addr0, uint16_t unlock_addr1)
 550 {
 551     pflash_t *pfl;
 552     int32_t chip_len;
 553
 554     chip_len = sector_len * nb_blocs;
 555     /* XXX: to be fixed */
 556 #if 0
 557     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 558         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 559         return NULL;
 560 #endif
 561     pfl = qemu_mallocz(sizeof(pflash_t));
 562     if (pfl == NULL)
 563         return NULL;
 564     pfl->storage = phys_ram_base + off;
 565     pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
 566                                          pfl);
 567     pfl->off = off;
 568     pfl->base = base;
 569     pfl->chip_len = chip_len;
 570     pfl->mappings = nb_mappings;
 571     pflash_register_memory(pfl, 1);
 572     pfl->bs = bs;
 573     if (pfl->bs) {
 574         /* read the initial flash content */
 575         bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
 576     }
 577 #if 0 /* XXX: there should be a bit to set up read-only,
 578        *      the same way the hardware does (with WP pin).
 579        */
 580     pfl->ro = 1;
 581 #else
 582     pfl->ro = 0;
 583 #endif
 584     pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
 585     pfl->sector_len = sector_len;
 586     pfl->width = width;
 587     pfl->wcycle = 0;
 588     pfl->cmd = 0;
 589     pfl->status = 0;
 590     pfl->ident[0] = id0;
 591     pfl->ident[1] = id1;
 592     pfl->ident[2] = id2;
 593     pfl->ident[3] = id3;
 594     pfl->unlock_addr[0] = unlock_addr0;
 595     pfl->unlock_addr[1] = unlock_addr1;
 596     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 597     pfl->cfi_len = 0x52;
 598     /* Standard "QRY" string */
 599     pfl->cfi_table[0x10] = 'Q';
 600     pfl->cfi_table[0x11] = 'R';
 601     pfl->cfi_table[0x12] = 'Y';
 602     /* Command set (AMD/Fujitsu) */
 603     pfl->cfi_table[0x13] = 0x02;
 604     pfl->cfi_table[0x14] = 0x00;
 605     /* Primary extended table address */
 606     pfl->cfi_table[0x15] = 0x31;
 607     pfl->cfi_table[0x16] = 0x00;
 608     /* Alternate command set (none) */
 609     pfl->cfi_table[0x17] = 0x00;
 610     pfl->cfi_table[0x18] = 0x00;
 611     /* Alternate extended table (none) */
 612     pfl->cfi_table[0x19] = 0x00;
 613     pfl->cfi_table[0x1A] = 0x00;
 614     /* Vcc min */
 615     pfl->cfi_table[0x1B] = 0x27;
 616     /* Vcc max */
 617     pfl->cfi_table[0x1C] = 0x36;
 618     /* Vpp min (no Vpp pin) */
 619     pfl->cfi_table[0x1D] = 0x00;
 620     /* Vpp max (no Vpp pin) */
 621     pfl->cfi_table[0x1E] = 0x00;
 622     /* Reserved */
 623     pfl->cfi_table[0x1F] = 0x07;
 624     /* Timeout for min size buffer write (NA) */
 625     pfl->cfi_table[0x20] = 0x00;
 626     /* Typical timeout for block erase (512 ms) */
 627     pfl->cfi_table[0x21] = 0x09;
 628     /* Typical timeout for full chip erase (4096 ms) */
 629     pfl->cfi_table[0x22] = 0x0C;
 630     /* Reserved */
 631     pfl->cfi_table[0x23] = 0x01;
 632     /* Max timeout for buffer write (NA) */
 633     pfl->cfi_table[0x24] = 0x00;
 634     /* Max timeout for block erase */
 635     pfl->cfi_table[0x25] = 0x0A;
 636     /* Max timeout for chip erase */
 637     pfl->cfi_table[0x26] = 0x0D;
 638     /* Device size */
 639     pfl->cfi_table[0x27] = ctz32(chip_len);
 640     /* Flash device interface (8 & 16 bits) */
 641     pfl->cfi_table[0x28] = 0x02;
 642     pfl->cfi_table[0x29] = 0x00;
 643     /* Max number of bytes in multi-bytes write */
 644     /* XXX: disable buffered write as it's not supported */
 645     //    pfl->cfi_table[0x2A] = 0x05;
 646     pfl->cfi_table[0x2A] = 0x00;
 647     pfl->cfi_table[0x2B] = 0x00;
 648     /* Number of erase block regions (uniform) */
 649     pfl->cfi_table[0x2C] = 0x01;
 650     /* Erase block region 1 */
 651     pfl->cfi_table[0x2D] = nb_blocs - 1;
 652     pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
 653     pfl->cfi_table[0x2F] = sector_len >> 8;
 654     pfl->cfi_table[0x30] = sector_len >> 16;
 655
 656     /* Extended */
 657     pfl->cfi_table[0x31] = 'P';
 658     pfl->cfi_table[0x32] = 'R';
 659     pfl->cfi_table[0x33] = 'I';
 660
 661     pfl->cfi_table[0x34] = '1';
 662     pfl->cfi_table[0x35] = '0';
 663
 664     pfl->cfi_table[0x36] = 0x00;
 665     pfl->cfi_table[0x37] = 0x00;
 666     pfl->cfi_table[0x38] = 0x00;
 667     pfl->cfi_table[0x39] = 0x00;
 668
 669     pfl->cfi_table[0x3a] = 0x00;
 670
 671     pfl->cfi_table[0x3b] = 0x00;
 672     pfl->cfi_table[0x3c] = 0x00;
 673
 674     return pfl;
 675 }