hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "serial.h"
  27 #include "char/char.h"
  28 #include "qemu/timer.h"
  29 #include "exec/address-spaces.h"
  30
  31 //#define DEBUG_SERIAL
  32
  33 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  34
  35 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  36 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  37 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  38 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  39
  40 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  41 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  42
  43 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  44 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  45 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  46 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  47 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  48
  49 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  50 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  51
  52 /*
  53  * These are the definitions for the Modem Control Register
  54  */
  55 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  56 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  57 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  58 #define UART_MCR_RTS    0x02    /* RTS complement */
  59 #define UART_MCR_DTR    0x01    /* DTR complement */
  60
  61 /*
  62  * These are the definitions for the Modem Status Register
  63  */
  64 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  65 #define UART_MSR_RI     0x40    /* Ring Indicator */
  66 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  67 #define UART_MSR_CTS    0x10    /* Clear to Send */
  68 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  69 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  70 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  71 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  72 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  73
  74 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  75 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  76 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  77 #define UART_LSR_FE     0x08    /* Frame error indicator */
  78 #define UART_LSR_PE     0x04    /* Parity error indicator */
  79 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  80 #define UART_LSR_DR     0x01    /* Receiver data ready */
  81 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  82
  83 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  84
  85 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  86 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  87 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  88 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  89
  90 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  91 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  92 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  93 #define UART_FCR_FE         0x01    /* FIFO Enable */
  94
  95 #define XMIT_FIFO           0
  96 #define RECV_FIFO           1
  97 #define MAX_XMIT_RETRY      4
  98
  99 #ifdef DEBUG_SERIAL
 100 #define DPRINTF(fmt, ...) \
 101 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 102 #else
 103 #define DPRINTF(fmt, ...) \
 104 do {} while (0)
 105 #endif
 106
 107 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 108
 109 static void fifo_clear(SerialState *s, int fifo)
 110 {
 111     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 112     memset(f->data, 0, UART_FIFO_LENGTH);
 113     f->count = 0;
 114     f->head = 0;
 115     f->tail = 0;
 116 }
 117
 118 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 119 {
 120     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 121
 122     /* Receive overruns do not overwrite FIFO contents. */
 123     if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
 124
 125         f->data[f->head++] = chr;
 126
 127         if (f->head == UART_FIFO_LENGTH)
 128             f->head = 0;
 129     }
 130
 131     if (f->count < UART_FIFO_LENGTH)
 132         f->count++;
 133     else if (fifo == RECV_FIFO)
 134         s->lsr |= UART_LSR_OE;
 135
 136     return 1;
 137 }
 138
 139 static uint8_t fifo_get(SerialState *s, int fifo)
 140 {
 141     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 142     uint8_t c;
 143
 144     if(f->count == 0)
 145         return 0;
 146
 147     c = f->data[f->tail++];
 148     if (f->tail == UART_FIFO_LENGTH)
 149         f->tail = 0;
 150     f->count--;
 151
 152     return c;
 153 }
 154
 155 static void serial_update_irq(SerialState *s)
 156 {
 157     uint8_t tmp_iir = UART_IIR_NO_INT;
 158
 159     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 160         tmp_iir = UART_IIR_RLSI;
 161     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 162         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 163          * this is not in the specification but is observed on existing
 164          * hardware.  */
 165         tmp_iir = UART_IIR_CTI;
 166     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 167                (!(s->fcr & UART_FCR_FE) ||
 168                 s->recv_fifo.count >= s->recv_fifo.itl)) {
 169         tmp_iir = UART_IIR_RDI;
 170     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 171         tmp_iir = UART_IIR_THRI;
 172     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 173         tmp_iir = UART_IIR_MSI;
 174     }
 175
 176     s->iir = tmp_iir | (s->iir & 0xF0);
 177
 178     if (tmp_iir != UART_IIR_NO_INT) {
 179         qemu_irq_raise(s->irq);
 180     } else {
 181         qemu_irq_lower(s->irq);
 182     }
 183 }
 184
 185 static void serial_update_parameters(SerialState *s)
 186 {
 187     int speed, parity, data_bits, stop_bits, frame_size;
 188     QEMUSerialSetParams ssp;
 189
 190     if (s->divider == 0)
 191         return;
 192
 193     /* Start bit. */
 194     frame_size = 1;
 195     if (s->lcr & 0x08) {
 196         /* Parity bit. */
 197         frame_size++;
 198         if (s->lcr & 0x10)
 199             parity = 'E';
 200         else
 201             parity = 'O';
 202     } else {
 203             parity = 'N';
 204     }
 205     if (s->lcr & 0x04)
 206         stop_bits = 2;
 207     else
 208         stop_bits = 1;
 209
 210     data_bits = (s->lcr & 0x03) + 5;
 211     frame_size += data_bits + stop_bits;
 212     speed = s->baudbase / s->divider;
 213     ssp.speed = speed;
 214     ssp.parity = parity;
 215     ssp.data_bits = data_bits;
 216     ssp.stop_bits = stop_bits;
 217     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 218     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 219
 220     DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
 221            speed, parity, data_bits, stop_bits);
 222 }
 223
 224 static void serial_update_msl(SerialState *s)
 225 {
 226     uint8_t omsr;
 227     int flags;
 228
 229     qemu_del_timer(s->modem_status_poll);
 230
 231     if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 232         s->poll_msl = -1;
 233         return;
 234     }
 235
 236     omsr = s->msr;
 237
 238     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 239     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 240     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 241     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 242
 243     if (s->msr != omsr) {
 244          /* Set delta bits */
 245          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 246          /* UART_MSR_TERI only if change was from 1 -> 0 */
 247          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 248              s->msr &= ~UART_MSR_TERI;
 249          serial_update_irq(s);
 250     }
 251
 252     /* The real 16550A apparently has a 250ns response latency to line status changes.
 253        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 254
 255     if (s->poll_msl)
 256         qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
 257 }
 258
 259 static void serial_xmit(void *opaque)
 260 {
 261     SerialState *s = opaque;
 262     uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
 263
 264     if (s->tsr_retry <= 0) {
 265         if (s->fcr & UART_FCR_FE) {
 266             s->tsr = fifo_get(s,XMIT_FIFO);
 267             if (!s->xmit_fifo.count)
 268                 s->lsr |= UART_LSR_THRE;
 269         } else {
 270             s->tsr = s->thr;
 271             s->lsr |= UART_LSR_THRE;
 272             s->lsr &= ~UART_LSR_TEMT;
 273         }
 274     }
 275
 276     if (s->mcr & UART_MCR_LOOP) {
 277         /* in loopback mode, say that we just received a char */
 278         serial_receive1(s, &s->tsr, 1);
 279     } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
 280         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 281             s->tsr_retry++;
 282             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 283             return;
 284         } else if (s->poll_msl < 0) {
 285             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 286             drop any further failed writes instantly, until we get one that goes through.
 287             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 288             s->tsr_retry = -1;
 289         }
 290     }
 291     else {
 292         s->tsr_retry = 0;
 293     }
 294
 295     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
 296     if (!(s->lsr & UART_LSR_THRE))
 297         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 298
 299     if (s->lsr & UART_LSR_THRE) {
 300         s->lsr |= UART_LSR_TEMT;
 301         s->thr_ipending = 1;
 302         serial_update_irq(s);
 303     }
 304 }
 305
 306
 307 static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 308                                 unsigned size)
 309 {
 310     SerialState *s = opaque;
 311
 312     addr &= 7;
 313     DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
 314     switch(addr) {
 315     default:
 316     case 0:
 317         if (s->lcr & UART_LCR_DLAB) {
 318             s->divider = (s->divider & 0xff00) | val;
 319             serial_update_parameters(s);
 320         } else {
 321             s->thr = (uint8_t) val;
 322             if(s->fcr & UART_FCR_FE) {
 323                 fifo_put(s, XMIT_FIFO, s->thr);
 324                 s->thr_ipending = 0;
 325                 s->lsr &= ~UART_LSR_TEMT;
 326                 s->lsr &= ~UART_LSR_THRE;
 327                 serial_update_irq(s);
 328             } else {
 329                 s->thr_ipending = 0;
 330                 s->lsr &= ~UART_LSR_THRE;
 331                 serial_update_irq(s);
 332             }
 333             serial_xmit(s);
 334         }
 335         break;
 336     case 1:
 337         if (s->lcr & UART_LCR_DLAB) {
 338             s->divider = (s->divider & 0x00ff) | (val << 8);
 339             serial_update_parameters(s);
 340         } else {
 341             s->ier = val & 0x0f;
 342             /* If the backend device is a real serial port, turn polling of the modem
 343                status lines on physical port on or off depending on UART_IER_MSI state */
 344             if (s->poll_msl >= 0) {
 345                 if (s->ier & UART_IER_MSI) {
 346                      s->poll_msl = 1;
 347                      serial_update_msl(s);
 348                 } else {
 349                      qemu_del_timer(s->modem_status_poll);
 350                      s->poll_msl = 0;
 351                 }
 352             }
 353             if (s->lsr & UART_LSR_THRE) {
 354                 s->thr_ipending = 1;
 355                 serial_update_irq(s);
 356             }
 357         }
 358         break;
 359     case 2:
 360         val = val & 0xFF;
 361
 362         if (s->fcr == val)
 363             break;
 364
 365         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 366         if ((val ^ s->fcr) & UART_FCR_FE)
 367             val |= UART_FCR_XFR | UART_FCR_RFR;
 368
 369         /* FIFO clear */
 370
 371         if (val & UART_FCR_RFR) {
 372             qemu_del_timer(s->fifo_timeout_timer);
 373             s->timeout_ipending=0;
 374             fifo_clear(s,RECV_FIFO);
 375         }
 376
 377         if (val & UART_FCR_XFR) {
 378             fifo_clear(s,XMIT_FIFO);
 379         }
 380
 381         if (val & UART_FCR_FE) {
 382             s->iir |= UART_IIR_FE;
 383             /* Set RECV_FIFO trigger Level */
 384             switch (val & 0xC0) {
 385             case UART_FCR_ITL_1:
 386                 s->recv_fifo.itl = 1;
 387                 break;
 388             case UART_FCR_ITL_2:
 389                 s->recv_fifo.itl = 4;
 390                 break;
 391             case UART_FCR_ITL_3:
 392                 s->recv_fifo.itl = 8;
 393                 break;
 394             case UART_FCR_ITL_4:
 395                 s->recv_fifo.itl = 14;
 396                 break;
 397             }
 398         } else
 399             s->iir &= ~UART_IIR_FE;
 400
 401         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 402         s->fcr = val & 0xC9;
 403         serial_update_irq(s);
 404         break;
 405     case 3:
 406         {
 407             int break_enable;
 408             s->lcr = val;
 409             serial_update_parameters(s);
 410             break_enable = (val >> 6) & 1;
 411             if (break_enable != s->last_break_enable) {
 412                 s->last_break_enable = break_enable;
 413                 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 414                                &break_enable);
 415             }
 416         }
 417         break;
 418     case 4:
 419         {
 420             int flags;
 421             int old_mcr = s->mcr;
 422             s->mcr = val & 0x1f;
 423             if (val & UART_MCR_LOOP)
 424                 break;
 425
 426             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 427
 428                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 429
 430                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 431
 432                 if (val & UART_MCR_RTS)
 433                     flags |= CHR_TIOCM_RTS;
 434                 if (val & UART_MCR_DTR)
 435                     flags |= CHR_TIOCM_DTR;
 436
 437                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 438                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 439                    from the device/computer at the other end of the serial line */
 440                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
 441             }
 442         }
 443         break;
 444     case 5:
 445         break;
 446     case 6:
 447         break;
 448     case 7:
 449         s->scr = val;
 450         break;
 451     }
 452 }
 453
 454 static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
 455 {
 456     SerialState *s = opaque;
 457     uint32_t ret;
 458
 459     addr &= 7;
 460     switch(addr) {
 461     default:
 462     case 0:
 463         if (s->lcr & UART_LCR_DLAB) {
 464             ret = s->divider & 0xff;
 465         } else {
 466             if(s->fcr & UART_FCR_FE) {
 467                 ret = fifo_get(s,RECV_FIFO);
 468                 if (s->recv_fifo.count == 0)
 469                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 470                 else
 471                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
 472                 s->timeout_ipending = 0;
 473             } else {
 474                 ret = s->rbr;
 475                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 476             }
 477             serial_update_irq(s);
 478             if (!(s->mcr & UART_MCR_LOOP)) {
 479                 /* in loopback mode, don't receive any data */
 480                 qemu_chr_accept_input(s->chr);
 481             }
 482         }
 483         break;
 484     case 1:
 485         if (s->lcr & UART_LCR_DLAB) {
 486             ret = (s->divider >> 8) & 0xff;
 487         } else {
 488             ret = s->ier;
 489         }
 490         break;
 491     case 2:
 492         ret = s->iir;
 493         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 494             s->thr_ipending = 0;
 495             serial_update_irq(s);
 496         }
 497         break;
 498     case 3:
 499         ret = s->lcr;
 500         break;
 501     case 4:
 502         ret = s->mcr;
 503         break;
 504     case 5:
 505         ret = s->lsr;
 506         /* Clear break and overrun interrupts */
 507         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 508             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 509             serial_update_irq(s);
 510         }
 511         break;
 512     case 6:
 513         if (s->mcr & UART_MCR_LOOP) {
 514             /* in loopback, the modem output pins are connected to the
 515                inputs */
 516             ret = (s->mcr & 0x0c) << 4;
 517             ret |= (s->mcr & 0x02) << 3;
 518             ret |= (s->mcr & 0x01) << 5;
 519         } else {
 520             if (s->poll_msl >= 0)
 521                 serial_update_msl(s);
 522             ret = s->msr;
 523             /* Clear delta bits & msr int after read, if they were set */
 524             if (s->msr & UART_MSR_ANY_DELTA) {
 525                 s->msr &= 0xF0;
 526                 serial_update_irq(s);
 527             }
 528         }
 529         break;
 530     case 7:
 531         ret = s->scr;
 532         break;
 533     }
 534     DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
 535     return ret;
 536 }
 537
 538 static int serial_can_receive(SerialState *s)
 539 {
 540     if(s->fcr & UART_FCR_FE) {
 541         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 542         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 543         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 544         effectively overriding the ITL that the guest has set. */
 545              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 546         else
 547              return 0;
 548     } else {
 549     return !(s->lsr & UART_LSR_DR);
 550     }
 551 }
 552
 553 static void serial_receive_break(SerialState *s)
 554 {
 555     s->rbr = 0;
 556     /* When the LSR_DR is set a null byte is pushed into the fifo */
 557     fifo_put(s, RECV_FIFO, '\0');
 558     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 559     serial_update_irq(s);
 560 }
 561
 562 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 563 static void fifo_timeout_int (void *opaque) {
 564     SerialState *s = opaque;
 565     if (s->recv_fifo.count) {
 566         s->timeout_ipending = 1;
 567         serial_update_irq(s);
 568     }
 569 }
 570
 571 static int serial_can_receive1(void *opaque)
 572 {
 573     SerialState *s = opaque;
 574     return serial_can_receive(s);
 575 }
 576
 577 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 578 {
 579     SerialState *s = opaque;
 580
 581     if (s->wakeup) {
 582         qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
 583     }
 584     if(s->fcr & UART_FCR_FE) {
 585         int i;
 586         for (i = 0; i < size; i++) {
 587             fifo_put(s, RECV_FIFO, buf[i]);
 588         }
 589         s->lsr |= UART_LSR_DR;
 590         /* call the timeout receive callback in 4 char transmit time */
 591         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
 592     } else {
 593         if (s->lsr & UART_LSR_DR)
 594             s->lsr |= UART_LSR_OE;
 595         s->rbr = buf[0];
 596         s->lsr |= UART_LSR_DR;
 597     }
 598     serial_update_irq(s);
 599 }
 600
 601 static void serial_event(void *opaque, int event)
 602 {
 603     SerialState *s = opaque;
 604     DPRINTF("event %x\n", event);
 605     if (event == CHR_EVENT_BREAK)
 606         serial_receive_break(s);
 607 }
 608
 609 static void serial_pre_save(void *opaque)
 610 {
 611     SerialState *s = opaque;
 612     s->fcr_vmstate = s->fcr;
 613 }
 614
 615 static int serial_post_load(void *opaque, int version_id)
 616 {
 617     SerialState *s = opaque;
 618
 619     if (version_id < 3) {
 620         s->fcr_vmstate = 0;
 621     }
 622     /* Initialize fcr via setter to perform essential side-effects */
 623     serial_ioport_write(s, 0x02, s->fcr_vmstate, 1);
 624     serial_update_parameters(s);
 625     return 0;
 626 }
 627
 628 const VMStateDescription vmstate_serial = {
 629     .name = "serial",
 630     .version_id = 3,
 631     .minimum_version_id = 2,
 632     .pre_save = serial_pre_save,
 633     .post_load = serial_post_load,
 634     .fields      = (VMStateField []) {
 635         VMSTATE_UINT16_V(divider, SerialState, 2),
 636         VMSTATE_UINT8(rbr, SerialState),
 637         VMSTATE_UINT8(ier, SerialState),
 638         VMSTATE_UINT8(iir, SerialState),
 639         VMSTATE_UINT8(lcr, SerialState),
 640         VMSTATE_UINT8(mcr, SerialState),
 641         VMSTATE_UINT8(lsr, SerialState),
 642         VMSTATE_UINT8(msr, SerialState),
 643         VMSTATE_UINT8(scr, SerialState),
 644         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 645         VMSTATE_END_OF_LIST()
 646     }
 647 };
 648
 649 static void serial_reset(void *opaque)
 650 {
 651     SerialState *s = opaque;
 652
 653     s->rbr = 0;
 654     s->ier = 0;
 655     s->iir = UART_IIR_NO_INT;
 656     s->lcr = 0;
 657     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 658     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 659     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 660     s->divider = 0x0C;
 661     s->mcr = UART_MCR_OUT2;
 662     s->scr = 0;
 663     s->tsr_retry = 0;
 664     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
 665     s->poll_msl = 0;
 666
 667     fifo_clear(s,RECV_FIFO);
 668     fifo_clear(s,XMIT_FIFO);
 669
 670     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
 671
 672     s->thr_ipending = 0;
 673     s->last_break_enable = 0;
 674     qemu_irq_lower(s->irq);
 675 }
 676
 677 void serial_init_core(SerialState *s)
 678 {
 679     if (!s->chr) {
 680         fprintf(stderr, "Can't create serial device, empty char device\n");
 681         exit(1);
 682     }
 683
 684     s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 685
 686     s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 687     s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 688
 689     qemu_register_reset(serial_reset, s);
 690
 691     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 692                           serial_event, s);
 693 }
 694
 695 void serial_exit_core(SerialState *s)
 696 {
 697     qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL);
 698     qemu_unregister_reset(serial_reset, s);
 699 }
 700
 701 /* Change the main reference oscillator frequency. */
 702 void serial_set_frequency(SerialState *s, uint32_t frequency)
 703 {
 704     s->baudbase = frequency;
 705     serial_update_parameters(s);
 706 }
 707
 708 const MemoryRegionOps serial_io_ops = {
 709     .read = serial_ioport_read,
 710     .write = serial_ioport_write,
 711     .impl = {
 712         .min_access_size = 1,
 713         .max_access_size = 1,
 714     },
 715     .endianness = DEVICE_LITTLE_ENDIAN,
 716 };
 717
 718 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 719                          CharDriverState *chr, MemoryRegion *system_io)
 720 {
 721     SerialState *s;
 722
 723     s = g_malloc0(sizeof(SerialState));
 724
 725     s->irq = irq;
 726     s->baudbase = baudbase;
 727     s->chr = chr;
 728     serial_init_core(s);
 729
 730     vmstate_register(NULL, base, &vmstate_serial, s);
 731
 732     memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
 733     memory_region_add_subregion(system_io, base, &s->io);
 734
 735     return s;
 736 }
 737
 738 /* Memory mapped interface */
 739 static uint64_t serial_mm_read(void *opaque, hwaddr addr,
 740                                unsigned size)
 741 {
 742     SerialState *s = opaque;
 743     return serial_ioport_read(s, addr >> s->it_shift, 1);
 744 }
 745
 746 static void serial_mm_write(void *opaque, hwaddr addr,
 747                             uint64_t value, unsigned size)
 748 {
 749     SerialState *s = opaque;
 750     value &= ~0u >> (32 - (size * 8));
 751     serial_ioport_write(s, addr >> s->it_shift, value, 1);
 752 }
 753
 754 static const MemoryRegionOps serial_mm_ops[3] = {
 755     [DEVICE_NATIVE_ENDIAN] = {
 756         .read = serial_mm_read,
 757         .write = serial_mm_write,
 758         .endianness = DEVICE_NATIVE_ENDIAN,
 759     },
 760     [DEVICE_LITTLE_ENDIAN] = {
 761         .read = serial_mm_read,
 762         .write = serial_mm_write,
 763         .endianness = DEVICE_LITTLE_ENDIAN,
 764     },
 765     [DEVICE_BIG_ENDIAN] = {
 766         .read = serial_mm_read,
 767         .write = serial_mm_write,
 768         .endianness = DEVICE_BIG_ENDIAN,
 769     },
 770 };
 771
 772 SerialState *serial_mm_init(MemoryRegion *address_space,
 773                             hwaddr base, int it_shift,
 774                             qemu_irq irq, int baudbase,
 775                             CharDriverState *chr, enum device_endian end)
 776 {
 777     SerialState *s;
 778
 779     s = g_malloc0(sizeof(SerialState));
 780
 781     s->it_shift = it_shift;
 782     s->irq = irq;
 783     s->baudbase = baudbase;
 784     s->chr = chr;
 785
 786     serial_init_core(s);
 787     vmstate_register(NULL, base, &vmstate_serial, s);
 788
 789     memory_region_init_io(&s->io, &serial_mm_ops[end], s,
 790                           "serial", 8 << it_shift);
 791     memory_region_add_subregion(address_space, base, &s->io);
 792
 793     serial_update_msl(s);
 794     return s;
 795 }