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target-arm: Add support for 'Standard FPSCR Value' as used by Neon
[qemu/agraf.git] / target-microblaze / translate.c
blob2e236fb8443d839a3e2c684a212d8d12a8d5b1a8
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "helper.h"
32 #include "microblaze-decode.h"
33 #include "qemu-common.h"
34
35 #define GEN_HELPER 1
36 #include "helper.h"
37
38 #define SIM_COMPAT 0
39 #define DISAS_GNU 1
40 #define DISAS_MB 1
41 #if DISAS_MB && !SIM_COMPAT
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DIS(...) do { } while (0)
45 #endif
46
47 #define D(x)
48
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52 static TCGv env_debug;
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_R[32];
55 static TCGv cpu_SR[18];
56 static TCGv env_imm;
57 static TCGv env_btaken;
58 static TCGv env_btarget;
59 static TCGv env_iflags;
60
61 #include "gen-icount.h"
62
63 /* This is the state at translation time. */
64 typedef struct DisasContext {
65 CPUState *env;
66 target_ulong pc;
67
68 /* Decoder. */
69 int type_b;
70 uint32_t ir;
71 uint8_t opcode;
72 uint8_t rd, ra, rb;
73 uint16_t imm;
74
75 unsigned int cpustate_changed;
76 unsigned int delayed_branch;
77 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
78 unsigned int clear_imm;
79 int is_jmp;
80
81 #define JMP_NOJMP 0
82 #define JMP_DIRECT 1
83 #define JMP_DIRECT_CC 2
84 #define JMP_INDIRECT 3
85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92 } DisasContext;
93
94 static const char *regnames[] =
95 {
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100 };
101
102 static const char *special_regnames[] =
103 {
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107 };
108
109 /* Sign extend at translation time. */
110 static inline int sign_extend(unsigned int val, unsigned int width)
111 {
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120 }
121
122 static inline void t_sync_flags(DisasContext *dc)
123 {
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129 }
130
131 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132 {
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140 }
141
142 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143 {
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154 }
155
156 /* True if ALU operand b is a small immediate that may deserve
157 faster treatment. */
158 static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
159 {
160 /* Immediate insn without the imm prefix ? */
161 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
162 }
163
164 static inline TCGv *dec_alu_op_b(DisasContext *dc)
165 {
166 if (dc->type_b) {
167 if (dc->tb_flags & IMM_FLAG)
168 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
169 else
170 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
171 return &env_imm;
172 } else
173 return &cpu_R[dc->rb];
174 }
175
176 static void dec_add(DisasContext *dc)
177 {
178 unsigned int k, c;
179
180 k = dc->opcode & 4;
181 c = dc->opcode & 2;
182
183 LOG_DIS("add%s%s%s r%d r%d r%d\n",
184 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
185 dc->rd, dc->ra, dc->rb);
186
187 if (k && !c && dc->rd)
188 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
189 else if (dc->rd)
190 gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
191 tcg_const_tl(k), tcg_const_tl(c));
192 else {
193 TCGv d = tcg_temp_new();
194 gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
195 tcg_const_tl(k), tcg_const_tl(c));
196 tcg_temp_free(d);
197 }
198 }
199
200 static void dec_sub(DisasContext *dc)
201 {
202 unsigned int u, cmp, k, c;
203
204 u = dc->imm & 2;
205 k = dc->opcode & 4;
206 c = dc->opcode & 2;
207 cmp = (dc->imm & 1) && (!dc->type_b) && k;
208
209 if (cmp) {
210 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
211 if (dc->rd) {
212 if (u)
213 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
214 else
215 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
216 }
217 } else {
218 LOG_DIS("sub%s%s r%d, r%d r%d\n",
219 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
220
221 if (!k || c) {
222 TCGv t;
223 t = tcg_temp_new();
224 if (dc->rd)
225 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
226 tcg_const_tl(k), tcg_const_tl(c));
227 else
228 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
229 tcg_const_tl(k), tcg_const_tl(c));
230 tcg_temp_free(t);
231 }
232 else if (dc->rd)
233 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
234 }
235 }
236
237 static void dec_pattern(DisasContext *dc)
238 {
239 unsigned int mode;
240 int l1;
241
242 if ((dc->tb_flags & MSR_EE_FLAG)
243 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
244 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
245 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
246 t_gen_raise_exception(dc, EXCP_HW_EXCP);
247 }
248
249 mode = dc->opcode & 3;
250 switch (mode) {
251 case 0:
252 /* pcmpbf. */
253 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
254 if (dc->rd)
255 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
256 break;
257 case 2:
258 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
259 if (dc->rd) {
260 TCGv t0 = tcg_temp_local_new();
261 l1 = gen_new_label();
262 tcg_gen_movi_tl(t0, 1);
263 tcg_gen_brcond_tl(TCG_COND_EQ,
264 cpu_R[dc->ra], cpu_R[dc->rb], l1);
265 tcg_gen_movi_tl(t0, 0);
266 gen_set_label(l1);
267 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
268 tcg_temp_free(t0);
269 }
270 break;
271 case 3:
272 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
273 l1 = gen_new_label();
274 if (dc->rd) {
275 TCGv t0 = tcg_temp_local_new();
276 tcg_gen_movi_tl(t0, 1);
277 tcg_gen_brcond_tl(TCG_COND_NE,
278 cpu_R[dc->ra], cpu_R[dc->rb], l1);
279 tcg_gen_movi_tl(t0, 0);
280 gen_set_label(l1);
281 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
282 tcg_temp_free(t0);
283 }
284 break;
285 default:
286 cpu_abort(dc->env,
287 "unsupported pattern insn opcode=%x\n", dc->opcode);
288 break;
289 }
290 }
291
292 static void dec_and(DisasContext *dc)
293 {
294 unsigned int not;
295
296 if (!dc->type_b && (dc->imm & (1 << 10))) {
297 dec_pattern(dc);
298 return;
299 }
300
301 not = dc->opcode & (1 << 1);
302 LOG_DIS("and%s\n", not ? "n" : "");
303
304 if (!dc->rd)
305 return;
306
307 if (not) {
308 TCGv t = tcg_temp_new();
309 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
310 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
311 tcg_temp_free(t);
312 } else
313 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
314 }
315
316 static void dec_or(DisasContext *dc)
317 {
318 if (!dc->type_b && (dc->imm & (1 << 10))) {
319 dec_pattern(dc);
320 return;
321 }
322
323 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
324 if (dc->rd)
325 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
326 }
327
328 static void dec_xor(DisasContext *dc)
329 {
330 if (!dc->type_b && (dc->imm & (1 << 10))) {
331 dec_pattern(dc);
332 return;
333 }
334
335 LOG_DIS("xor r%d\n", dc->rd);
336 if (dc->rd)
337 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
338 }
339
340 static void read_carry(DisasContext *dc, TCGv d)
341 {
342 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
343 }
344
345 static void write_carry(DisasContext *dc, TCGv v)
346 {
347 TCGv t0 = tcg_temp_new();
348 tcg_gen_shli_tl(t0, v, 31);
349 tcg_gen_sari_tl(t0, t0, 31);
350 tcg_gen_mov_tl(env_debug, t0);
351 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
352 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
353 ~(MSR_C | MSR_CC));
354 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
355 tcg_temp_free(t0);
356 }
357
358
359 static inline void msr_read(DisasContext *dc, TCGv d)
360 {
361 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
362 }
363
364 static inline void msr_write(DisasContext *dc, TCGv v)
365 {
366 dc->cpustate_changed = 1;
367 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
368 /* PVR, we have a processor version register. */
369 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
370 }
371
372 static void dec_msr(DisasContext *dc)
373 {
374 TCGv t0, t1;
375 unsigned int sr, to, rn;
376 int mem_index = cpu_mmu_index(dc->env);
377
378 sr = dc->imm & ((1 << 14) - 1);
379 to = dc->imm & (1 << 14);
380 dc->type_b = 1;
381 if (to)
382 dc->cpustate_changed = 1;
383
384 /* msrclr and msrset. */
385 if (!(dc->imm & (1 << 15))) {
386 unsigned int clr = dc->ir & (1 << 16);
387
388 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
389 dc->rd, dc->imm);
390
391 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
392 /* nop??? */
393 return;
394 }
395
396 if ((dc->tb_flags & MSR_EE_FLAG)
397 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
398 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
399 t_gen_raise_exception(dc, EXCP_HW_EXCP);
400 return;
401 }
402
403 if (dc->rd)
404 msr_read(dc, cpu_R[dc->rd]);
405
406 t0 = tcg_temp_new();
407 t1 = tcg_temp_new();
408 msr_read(dc, t0);
409 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
410
411 if (clr) {
412 tcg_gen_not_tl(t1, t1);
413 tcg_gen_and_tl(t0, t0, t1);
414 } else
415 tcg_gen_or_tl(t0, t0, t1);
416 msr_write(dc, t0);
417 tcg_temp_free(t0);
418 tcg_temp_free(t1);
419 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
420 dc->is_jmp = DISAS_UPDATE;
421 return;
422 }
423
424 if (to) {
425 if ((dc->tb_flags & MSR_EE_FLAG)
426 && mem_index == MMU_USER_IDX) {
427 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
428 t_gen_raise_exception(dc, EXCP_HW_EXCP);
429 return;
430 }
431 }
432
433 #if !defined(CONFIG_USER_ONLY)
434 /* Catch read/writes to the mmu block. */
435 if ((sr & ~0xff) == 0x1000) {
436 sr &= 7;
437 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
438 if (to)
439 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
440 else
441 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
442 return;
443 }
444 #endif
445
446 if (to) {
447 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
448 switch (sr) {
449 case 0:
450 break;
451 case 1:
452 msr_write(dc, cpu_R[dc->ra]);
453 break;
454 case 0x3:
455 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
456 break;
457 case 0x5:
458 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
459 break;
460 case 0x7:
461 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
462 break;
463 default:
464 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
465 break;
466 }
467 } else {
468 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
469
470 switch (sr) {
471 case 0:
472 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
473 break;
474 case 1:
475 msr_read(dc, cpu_R[dc->rd]);
476 break;
477 case 0x3:
478 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
479 break;
480 case 0x5:
481 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
482 break;
483 case 0x7:
484 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
485 break;
486 case 0xb:
487 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
488 break;
489 case 0x2000:
490 case 0x2001:
491 case 0x2002:
492 case 0x2003:
493 case 0x2004:
494 case 0x2005:
495 case 0x2006:
496 case 0x2007:
497 case 0x2008:
498 case 0x2009:
499 case 0x200a:
500 case 0x200b:
501 case 0x200c:
502 rn = sr & 0xf;
503 tcg_gen_ld_tl(cpu_R[dc->rd],
504 cpu_env, offsetof(CPUState, pvr.regs[rn]));
505 break;
506 default:
507 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
508 break;
509 }
510 }
511
512 if (dc->rd == 0) {
513 tcg_gen_movi_tl(cpu_R[0], 0);
514 }
515 }
516
517 /* 64-bit signed mul, lower result in d and upper in d2. */
518 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
519 {
520 TCGv_i64 t0, t1;
521
522 t0 = tcg_temp_new_i64();
523 t1 = tcg_temp_new_i64();
524
525 tcg_gen_ext_i32_i64(t0, a);
526 tcg_gen_ext_i32_i64(t1, b);
527 tcg_gen_mul_i64(t0, t0, t1);
528
529 tcg_gen_trunc_i64_i32(d, t0);
530 tcg_gen_shri_i64(t0, t0, 32);
531 tcg_gen_trunc_i64_i32(d2, t0);
532
533 tcg_temp_free_i64(t0);
534 tcg_temp_free_i64(t1);
535 }
536
537 /* 64-bit unsigned muls, lower result in d and upper in d2. */
538 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
539 {
540 TCGv_i64 t0, t1;
541
542 t0 = tcg_temp_new_i64();
543 t1 = tcg_temp_new_i64();
544
545 tcg_gen_extu_i32_i64(t0, a);
546 tcg_gen_extu_i32_i64(t1, b);
547 tcg_gen_mul_i64(t0, t0, t1);
548
549 tcg_gen_trunc_i64_i32(d, t0);
550 tcg_gen_shri_i64(t0, t0, 32);
551 tcg_gen_trunc_i64_i32(d2, t0);
552
553 tcg_temp_free_i64(t0);
554 tcg_temp_free_i64(t1);
555 }
556
557 /* Multiplier unit. */
558 static void dec_mul(DisasContext *dc)
559 {
560 TCGv d[2];
561 unsigned int subcode;
562
563 if ((dc->tb_flags & MSR_EE_FLAG)
564 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
565 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
566 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
567 t_gen_raise_exception(dc, EXCP_HW_EXCP);
568 return;
569 }
570
571 subcode = dc->imm & 3;
572 d[0] = tcg_temp_new();
573 d[1] = tcg_temp_new();
574
575 if (dc->type_b) {
576 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
577 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
578 goto done;
579 }
580
581 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
582 if (subcode >= 1 && subcode <= 3
583 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
584 /* nop??? */
585 }
586
587 switch (subcode) {
588 case 0:
589 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
590 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
591 break;
592 case 1:
593 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
594 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
595 break;
596 case 2:
597 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
598 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
599 break;
600 case 3:
601 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
602 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
603 break;
604 default:
605 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
606 break;
607 }
608 done:
609 tcg_temp_free(d[0]);
610 tcg_temp_free(d[1]);
611 }
612
613 /* Div unit. */
614 static void dec_div(DisasContext *dc)
615 {
616 unsigned int u;
617
618 u = dc->imm & 2;
619 LOG_DIS("div\n");
620
621 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
622 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
623 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
624 t_gen_raise_exception(dc, EXCP_HW_EXCP);
625 }
626
627 if (u)
628 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
629 else
630 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
631 if (!dc->rd)
632 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
633 }
634
635 static void dec_barrel(DisasContext *dc)
636 {
637 TCGv t0;
638 unsigned int s, t;
639
640 if ((dc->tb_flags & MSR_EE_FLAG)
641 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
642 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
643 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
644 t_gen_raise_exception(dc, EXCP_HW_EXCP);
645 return;
646 }
647
648 s = dc->imm & (1 << 10);
649 t = dc->imm & (1 << 9);
650
651 LOG_DIS("bs%s%s r%d r%d r%d\n",
652 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
653
654 t0 = tcg_temp_new();
655
656 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
657 tcg_gen_andi_tl(t0, t0, 31);
658
659 if (s)
660 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
661 else {
662 if (t)
663 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
664 else
665 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
666 }
667 }
668
669 static void dec_bit(DisasContext *dc)
670 {
671 TCGv t0, t1;
672 unsigned int op;
673 int mem_index = cpu_mmu_index(dc->env);
674
675 op = dc->ir & ((1 << 8) - 1);
676 switch (op) {
677 case 0x21:
678 /* src. */
679 t0 = tcg_temp_new();
680
681 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
682 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
683 if (dc->rd) {
684 t1 = tcg_temp_new();
685 read_carry(dc, t1);
686 tcg_gen_shli_tl(t1, t1, 31);
687
688 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
689 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
690 tcg_temp_free(t1);
691 }
692
693 /* Update carry. */
694 write_carry(dc, t0);
695 tcg_temp_free(t0);
696 break;
697
698 case 0x1:
699 case 0x41:
700 /* srl. */
701 t0 = tcg_temp_new();
702 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
703
704 /* Update carry. */
705 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
706 write_carry(dc, t0);
707 tcg_temp_free(t0);
708 if (dc->rd) {
709 if (op == 0x41)
710 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
711 else
712 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
713 }
714 break;
715 case 0x60:
716 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
717 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
718 break;
719 case 0x61:
720 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
721 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
722 break;
723 case 0x64:
724 case 0x66:
725 case 0x74:
726 case 0x76:
727 /* wdc. */
728 LOG_DIS("wdc r%d\n", dc->ra);
729 if ((dc->tb_flags & MSR_EE_FLAG)
730 && mem_index == MMU_USER_IDX) {
731 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
732 t_gen_raise_exception(dc, EXCP_HW_EXCP);
733 return;
734 }
735 break;
736 case 0x68:
737 /* wic. */
738 LOG_DIS("wic r%d\n", dc->ra);
739 if ((dc->tb_flags & MSR_EE_FLAG)
740 && mem_index == MMU_USER_IDX) {
741 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
742 t_gen_raise_exception(dc, EXCP_HW_EXCP);
743 return;
744 }
745 break;
746 default:
747 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
748 dc->pc, op, dc->rd, dc->ra, dc->rb);
749 break;
750 }
751 }
752
753 static inline void sync_jmpstate(DisasContext *dc)
754 {
755 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
756 if (dc->jmp == JMP_DIRECT) {
757 tcg_gen_movi_tl(env_btaken, 1);
758 }
759 dc->jmp = JMP_INDIRECT;
760 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
761 }
762 }
763
764 static void dec_imm(DisasContext *dc)
765 {
766 LOG_DIS("imm %x\n", dc->imm << 16);
767 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
768 dc->tb_flags |= IMM_FLAG;
769 dc->clear_imm = 0;
770 }
771
772 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
773 unsigned int size)
774 {
775 int mem_index = cpu_mmu_index(dc->env);
776
777 if (size == 1) {
778 tcg_gen_qemu_ld8u(dst, addr, mem_index);
779 } else if (size == 2) {
780 tcg_gen_qemu_ld16u(dst, addr, mem_index);
781 } else if (size == 4) {
782 tcg_gen_qemu_ld32u(dst, addr, mem_index);
783 } else
784 cpu_abort(dc->env, "Incorrect load size %d\n", size);
785 }
786
787 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
788 {
789 unsigned int extimm = dc->tb_flags & IMM_FLAG;
790
791 /* Treat the fast cases first. */
792 if (!dc->type_b) {
793 /* If any of the regs is r0, return a ptr to the other. */
794 if (dc->ra == 0) {
795 return &cpu_R[dc->rb];
796 } else if (dc->rb == 0) {
797 return &cpu_R[dc->ra];
798 }
799
800 *t = tcg_temp_new();
801 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
802 return t;
803 }
804 /* Immediate. */
805 if (!extimm) {
806 if (dc->imm == 0) {
807 return &cpu_R[dc->ra];
808 }
809 *t = tcg_temp_new();
810 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
811 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
812 } else {
813 *t = tcg_temp_new();
814 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
815 }
816
817 return t;
818 }
819
820 static void dec_load(DisasContext *dc)
821 {
822 TCGv t, *addr;
823 unsigned int size;
824
825 size = 1 << (dc->opcode & 3);
826 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
827 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
828 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
829 t_gen_raise_exception(dc, EXCP_HW_EXCP);
830 return;
831 }
832
833 LOG_DIS("l %x %d\n", dc->opcode, size);
834 t_sync_flags(dc);
835 addr = compute_ldst_addr(dc, &t);
836
837 /* If we get a fault on a dslot, the jmpstate better be in sync. */
838 sync_jmpstate(dc);
839
840 /* Verify alignment if needed. */
841 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
842 TCGv v = tcg_temp_new();
843
844 /*
845 * Microblaze gives MMU faults priority over faults due to
846 * unaligned addresses. That's why we speculatively do the load
847 * into v. If the load succeeds, we verify alignment of the
848 * address and if that succeeds we write into the destination reg.
849 */
850 gen_load(dc, v, *addr, size);
851
852 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
853 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
854 tcg_const_tl(0), tcg_const_tl(size - 1));
855 if (dc->rd)
856 tcg_gen_mov_tl(cpu_R[dc->rd], v);
857 tcg_temp_free(v);
858 } else {
859 if (dc->rd) {
860 gen_load(dc, cpu_R[dc->rd], *addr, size);
861 } else {
862 gen_load(dc, env_imm, *addr, size);
863 }
864 }
865
866 if (addr == &t)
867 tcg_temp_free(t);
868 }
869
870 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
871 unsigned int size)
872 {
873 int mem_index = cpu_mmu_index(dc->env);
874
875 if (size == 1)
876 tcg_gen_qemu_st8(val, addr, mem_index);
877 else if (size == 2) {
878 tcg_gen_qemu_st16(val, addr, mem_index);
879 } else if (size == 4) {
880 tcg_gen_qemu_st32(val, addr, mem_index);
881 } else
882 cpu_abort(dc->env, "Incorrect store size %d\n", size);
883 }
884
885 static void dec_store(DisasContext *dc)
886 {
887 TCGv t, *addr;
888 unsigned int size;
889
890 size = 1 << (dc->opcode & 3);
891
892 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
893 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
894 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
895 t_gen_raise_exception(dc, EXCP_HW_EXCP);
896 return;
897 }
898
899 LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");
900 t_sync_flags(dc);
901 /* If we get a fault on a dslot, the jmpstate better be in sync. */
902 sync_jmpstate(dc);
903 addr = compute_ldst_addr(dc, &t);
904
905 gen_store(dc, *addr, cpu_R[dc->rd], size);
906
907 /* Verify alignment if needed. */
908 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
909 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
910 /* FIXME: if the alignment is wrong, we should restore the value
911 * in memory.
912 */
913 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
914 tcg_const_tl(1), tcg_const_tl(size - 1));
915 }
916
917 if (addr == &t)
918 tcg_temp_free(t);
919 }
920
921 static inline void eval_cc(DisasContext *dc, unsigned int cc,
922 TCGv d, TCGv a, TCGv b)
923 {
924 switch (cc) {
925 case CC_EQ:
926 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
927 break;
928 case CC_NE:
929 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
930 break;
931 case CC_LT:
932 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
933 break;
934 case CC_LE:
935 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
936 break;
937 case CC_GE:
938 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
939 break;
940 case CC_GT:
941 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
942 break;
943 default:
944 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
945 break;
946 }
947 }
948
949 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
950 {
951 int l1;
952
953 l1 = gen_new_label();
954 /* Conditional jmp. */
955 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
956 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
957 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
958 gen_set_label(l1);
959 }
960
961 static void dec_bcc(DisasContext *dc)
962 {
963 unsigned int cc;
964 unsigned int dslot;
965
966 cc = EXTRACT_FIELD(dc->ir, 21, 23);
967 dslot = dc->ir & (1 << 25);
968 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
969
970 dc->delayed_branch = 1;
971 if (dslot) {
972 dc->delayed_branch = 2;
973 dc->tb_flags |= D_FLAG;
974 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
975 cpu_env, offsetof(CPUState, bimm));
976 }
977
978 if (dec_alu_op_b_is_small_imm(dc)) {
979 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
980
981 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
982 dc->jmp = JMP_DIRECT_CC;
983 dc->jmp_pc = dc->pc + offset;
984 } else {
985 dc->jmp = JMP_INDIRECT;
986 tcg_gen_movi_tl(env_btarget, dc->pc);
987 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
988 }
989 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
990 }
991
992 static void dec_br(DisasContext *dc)
993 {
994 unsigned int dslot, link, abs;
995 int mem_index = cpu_mmu_index(dc->env);
996
997 dslot = dc->ir & (1 << 20);
998 abs = dc->ir & (1 << 19);
999 link = dc->ir & (1 << 18);
1000 LOG_DIS("br%s%s%s%s imm=%x\n",
1001 abs ? "a" : "", link ? "l" : "",
1002 dc->type_b ? "i" : "", dslot ? "d" : "",
1003 dc->imm);
1004
1005 dc->delayed_branch = 1;
1006 if (dslot) {
1007 dc->delayed_branch = 2;
1008 dc->tb_flags |= D_FLAG;
1009 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1010 cpu_env, offsetof(CPUState, bimm));
1011 }
1012 if (link && dc->rd)
1013 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1014
1015 dc->jmp = JMP_INDIRECT;
1016 if (abs) {
1017 tcg_gen_movi_tl(env_btaken, 1);
1018 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1019 if (link && !dslot) {
1020 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1021 t_gen_raise_exception(dc, EXCP_BREAK);
1022 if (dc->imm == 0) {
1023 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1024 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1025 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1026 return;
1027 }
1028
1029 t_gen_raise_exception(dc, EXCP_DEBUG);
1030 }
1031 }
1032 } else {
1033 if (dec_alu_op_b_is_small_imm(dc)) {
1034 dc->jmp = JMP_DIRECT;
1035 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1036 } else {
1037 tcg_gen_movi_tl(env_btaken, 1);
1038 tcg_gen_movi_tl(env_btarget, dc->pc);
1039 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1040 }
1041 }
1042 }
1043
1044 static inline void do_rti(DisasContext *dc)
1045 {
1046 TCGv t0, t1;
1047 t0 = tcg_temp_new();
1048 t1 = tcg_temp_new();
1049 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1050 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1051 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1052
1053 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1054 tcg_gen_or_tl(t1, t1, t0);
1055 msr_write(dc, t1);
1056 tcg_temp_free(t1);
1057 tcg_temp_free(t0);
1058 dc->tb_flags &= ~DRTI_FLAG;
1059 }
1060
1061 static inline void do_rtb(DisasContext *dc)
1062 {
1063 TCGv t0, t1;
1064 t0 = tcg_temp_new();
1065 t1 = tcg_temp_new();
1066 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1067 tcg_gen_shri_tl(t0, t1, 1);
1068 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1069
1070 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1071 tcg_gen_or_tl(t1, t1, t0);
1072 msr_write(dc, t1);
1073 tcg_temp_free(t1);
1074 tcg_temp_free(t0);
1075 dc->tb_flags &= ~DRTB_FLAG;
1076 }
1077
1078 static inline void do_rte(DisasContext *dc)
1079 {
1080 TCGv t0, t1;
1081 t0 = tcg_temp_new();
1082 t1 = tcg_temp_new();
1083
1084 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1085 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1086 tcg_gen_shri_tl(t0, t1, 1);
1087 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1088
1089 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1090 tcg_gen_or_tl(t1, t1, t0);
1091 msr_write(dc, t1);
1092 tcg_temp_free(t1);
1093 tcg_temp_free(t0);
1094 dc->tb_flags &= ~DRTE_FLAG;
1095 }
1096
1097 static void dec_rts(DisasContext *dc)
1098 {
1099 unsigned int b_bit, i_bit, e_bit;
1100 int mem_index = cpu_mmu_index(dc->env);
1101
1102 i_bit = dc->ir & (1 << 21);
1103 b_bit = dc->ir & (1 << 22);
1104 e_bit = dc->ir & (1 << 23);
1105
1106 dc->delayed_branch = 2;
1107 dc->tb_flags |= D_FLAG;
1108 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1109 cpu_env, offsetof(CPUState, bimm));
1110
1111 if (i_bit) {
1112 LOG_DIS("rtid ir=%x\n", dc->ir);
1113 if ((dc->tb_flags & MSR_EE_FLAG)
1114 && mem_index == MMU_USER_IDX) {
1115 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1116 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1117 }
1118 dc->tb_flags |= DRTI_FLAG;
1119 } else if (b_bit) {
1120 LOG_DIS("rtbd ir=%x\n", dc->ir);
1121 if ((dc->tb_flags & MSR_EE_FLAG)
1122 && mem_index == MMU_USER_IDX) {
1123 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1124 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1125 }
1126 dc->tb_flags |= DRTB_FLAG;
1127 } else if (e_bit) {
1128 LOG_DIS("rted ir=%x\n", dc->ir);
1129 if ((dc->tb_flags & MSR_EE_FLAG)
1130 && mem_index == MMU_USER_IDX) {
1131 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1132 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1133 }
1134 dc->tb_flags |= DRTE_FLAG;
1135 } else
1136 LOG_DIS("rts ir=%x\n", dc->ir);
1137
1138 dc->jmp = JMP_INDIRECT;
1139 tcg_gen_movi_tl(env_btaken, 1);
1140 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1141 }
1142
1143 static int dec_check_fpuv2(DisasContext *dc)
1144 {
1145 int r;
1146
1147 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1148
1149 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1150 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1151 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1152 }
1153 return r;
1154 }
1155
1156 static void dec_fpu(DisasContext *dc)
1157 {
1158 unsigned int fpu_insn;
1159
1160 if ((dc->tb_flags & MSR_EE_FLAG)
1161 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1162 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1163 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1164 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1165 return;
1166 }
1167
1168 fpu_insn = (dc->ir >> 7) & 7;
1169
1170 switch (fpu_insn) {
1171 case 0:
1172 gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1173 break;
1174
1175 case 1:
1176 gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1177 break;
1178
1179 case 2:
1180 gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1181 break;
1182
1183 case 3:
1184 gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1185 break;
1186
1187 case 4:
1188 switch ((dc->ir >> 4) & 7) {
1189 case 0:
1190 gen_helper_fcmp_un(cpu_R[dc->rd],
1191 cpu_R[dc->ra], cpu_R[dc->rb]);
1192 break;
1193 case 1:
1194 gen_helper_fcmp_lt(cpu_R[dc->rd],
1195 cpu_R[dc->ra], cpu_R[dc->rb]);
1196 break;
1197 case 2:
1198 gen_helper_fcmp_eq(cpu_R[dc->rd],
1199 cpu_R[dc->ra], cpu_R[dc->rb]);
1200 break;
1201 case 3:
1202 gen_helper_fcmp_le(cpu_R[dc->rd],
1203 cpu_R[dc->ra], cpu_R[dc->rb]);
1204 break;
1205 case 4:
1206 gen_helper_fcmp_gt(cpu_R[dc->rd],
1207 cpu_R[dc->ra], cpu_R[dc->rb]);
1208 break;
1209 case 5:
1210 gen_helper_fcmp_ne(cpu_R[dc->rd],
1211 cpu_R[dc->ra], cpu_R[dc->rb]);
1212 break;
1213 case 6:
1214 gen_helper_fcmp_ge(cpu_R[dc->rd],
1215 cpu_R[dc->ra], cpu_R[dc->rb]);
1216 break;
1217 default:
1218 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1219 fpu_insn, dc->pc, dc->opcode);
1220 dc->abort_at_next_insn = 1;
1221 break;
1222 }
1223 break;
1224
1225 case 5:
1226 if (!dec_check_fpuv2(dc)) {
1227 return;
1228 }
1229 gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
1230 break;
1231
1232 case 6:
1233 if (!dec_check_fpuv2(dc)) {
1234 return;
1235 }
1236 gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
1237 break;
1238
1239 case 7:
1240 if (!dec_check_fpuv2(dc)) {
1241 return;
1242 }
1243 gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
1244 break;
1245
1246 default:
1247 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1248 fpu_insn, dc->pc, dc->opcode);
1249 dc->abort_at_next_insn = 1;
1250 break;
1251 }
1252 }
1253
1254 static void dec_null(DisasContext *dc)
1255 {
1256 if ((dc->tb_flags & MSR_EE_FLAG)
1257 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1258 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1259 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1260 return;
1261 }
1262 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1263 dc->abort_at_next_insn = 1;
1264 }
1265
1266 static struct decoder_info {
1267 struct {
1268 uint32_t bits;
1269 uint32_t mask;
1270 };
1271 void (*dec)(DisasContext *dc);
1272 } decinfo[] = {
1273 {DEC_ADD, dec_add},
1274 {DEC_SUB, dec_sub},
1275 {DEC_AND, dec_and},
1276 {DEC_XOR, dec_xor},
1277 {DEC_OR, dec_or},
1278 {DEC_BIT, dec_bit},
1279 {DEC_BARREL, dec_barrel},
1280 {DEC_LD, dec_load},
1281 {DEC_ST, dec_store},
1282 {DEC_IMM, dec_imm},
1283 {DEC_BR, dec_br},
1284 {DEC_BCC, dec_bcc},
1285 {DEC_RTS, dec_rts},
1286 {DEC_FPU, dec_fpu},
1287 {DEC_MUL, dec_mul},
1288 {DEC_DIV, dec_div},
1289 {DEC_MSR, dec_msr},
1290 {{0, 0}, dec_null}
1291 };
1292
1293 static inline void decode(DisasContext *dc)
1294 {
1295 uint32_t ir;
1296 int i;
1297
1298 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1299 tcg_gen_debug_insn_start(dc->pc);
1300
1301 dc->ir = ir = ldl_code(dc->pc);
1302 LOG_DIS("%8.8x\t", dc->ir);
1303
1304 if (dc->ir)
1305 dc->nr_nops = 0;
1306 else {
1307 if ((dc->tb_flags & MSR_EE_FLAG)
1308 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1309 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1310 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1311 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1312 return;
1313 }
1314
1315 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1316 dc->nr_nops++;
1317 if (dc->nr_nops > 4)
1318 cpu_abort(dc->env, "fetching nop sequence\n");
1319 }
1320 /* bit 2 seems to indicate insn type. */
1321 dc->type_b = ir & (1 << 29);
1322
1323 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1324 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1325 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1326 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1327 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1328
1329 /* Large switch for all insns. */
1330 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1331 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1332 decinfo[i].dec(dc);
1333 break;
1334 }
1335 }
1336 }
1337
1338 static void check_breakpoint(CPUState *env, DisasContext *dc)
1339 {
1340 CPUBreakpoint *bp;
1341
1342 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1343 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1344 if (bp->pc == dc->pc) {
1345 t_gen_raise_exception(dc, EXCP_DEBUG);
1346 dc->is_jmp = DISAS_UPDATE;
1347 }
1348 }
1349 }
1350 }
1351
1352 /* generate intermediate code for basic block 'tb'. */
1353 static void
1354 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1355 int search_pc)
1356 {
1357 uint16_t *gen_opc_end;
1358 uint32_t pc_start;
1359 int j, lj;
1360 struct DisasContext ctx;
1361 struct DisasContext *dc = &ctx;
1362 uint32_t next_page_start, org_flags;
1363 target_ulong npc;
1364 int num_insns;
1365 int max_insns;
1366
1367 qemu_log_try_set_file(stderr);
1368
1369 pc_start = tb->pc;
1370 dc->env = env;
1371 dc->tb = tb;
1372 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1373
1374 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1375
1376 dc->is_jmp = DISAS_NEXT;
1377 dc->jmp = 0;
1378 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1379 if (dc->delayed_branch) {
1380 dc->jmp = JMP_INDIRECT;
1381 }
1382 dc->pc = pc_start;
1383 dc->singlestep_enabled = env->singlestep_enabled;
1384 dc->cpustate_changed = 0;
1385 dc->abort_at_next_insn = 0;
1386 dc->nr_nops = 0;
1387
1388 if (pc_start & 3)
1389 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1390
1391 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1392 #if !SIM_COMPAT
1393 qemu_log("--------------\n");
1394 log_cpu_state(env, 0);
1395 #endif
1396 }
1397
1398 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1399 lj = -1;
1400 num_insns = 0;
1401 max_insns = tb->cflags & CF_COUNT_MASK;
1402 if (max_insns == 0)
1403 max_insns = CF_COUNT_MASK;
1404
1405 gen_icount_start();
1406 do
1407 {
1408 #if SIM_COMPAT
1409 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1410 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1411 gen_helper_debug();
1412 }
1413 #endif
1414 check_breakpoint(env, dc);
1415
1416 if (search_pc) {
1417 j = gen_opc_ptr - gen_opc_buf;
1418 if (lj < j) {
1419 lj++;
1420 while (lj < j)
1421 gen_opc_instr_start[lj++] = 0;
1422 }
1423 gen_opc_pc[lj] = dc->pc;
1424 gen_opc_instr_start[lj] = 1;
1425 gen_opc_icount[lj] = num_insns;
1426 }
1427
1428 /* Pretty disas. */
1429 LOG_DIS("%8.8x:\t", dc->pc);
1430
1431 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1432 gen_io_start();
1433
1434 dc->clear_imm = 1;
1435 decode(dc);
1436 if (dc->clear_imm)
1437 dc->tb_flags &= ~IMM_FLAG;
1438 dc->pc += 4;
1439 num_insns++;
1440
1441 if (dc->delayed_branch) {
1442 dc->delayed_branch--;
1443 if (!dc->delayed_branch) {
1444 if (dc->tb_flags & DRTI_FLAG)
1445 do_rti(dc);
1446 if (dc->tb_flags & DRTB_FLAG)
1447 do_rtb(dc);
1448 if (dc->tb_flags & DRTE_FLAG)
1449 do_rte(dc);
1450 /* Clear the delay slot flag. */
1451 dc->tb_flags &= ~D_FLAG;
1452 /* If it is a direct jump, try direct chaining. */
1453 if (dc->jmp == JMP_INDIRECT) {
1454 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1455 dc->is_jmp = DISAS_JUMP;
1456 } else if (dc->jmp == JMP_DIRECT) {
1457 t_sync_flags(dc);
1458 gen_goto_tb(dc, 0, dc->jmp_pc);
1459 dc->is_jmp = DISAS_TB_JUMP;
1460 } else if (dc->jmp == JMP_DIRECT_CC) {
1461 int l1;
1462
1463 t_sync_flags(dc);
1464 l1 = gen_new_label();
1465 /* Conditional jmp. */
1466 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1467 gen_goto_tb(dc, 1, dc->pc);
1468 gen_set_label(l1);
1469 gen_goto_tb(dc, 0, dc->jmp_pc);
1470
1471 dc->is_jmp = DISAS_TB_JUMP;
1472 }
1473 break;
1474 }
1475 }
1476 if (env->singlestep_enabled)
1477 break;
1478 } while (!dc->is_jmp && !dc->cpustate_changed
1479 && gen_opc_ptr < gen_opc_end
1480 && !singlestep
1481 && (dc->pc < next_page_start)
1482 && num_insns < max_insns);
1483
1484 npc = dc->pc;
1485 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1486 if (dc->tb_flags & D_FLAG) {
1487 dc->is_jmp = DISAS_UPDATE;
1488 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1489 sync_jmpstate(dc);
1490 } else
1491 npc = dc->jmp_pc;
1492 }
1493
1494 if (tb->cflags & CF_LAST_IO)
1495 gen_io_end();
1496 /* Force an update if the per-tb cpu state has changed. */
1497 if (dc->is_jmp == DISAS_NEXT
1498 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1499 dc->is_jmp = DISAS_UPDATE;
1500 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1501 }
1502 t_sync_flags(dc);
1503
1504 if (unlikely(env->singlestep_enabled)) {
1505 t_gen_raise_exception(dc, EXCP_DEBUG);
1506 if (dc->is_jmp == DISAS_NEXT)
1507 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1508 } else {
1509 switch(dc->is_jmp) {
1510 case DISAS_NEXT:
1511 gen_goto_tb(dc, 1, npc);
1512 break;
1513 default:
1514 case DISAS_JUMP:
1515 case DISAS_UPDATE:
1516 /* indicate that the hash table must be used
1517 to find the next TB */
1518 tcg_gen_exit_tb(0);
1519 break;
1520 case DISAS_TB_JUMP:
1521 /* nothing more to generate */
1522 break;
1523 }
1524 }
1525 gen_icount_end(tb, num_insns);
1526 *gen_opc_ptr = INDEX_op_end;
1527 if (search_pc) {
1528 j = gen_opc_ptr - gen_opc_buf;
1529 lj++;
1530 while (lj <= j)
1531 gen_opc_instr_start[lj++] = 0;
1532 } else {
1533 tb->size = dc->pc - pc_start;
1534 tb->icount = num_insns;
1535 }
1536
1537 #ifdef DEBUG_DISAS
1538 #if !SIM_COMPAT
1539 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1540 qemu_log("\n");
1541 #if DISAS_GNU
1542 log_target_disas(pc_start, dc->pc - pc_start, 0);
1543 #endif
1544 qemu_log("\nisize=%d osize=%td\n",
1545 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1546 }
1547 #endif
1548 #endif
1549 assert(!dc->abort_at_next_insn);
1550 }
1551
1552 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1553 {
1554 gen_intermediate_code_internal(env, tb, 0);
1555 }
1556
1557 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1558 {
1559 gen_intermediate_code_internal(env, tb, 1);
1560 }
1561
1562 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1563 int flags)
1564 {
1565 int i;
1566
1567 if (!env || !f)
1568 return;
1569
1570 cpu_fprintf(f, "IN: PC=%x %s\n",
1571 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1572 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1573 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1574 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1575 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1576 env->btaken, env->btarget,
1577 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1578 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1579 (env->sregs[SR_MSR] & MSR_EIP),
1580 (env->sregs[SR_MSR] & MSR_IE));
1581
1582 for (i = 0; i < 32; i++) {
1583 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1584 if ((i + 1) % 4 == 0)
1585 cpu_fprintf(f, "\n");
1586 }
1587 cpu_fprintf(f, "\n\n");
1588 }
1589
1590 CPUState *cpu_mb_init (const char *cpu_model)
1591 {
1592 CPUState *env;
1593 static int tcg_initialized = 0;
1594 int i;
1595
1596 env = qemu_mallocz(sizeof(CPUState));
1597
1598 cpu_exec_init(env);
1599 cpu_reset(env);
1600 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1601
1602 if (tcg_initialized)
1603 return env;
1604
1605 tcg_initialized = 1;
1606
1607 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1608
1609 env_debug = tcg_global_mem_new(TCG_AREG0,
1610 offsetof(CPUState, debug),
1611 "debug0");
1612 env_iflags = tcg_global_mem_new(TCG_AREG0,
1613 offsetof(CPUState, iflags),
1614 "iflags");
1615 env_imm = tcg_global_mem_new(TCG_AREG0,
1616 offsetof(CPUState, imm),
1617 "imm");
1618 env_btarget = tcg_global_mem_new(TCG_AREG0,
1619 offsetof(CPUState, btarget),
1620 "btarget");
1621 env_btaken = tcg_global_mem_new(TCG_AREG0,
1622 offsetof(CPUState, btaken),
1623 "btaken");
1624 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1625 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1626 offsetof(CPUState, regs[i]),
1627 regnames[i]);
1628 }
1629 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1630 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1631 offsetof(CPUState, sregs[i]),
1632 special_regnames[i]);
1633 }
1634 #define GEN_HELPER 2
1635 #include "helper.h"
1636
1637 return env;
1638 }
1639
1640 void cpu_reset (CPUState *env)
1641 {
1642 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1643 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1644 log_cpu_state(env, 0);
1645 }
1646
1647 memset(env, 0, offsetof(CPUMBState, breakpoints));
1648 tlb_flush(env, 1);
1649
1650 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1651 | PVR0_USE_BARREL_MASK \
1652 | PVR0_USE_DIV_MASK \
1653 | PVR0_USE_HW_MUL_MASK \
1654 | PVR0_USE_EXC_MASK \
1655 | PVR0_USE_ICACHE_MASK \
1656 | PVR0_USE_DCACHE_MASK \
1657 | PVR0_USE_MMU \
1658 | (0xb << 8);
1659 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1660 | PVR2_D_LMB_MASK \
1661 | PVR2_I_OPB_MASK \
1662 | PVR2_I_LMB_MASK \
1663 | PVR2_USE_MSR_INSTR \
1664 | PVR2_USE_PCMP_INSTR \
1665 | PVR2_USE_BARREL_MASK \
1666 | PVR2_USE_DIV_MASK \
1667 | PVR2_USE_HW_MUL_MASK \
1668 | PVR2_USE_MUL64_MASK \
1669 | PVR2_USE_FPU_MASK \
1670 | PVR2_USE_FPU2_MASK \
1671 | PVR2_FPU_EXC_MASK \
1672 | 0;
1673 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1674 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1675
1676 #if defined(CONFIG_USER_ONLY)
1677 /* start in user mode with interrupts enabled. */
1678 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
1679 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1680 #else
1681 env->sregs[SR_MSR] = 0;
1682 mmu_init(&env->mmu);
1683 env->mmu.c_mmu = 3;
1684 env->mmu.c_mmu_tlb_access = 3;
1685 env->mmu.c_mmu_zones = 16;
1686 #endif
1687 }
1688
1689 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1690 unsigned long searched_pc, int pc_pos, void *puc)
1691 {
1692 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1693 }
Qemu with PowerPC KVM improvements