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PPC: Fix large pages
[qemu/agraf.git] / target-microblaze / translate.c
blob583f09d7b4b44f0ff80b2fc3bf0b63663293dc36
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "helper.h"
32 #include "microblaze-decode.h"
33 #include "qemu-common.h"
34
35 #define GEN_HELPER 1
36 #include "helper.h"
37
38 #define SIM_COMPAT 0
39 #define DISAS_GNU 1
40 #define DISAS_MB 1
41 #if DISAS_MB && !SIM_COMPAT
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DIS(...) do { } while (0)
45 #endif
46
47 #define D(x)
48
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52 static TCGv env_debug;
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_R[32];
55 static TCGv cpu_SR[18];
56 static TCGv env_imm;
57 static TCGv env_btaken;
58 static TCGv env_btarget;
59 static TCGv env_iflags;
60
61 #include "gen-icount.h"
62
63 /* This is the state at translation time. */
64 typedef struct DisasContext {
65 CPUState *env;
66 target_ulong pc, ppc;
67 target_ulong cache_pc;
68
69 /* Decoder. */
70 int type_b;
71 uint32_t ir;
72 uint8_t opcode;
73 uint8_t rd, ra, rb;
74 uint16_t imm;
75
76 unsigned int cpustate_changed;
77 unsigned int delayed_branch;
78 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
79 unsigned int clear_imm;
80 int is_jmp;
81
82 #define JMP_NOJMP 0
83 #define JMP_DIRECT 1
84 #define JMP_INDIRECT 2
85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92 } DisasContext;
93
94 static const char *regnames[] =
95 {
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100 };
101
102 static const char *special_regnames[] =
103 {
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107 };
108
109 /* Sign extend at translation time. */
110 static inline int sign_extend(unsigned int val, unsigned int width)
111 {
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120 }
121
122 static inline void t_sync_flags(DisasContext *dc)
123 {
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129 }
130
131 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132 {
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140 }
141
142 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143 {
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154 }
155
156 static inline TCGv *dec_alu_op_b(DisasContext *dc)
157 {
158 if (dc->type_b) {
159 if (dc->tb_flags & IMM_FLAG)
160 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
161 else
162 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
163 return &env_imm;
164 } else
165 return &cpu_R[dc->rb];
166 }
167
168 static void dec_add(DisasContext *dc)
169 {
170 unsigned int k, c;
171
172 k = dc->opcode & 4;
173 c = dc->opcode & 2;
174
175 LOG_DIS("add%s%s%s r%d r%d r%d\n",
176 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
177 dc->rd, dc->ra, dc->rb);
178
179 if (k && !c && dc->rd)
180 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
181 else if (dc->rd)
182 gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
183 tcg_const_tl(k), tcg_const_tl(c));
184 else {
185 TCGv d = tcg_temp_new();
186 gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
187 tcg_const_tl(k), tcg_const_tl(c));
188 tcg_temp_free(d);
189 }
190 }
191
192 static void dec_sub(DisasContext *dc)
193 {
194 unsigned int u, cmp, k, c;
195
196 u = dc->imm & 2;
197 k = dc->opcode & 4;
198 c = dc->opcode & 2;
199 cmp = (dc->imm & 1) && (!dc->type_b) && k;
200
201 if (cmp) {
202 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
203 if (dc->rd) {
204 if (u)
205 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
206 else
207 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
208 }
209 } else {
210 LOG_DIS("sub%s%s r%d, r%d r%d\n",
211 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
212
213 if (!k || c) {
214 TCGv t;
215 t = tcg_temp_new();
216 if (dc->rd)
217 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
218 tcg_const_tl(k), tcg_const_tl(c));
219 else
220 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
221 tcg_const_tl(k), tcg_const_tl(c));
222 tcg_temp_free(t);
223 }
224 else if (dc->rd)
225 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
226 }
227 }
228
229 static void dec_pattern(DisasContext *dc)
230 {
231 unsigned int mode;
232 int l1;
233
234 if ((dc->tb_flags & MSR_EE_FLAG)
235 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
236 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
237 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
238 t_gen_raise_exception(dc, EXCP_HW_EXCP);
239 }
240
241 mode = dc->opcode & 3;
242 switch (mode) {
243 case 0:
244 /* pcmpbf. */
245 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
246 if (dc->rd)
247 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
248 break;
249 case 2:
250 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
251 if (dc->rd) {
252 TCGv t0 = tcg_temp_local_new();
253 l1 = gen_new_label();
254 tcg_gen_movi_tl(t0, 1);
255 tcg_gen_brcond_tl(TCG_COND_EQ,
256 cpu_R[dc->ra], cpu_R[dc->rb], l1);
257 tcg_gen_movi_tl(t0, 0);
258 gen_set_label(l1);
259 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
260 tcg_temp_free(t0);
261 }
262 break;
263 case 3:
264 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
265 l1 = gen_new_label();
266 if (dc->rd) {
267 TCGv t0 = tcg_temp_local_new();
268 tcg_gen_movi_tl(t0, 1);
269 tcg_gen_brcond_tl(TCG_COND_NE,
270 cpu_R[dc->ra], cpu_R[dc->rb], l1);
271 tcg_gen_movi_tl(t0, 0);
272 gen_set_label(l1);
273 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
274 tcg_temp_free(t0);
275 }
276 break;
277 default:
278 cpu_abort(dc->env,
279 "unsupported pattern insn opcode=%x\n", dc->opcode);
280 break;
281 }
282 }
283
284 static void dec_and(DisasContext *dc)
285 {
286 unsigned int not;
287
288 if (!dc->type_b && (dc->imm & (1 << 10))) {
289 dec_pattern(dc);
290 return;
291 }
292
293 not = dc->opcode & (1 << 1);
294 LOG_DIS("and%s\n", not ? "n" : "");
295
296 if (!dc->rd)
297 return;
298
299 if (not) {
300 TCGv t = tcg_temp_new();
301 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
302 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
303 tcg_temp_free(t);
304 } else
305 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
306 }
307
308 static void dec_or(DisasContext *dc)
309 {
310 if (!dc->type_b && (dc->imm & (1 << 10))) {
311 dec_pattern(dc);
312 return;
313 }
314
315 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
316 if (dc->rd)
317 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
318 }
319
320 static void dec_xor(DisasContext *dc)
321 {
322 if (!dc->type_b && (dc->imm & (1 << 10))) {
323 dec_pattern(dc);
324 return;
325 }
326
327 LOG_DIS("xor r%d\n", dc->rd);
328 if (dc->rd)
329 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
330 }
331
332 static void read_carry(DisasContext *dc, TCGv d)
333 {
334 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
335 }
336
337 static void write_carry(DisasContext *dc, TCGv v)
338 {
339 TCGv t0 = tcg_temp_new();
340 tcg_gen_shli_tl(t0, v, 31);
341 tcg_gen_sari_tl(t0, t0, 31);
342 tcg_gen_mov_tl(env_debug, t0);
343 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
344 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
345 ~(MSR_C | MSR_CC));
346 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
347 tcg_temp_free(t0);
348 }
349
350
351 static inline void msr_read(DisasContext *dc, TCGv d)
352 {
353 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
354 }
355
356 static inline void msr_write(DisasContext *dc, TCGv v)
357 {
358 dc->cpustate_changed = 1;
359 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
360 /* PVR, we have a processor version register. */
361 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
362 }
363
364 static void dec_msr(DisasContext *dc)
365 {
366 TCGv t0, t1;
367 unsigned int sr, to, rn;
368 int mem_index = cpu_mmu_index(dc->env);
369
370 sr = dc->imm & ((1 << 14) - 1);
371 to = dc->imm & (1 << 14);
372 dc->type_b = 1;
373 if (to)
374 dc->cpustate_changed = 1;
375
376 /* msrclr and msrset. */
377 if (!(dc->imm & (1 << 15))) {
378 unsigned int clr = dc->ir & (1 << 16);
379
380 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
381 dc->rd, dc->imm);
382
383 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
384 /* nop??? */
385 return;
386 }
387
388 if ((dc->tb_flags & MSR_EE_FLAG)
389 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
390 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
391 t_gen_raise_exception(dc, EXCP_HW_EXCP);
392 return;
393 }
394
395 if (dc->rd)
396 msr_read(dc, cpu_R[dc->rd]);
397
398 t0 = tcg_temp_new();
399 t1 = tcg_temp_new();
400 msr_read(dc, t0);
401 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
402
403 if (clr) {
404 tcg_gen_not_tl(t1, t1);
405 tcg_gen_and_tl(t0, t0, t1);
406 } else
407 tcg_gen_or_tl(t0, t0, t1);
408 msr_write(dc, t0);
409 tcg_temp_free(t0);
410 tcg_temp_free(t1);
411 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
412 dc->is_jmp = DISAS_UPDATE;
413 return;
414 }
415
416 if (to) {
417 if ((dc->tb_flags & MSR_EE_FLAG)
418 && mem_index == MMU_USER_IDX) {
419 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
420 t_gen_raise_exception(dc, EXCP_HW_EXCP);
421 return;
422 }
423 }
424
425 #if !defined(CONFIG_USER_ONLY)
426 /* Catch read/writes to the mmu block. */
427 if ((sr & ~0xff) == 0x1000) {
428 sr &= 7;
429 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
430 if (to)
431 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
432 else
433 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
434 return;
435 }
436 #endif
437
438 if (to) {
439 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
440 switch (sr) {
441 case 0:
442 break;
443 case 1:
444 msr_write(dc, cpu_R[dc->ra]);
445 break;
446 case 0x3:
447 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
448 break;
449 case 0x5:
450 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
451 break;
452 case 0x7:
453 /* Ignored at the moment. */
454 break;
455 default:
456 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
457 break;
458 }
459 } else {
460 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
461
462 switch (sr) {
463 case 0:
464 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
465 break;
466 case 1:
467 msr_read(dc, cpu_R[dc->rd]);
468 break;
469 case 0x3:
470 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
471 break;
472 case 0x5:
473 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
474 break;
475 case 0x7:
476 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
477 break;
478 case 0xb:
479 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
480 break;
481 case 0x2000:
482 case 0x2001:
483 case 0x2002:
484 case 0x2003:
485 case 0x2004:
486 case 0x2005:
487 case 0x2006:
488 case 0x2007:
489 case 0x2008:
490 case 0x2009:
491 case 0x200a:
492 case 0x200b:
493 case 0x200c:
494 rn = sr & 0xf;
495 tcg_gen_ld_tl(cpu_R[dc->rd],
496 cpu_env, offsetof(CPUState, pvr.regs[rn]));
497 break;
498 default:
499 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
500 break;
501 }
502 }
503
504 if (dc->rd == 0) {
505 tcg_gen_movi_tl(cpu_R[0], 0);
506 }
507 }
508
509 /* 64-bit signed mul, lower result in d and upper in d2. */
510 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
511 {
512 TCGv_i64 t0, t1;
513
514 t0 = tcg_temp_new_i64();
515 t1 = tcg_temp_new_i64();
516
517 tcg_gen_ext_i32_i64(t0, a);
518 tcg_gen_ext_i32_i64(t1, b);
519 tcg_gen_mul_i64(t0, t0, t1);
520
521 tcg_gen_trunc_i64_i32(d, t0);
522 tcg_gen_shri_i64(t0, t0, 32);
523 tcg_gen_trunc_i64_i32(d2, t0);
524
525 tcg_temp_free_i64(t0);
526 tcg_temp_free_i64(t1);
527 }
528
529 /* 64-bit unsigned muls, lower result in d and upper in d2. */
530 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
531 {
532 TCGv_i64 t0, t1;
533
534 t0 = tcg_temp_new_i64();
535 t1 = tcg_temp_new_i64();
536
537 tcg_gen_extu_i32_i64(t0, a);
538 tcg_gen_extu_i32_i64(t1, b);
539 tcg_gen_mul_i64(t0, t0, t1);
540
541 tcg_gen_trunc_i64_i32(d, t0);
542 tcg_gen_shri_i64(t0, t0, 32);
543 tcg_gen_trunc_i64_i32(d2, t0);
544
545 tcg_temp_free_i64(t0);
546 tcg_temp_free_i64(t1);
547 }
548
549 /* Multiplier unit. */
550 static void dec_mul(DisasContext *dc)
551 {
552 TCGv d[2];
553 unsigned int subcode;
554
555 if ((dc->tb_flags & MSR_EE_FLAG)
556 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
557 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
558 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
559 t_gen_raise_exception(dc, EXCP_HW_EXCP);
560 return;
561 }
562
563 subcode = dc->imm & 3;
564 d[0] = tcg_temp_new();
565 d[1] = tcg_temp_new();
566
567 if (dc->type_b) {
568 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
569 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
570 goto done;
571 }
572
573 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
574 if (subcode >= 1 && subcode <= 3
575 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
576 /* nop??? */
577 }
578
579 switch (subcode) {
580 case 0:
581 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
582 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
583 break;
584 case 1:
585 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
586 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
587 break;
588 case 2:
589 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
590 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
591 break;
592 case 3:
593 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
594 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
595 break;
596 default:
597 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
598 break;
599 }
600 done:
601 tcg_temp_free(d[0]);
602 tcg_temp_free(d[1]);
603 }
604
605 /* Div unit. */
606 static void dec_div(DisasContext *dc)
607 {
608 unsigned int u;
609
610 u = dc->imm & 2;
611 LOG_DIS("div\n");
612
613 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
614 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
615 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
616 t_gen_raise_exception(dc, EXCP_HW_EXCP);
617 }
618
619 if (u)
620 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
621 else
622 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
623 if (!dc->rd)
624 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
625 }
626
627 static void dec_barrel(DisasContext *dc)
628 {
629 TCGv t0;
630 unsigned int s, t;
631
632 if ((dc->tb_flags & MSR_EE_FLAG)
633 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
634 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
635 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
636 t_gen_raise_exception(dc, EXCP_HW_EXCP);
637 return;
638 }
639
640 s = dc->imm & (1 << 10);
641 t = dc->imm & (1 << 9);
642
643 LOG_DIS("bs%s%s r%d r%d r%d\n",
644 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
645
646 t0 = tcg_temp_new();
647
648 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
649 tcg_gen_andi_tl(t0, t0, 31);
650
651 if (s)
652 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
653 else {
654 if (t)
655 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
656 else
657 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
658 }
659 }
660
661 static void dec_bit(DisasContext *dc)
662 {
663 TCGv t0, t1;
664 unsigned int op;
665 int mem_index = cpu_mmu_index(dc->env);
666
667 op = dc->ir & ((1 << 8) - 1);
668 switch (op) {
669 case 0x21:
670 /* src. */
671 t0 = tcg_temp_new();
672
673 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
674 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
675 if (dc->rd) {
676 t1 = tcg_temp_new();
677 read_carry(dc, t1);
678 tcg_gen_shli_tl(t1, t1, 31);
679
680 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
681 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
682 tcg_temp_free(t1);
683 }
684
685 /* Update carry. */
686 write_carry(dc, t0);
687 tcg_temp_free(t0);
688 break;
689
690 case 0x1:
691 case 0x41:
692 /* srl. */
693 t0 = tcg_temp_new();
694 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
695
696 /* Update carry. */
697 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
698 write_carry(dc, t0);
699 tcg_temp_free(t0);
700 if (dc->rd) {
701 if (op == 0x41)
702 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
703 else
704 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
705 }
706 break;
707 case 0x60:
708 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
709 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
710 break;
711 case 0x61:
712 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
713 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
714 break;
715 case 0x64:
716 case 0x66:
717 case 0x74:
718 case 0x76:
719 /* wdc. */
720 LOG_DIS("wdc r%d\n", dc->ra);
721 if ((dc->tb_flags & MSR_EE_FLAG)
722 && mem_index == MMU_USER_IDX) {
723 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
724 t_gen_raise_exception(dc, EXCP_HW_EXCP);
725 return;
726 }
727 break;
728 case 0x68:
729 /* wic. */
730 LOG_DIS("wic r%d\n", dc->ra);
731 if ((dc->tb_flags & MSR_EE_FLAG)
732 && mem_index == MMU_USER_IDX) {
733 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
734 t_gen_raise_exception(dc, EXCP_HW_EXCP);
735 return;
736 }
737 break;
738 default:
739 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
740 dc->pc, op, dc->rd, dc->ra, dc->rb);
741 break;
742 }
743 }
744
745 static inline void sync_jmpstate(DisasContext *dc)
746 {
747 if (dc->jmp == JMP_DIRECT) {
748 dc->jmp = JMP_INDIRECT;
749 tcg_gen_movi_tl(env_btaken, 1);
750 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
751 }
752 }
753
754 static void dec_imm(DisasContext *dc)
755 {
756 LOG_DIS("imm %x\n", dc->imm << 16);
757 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
758 dc->tb_flags |= IMM_FLAG;
759 dc->clear_imm = 0;
760 }
761
762 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
763 unsigned int size)
764 {
765 int mem_index = cpu_mmu_index(dc->env);
766
767 if (size == 1) {
768 tcg_gen_qemu_ld8u(dst, addr, mem_index);
769 } else if (size == 2) {
770 tcg_gen_qemu_ld16u(dst, addr, mem_index);
771 } else if (size == 4) {
772 tcg_gen_qemu_ld32u(dst, addr, mem_index);
773 } else
774 cpu_abort(dc->env, "Incorrect load size %d\n", size);
775 }
776
777 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
778 {
779 unsigned int extimm = dc->tb_flags & IMM_FLAG;
780
781 /* Treat the fast cases first. */
782 if (!dc->type_b) {
783 *t = tcg_temp_new();
784 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
785 return t;
786 }
787 /* Immediate. */
788 if (!extimm) {
789 if (dc->imm == 0) {
790 return &cpu_R[dc->ra];
791 }
792 *t = tcg_temp_new();
793 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
794 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
795 } else {
796 *t = tcg_temp_new();
797 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
798 }
799
800 return t;
801 }
802
803 static void dec_load(DisasContext *dc)
804 {
805 TCGv t, *addr;
806 unsigned int size;
807
808 size = 1 << (dc->opcode & 3);
809 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
810 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
811 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
812 t_gen_raise_exception(dc, EXCP_HW_EXCP);
813 return;
814 }
815
816 LOG_DIS("l %x %d\n", dc->opcode, size);
817 t_sync_flags(dc);
818 addr = compute_ldst_addr(dc, &t);
819
820 /* If we get a fault on a dslot, the jmpstate better be in sync. */
821 sync_jmpstate(dc);
822
823 /* Verify alignment if needed. */
824 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
825 TCGv v = tcg_temp_new();
826
827 /*
828 * Microblaze gives MMU faults priority over faults due to
829 * unaligned addresses. That's why we speculatively do the load
830 * into v. If the load succeeds, we verify alignment of the
831 * address and if that succeeds we write into the destination reg.
832 */
833 gen_load(dc, v, *addr, size);
834
835 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
836 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
837 tcg_const_tl(0), tcg_const_tl(size - 1));
838 if (dc->rd)
839 tcg_gen_mov_tl(cpu_R[dc->rd], v);
840 tcg_temp_free(v);
841 } else {
842 if (dc->rd) {
843 gen_load(dc, cpu_R[dc->rd], *addr, size);
844 } else {
845 gen_load(dc, env_imm, *addr, size);
846 }
847 }
848
849 if (addr == &t)
850 tcg_temp_free(t);
851 }
852
853 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
854 unsigned int size)
855 {
856 int mem_index = cpu_mmu_index(dc->env);
857
858 if (size == 1)
859 tcg_gen_qemu_st8(val, addr, mem_index);
860 else if (size == 2) {
861 tcg_gen_qemu_st16(val, addr, mem_index);
862 } else if (size == 4) {
863 tcg_gen_qemu_st32(val, addr, mem_index);
864 } else
865 cpu_abort(dc->env, "Incorrect store size %d\n", size);
866 }
867
868 static void dec_store(DisasContext *dc)
869 {
870 TCGv t, *addr;
871 unsigned int size;
872
873 size = 1 << (dc->opcode & 3);
874
875 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
876 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
877 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
878 t_gen_raise_exception(dc, EXCP_HW_EXCP);
879 return;
880 }
881
882 LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");
883 t_sync_flags(dc);
884 /* If we get a fault on a dslot, the jmpstate better be in sync. */
885 sync_jmpstate(dc);
886 addr = compute_ldst_addr(dc, &t);
887
888 gen_store(dc, *addr, cpu_R[dc->rd], size);
889
890 /* Verify alignment if needed. */
891 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
892 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
893 /* FIXME: if the alignment is wrong, we should restore the value
894 * in memory.
895 */
896 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
897 tcg_const_tl(1), tcg_const_tl(size - 1));
898 }
899
900 if (addr == &t)
901 tcg_temp_free(t);
902 }
903
904 static inline void eval_cc(DisasContext *dc, unsigned int cc,
905 TCGv d, TCGv a, TCGv b)
906 {
907 int l1;
908
909 switch (cc) {
910 case CC_EQ:
911 l1 = gen_new_label();
912 tcg_gen_movi_tl(env_btaken, 1);
913 tcg_gen_brcond_tl(TCG_COND_EQ, a, b, l1);
914 tcg_gen_movi_tl(env_btaken, 0);
915 gen_set_label(l1);
916 break;
917 case CC_NE:
918 l1 = gen_new_label();
919 tcg_gen_movi_tl(env_btaken, 1);
920 tcg_gen_brcond_tl(TCG_COND_NE, a, b, l1);
921 tcg_gen_movi_tl(env_btaken, 0);
922 gen_set_label(l1);
923 break;
924 case CC_LT:
925 l1 = gen_new_label();
926 tcg_gen_movi_tl(env_btaken, 1);
927 tcg_gen_brcond_tl(TCG_COND_LT, a, b, l1);
928 tcg_gen_movi_tl(env_btaken, 0);
929 gen_set_label(l1);
930 break;
931 case CC_LE:
932 l1 = gen_new_label();
933 tcg_gen_movi_tl(env_btaken, 1);
934 tcg_gen_brcond_tl(TCG_COND_LE, a, b, l1);
935 tcg_gen_movi_tl(env_btaken, 0);
936 gen_set_label(l1);
937 break;
938 case CC_GE:
939 l1 = gen_new_label();
940 tcg_gen_movi_tl(env_btaken, 1);
941 tcg_gen_brcond_tl(TCG_COND_GE, a, b, l1);
942 tcg_gen_movi_tl(env_btaken, 0);
943 gen_set_label(l1);
944 break;
945 case CC_GT:
946 l1 = gen_new_label();
947 tcg_gen_movi_tl(env_btaken, 1);
948 tcg_gen_brcond_tl(TCG_COND_GT, a, b, l1);
949 tcg_gen_movi_tl(env_btaken, 0);
950 gen_set_label(l1);
951 break;
952 default:
953 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
954 break;
955 }
956 }
957
958 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
959 {
960 int l1;
961
962 l1 = gen_new_label();
963 /* Conditional jmp. */
964 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
965 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
966 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
967 gen_set_label(l1);
968 }
969
970 static void dec_bcc(DisasContext *dc)
971 {
972 unsigned int cc;
973 unsigned int dslot;
974
975 cc = EXTRACT_FIELD(dc->ir, 21, 23);
976 dslot = dc->ir & (1 << 25);
977 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
978
979 dc->delayed_branch = 1;
980 if (dslot) {
981 dc->delayed_branch = 2;
982 dc->tb_flags |= D_FLAG;
983 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
984 cpu_env, offsetof(CPUState, bimm));
985 }
986
987 tcg_gen_movi_tl(env_btarget, dc->pc);
988 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
989 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
990 dc->jmp = JMP_INDIRECT;
991 }
992
993 static void dec_br(DisasContext *dc)
994 {
995 unsigned int dslot, link, abs;
996
997 dslot = dc->ir & (1 << 20);
998 abs = dc->ir & (1 << 19);
999 link = dc->ir & (1 << 18);
1000 LOG_DIS("br%s%s%s%s imm=%x\n",
1001 abs ? "a" : "", link ? "l" : "",
1002 dc->type_b ? "i" : "", dslot ? "d" : "",
1003 dc->imm);
1004
1005 dc->delayed_branch = 1;
1006 if (dslot) {
1007 dc->delayed_branch = 2;
1008 dc->tb_flags |= D_FLAG;
1009 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1010 cpu_env, offsetof(CPUState, bimm));
1011 }
1012 if (link && dc->rd)
1013 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1014
1015 dc->jmp = JMP_INDIRECT;
1016 if (abs) {
1017 tcg_gen_movi_tl(env_btaken, 1);
1018 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1019 if (link && !(dc->tb_flags & IMM_FLAG)
1020 && (dc->imm == 8 || dc->imm == 0x18))
1021 t_gen_raise_exception(dc, EXCP_BREAK);
1022 if (dc->imm == 0)
1023 t_gen_raise_exception(dc, EXCP_DEBUG);
1024 } else {
1025 if (!dc->type_b || (dc->tb_flags & IMM_FLAG)) {
1026 tcg_gen_movi_tl(env_btaken, 1);
1027 tcg_gen_movi_tl(env_btarget, dc->pc);
1028 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1029 } else {
1030 dc->jmp = JMP_DIRECT;
1031 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1032 }
1033 }
1034 }
1035
1036 static inline void do_rti(DisasContext *dc)
1037 {
1038 TCGv t0, t1;
1039 t0 = tcg_temp_new();
1040 t1 = tcg_temp_new();
1041 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1042 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1043 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1044
1045 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1046 tcg_gen_or_tl(t1, t1, t0);
1047 msr_write(dc, t1);
1048 tcg_temp_free(t1);
1049 tcg_temp_free(t0);
1050 dc->tb_flags &= ~DRTI_FLAG;
1051 }
1052
1053 static inline void do_rtb(DisasContext *dc)
1054 {
1055 TCGv t0, t1;
1056 t0 = tcg_temp_new();
1057 t1 = tcg_temp_new();
1058 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1059 tcg_gen_shri_tl(t0, t1, 1);
1060 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1061
1062 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1063 tcg_gen_or_tl(t1, t1, t0);
1064 msr_write(dc, t1);
1065 tcg_temp_free(t1);
1066 tcg_temp_free(t0);
1067 dc->tb_flags &= ~DRTB_FLAG;
1068 }
1069
1070 static inline void do_rte(DisasContext *dc)
1071 {
1072 TCGv t0, t1;
1073 t0 = tcg_temp_new();
1074 t1 = tcg_temp_new();
1075
1076 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1077 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1078 tcg_gen_shri_tl(t0, t1, 1);
1079 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1080
1081 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1082 tcg_gen_or_tl(t1, t1, t0);
1083 msr_write(dc, t1);
1084 tcg_temp_free(t1);
1085 tcg_temp_free(t0);
1086 dc->tb_flags &= ~DRTE_FLAG;
1087 }
1088
1089 static void dec_rts(DisasContext *dc)
1090 {
1091 unsigned int b_bit, i_bit, e_bit;
1092 int mem_index = cpu_mmu_index(dc->env);
1093
1094 i_bit = dc->ir & (1 << 21);
1095 b_bit = dc->ir & (1 << 22);
1096 e_bit = dc->ir & (1 << 23);
1097
1098 dc->delayed_branch = 2;
1099 dc->tb_flags |= D_FLAG;
1100 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1101 cpu_env, offsetof(CPUState, bimm));
1102
1103 if (i_bit) {
1104 LOG_DIS("rtid ir=%x\n", dc->ir);
1105 if ((dc->tb_flags & MSR_EE_FLAG)
1106 && mem_index == MMU_USER_IDX) {
1107 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1108 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1109 }
1110 dc->tb_flags |= DRTI_FLAG;
1111 } else if (b_bit) {
1112 LOG_DIS("rtbd ir=%x\n", dc->ir);
1113 if ((dc->tb_flags & MSR_EE_FLAG)
1114 && mem_index == MMU_USER_IDX) {
1115 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1116 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1117 }
1118 dc->tb_flags |= DRTB_FLAG;
1119 } else if (e_bit) {
1120 LOG_DIS("rted ir=%x\n", dc->ir);
1121 if ((dc->tb_flags & MSR_EE_FLAG)
1122 && mem_index == MMU_USER_IDX) {
1123 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1124 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1125 }
1126 dc->tb_flags |= DRTE_FLAG;
1127 } else
1128 LOG_DIS("rts ir=%x\n", dc->ir);
1129
1130 tcg_gen_movi_tl(env_btaken, 1);
1131 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1132 }
1133
1134 static void dec_fpu(DisasContext *dc)
1135 {
1136 if ((dc->tb_flags & MSR_EE_FLAG)
1137 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1138 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1139 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1140 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1141 return;
1142 }
1143
1144 qemu_log ("unimplemented FPU insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1145 dc->abort_at_next_insn = 1;
1146 }
1147
1148 static void dec_null(DisasContext *dc)
1149 {
1150 if ((dc->tb_flags & MSR_EE_FLAG)
1151 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1152 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1153 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1154 return;
1155 }
1156 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1157 dc->abort_at_next_insn = 1;
1158 }
1159
1160 static struct decoder_info {
1161 struct {
1162 uint32_t bits;
1163 uint32_t mask;
1164 };
1165 void (*dec)(DisasContext *dc);
1166 } decinfo[] = {
1167 {DEC_ADD, dec_add},
1168 {DEC_SUB, dec_sub},
1169 {DEC_AND, dec_and},
1170 {DEC_XOR, dec_xor},
1171 {DEC_OR, dec_or},
1172 {DEC_BIT, dec_bit},
1173 {DEC_BARREL, dec_barrel},
1174 {DEC_LD, dec_load},
1175 {DEC_ST, dec_store},
1176 {DEC_IMM, dec_imm},
1177 {DEC_BR, dec_br},
1178 {DEC_BCC, dec_bcc},
1179 {DEC_RTS, dec_rts},
1180 {DEC_FPU, dec_fpu},
1181 {DEC_MUL, dec_mul},
1182 {DEC_DIV, dec_div},
1183 {DEC_MSR, dec_msr},
1184 {{0, 0}, dec_null}
1185 };
1186
1187 static inline void decode(DisasContext *dc)
1188 {
1189 uint32_t ir;
1190 int i;
1191
1192 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1193 tcg_gen_debug_insn_start(dc->pc);
1194
1195 dc->ir = ir = ldl_code(dc->pc);
1196 LOG_DIS("%8.8x\t", dc->ir);
1197
1198 if (dc->ir)
1199 dc->nr_nops = 0;
1200 else {
1201 if ((dc->tb_flags & MSR_EE_FLAG)
1202 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1203 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1204 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1205 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1206 return;
1207 }
1208
1209 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1210 dc->nr_nops++;
1211 if (dc->nr_nops > 4)
1212 cpu_abort(dc->env, "fetching nop sequence\n");
1213 }
1214 /* bit 2 seems to indicate insn type. */
1215 dc->type_b = ir & (1 << 29);
1216
1217 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1218 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1219 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1220 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1221 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1222
1223 /* Large switch for all insns. */
1224 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1225 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1226 decinfo[i].dec(dc);
1227 break;
1228 }
1229 }
1230 }
1231
1232 static void check_breakpoint(CPUState *env, DisasContext *dc)
1233 {
1234 CPUBreakpoint *bp;
1235
1236 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1237 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1238 if (bp->pc == dc->pc) {
1239 t_gen_raise_exception(dc, EXCP_DEBUG);
1240 dc->is_jmp = DISAS_UPDATE;
1241 }
1242 }
1243 }
1244 }
1245
1246 /* generate intermediate code for basic block 'tb'. */
1247 static void
1248 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1249 int search_pc)
1250 {
1251 uint16_t *gen_opc_end;
1252 uint32_t pc_start;
1253 int j, lj;
1254 struct DisasContext ctx;
1255 struct DisasContext *dc = &ctx;
1256 uint32_t next_page_start, org_flags;
1257 target_ulong npc;
1258 int num_insns;
1259 int max_insns;
1260
1261 qemu_log_try_set_file(stderr);
1262
1263 pc_start = tb->pc;
1264 dc->env = env;
1265 dc->tb = tb;
1266 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1267
1268 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1269
1270 dc->is_jmp = DISAS_NEXT;
1271 dc->jmp = 0;
1272 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1273 dc->ppc = pc_start;
1274 dc->pc = pc_start;
1275 dc->cache_pc = -1;
1276 dc->singlestep_enabled = env->singlestep_enabled;
1277 dc->cpustate_changed = 0;
1278 dc->abort_at_next_insn = 0;
1279 dc->nr_nops = 0;
1280
1281 if (pc_start & 3)
1282 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1283
1284 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1285 #if !SIM_COMPAT
1286 qemu_log("--------------\n");
1287 log_cpu_state(env, 0);
1288 #endif
1289 }
1290
1291 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1292 lj = -1;
1293 num_insns = 0;
1294 max_insns = tb->cflags & CF_COUNT_MASK;
1295 if (max_insns == 0)
1296 max_insns = CF_COUNT_MASK;
1297
1298 gen_icount_start();
1299 do
1300 {
1301 #if SIM_COMPAT
1302 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1303 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1304 gen_helper_debug();
1305 }
1306 #endif
1307 check_breakpoint(env, dc);
1308
1309 if (search_pc) {
1310 j = gen_opc_ptr - gen_opc_buf;
1311 if (lj < j) {
1312 lj++;
1313 while (lj < j)
1314 gen_opc_instr_start[lj++] = 0;
1315 }
1316 gen_opc_pc[lj] = dc->pc;
1317 gen_opc_instr_start[lj] = 1;
1318 gen_opc_icount[lj] = num_insns;
1319 }
1320
1321 /* Pretty disas. */
1322 LOG_DIS("%8.8x:\t", dc->pc);
1323
1324 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1325 gen_io_start();
1326
1327 dc->clear_imm = 1;
1328 decode(dc);
1329 if (dc->clear_imm)
1330 dc->tb_flags &= ~IMM_FLAG;
1331 dc->ppc = dc->pc;
1332 dc->pc += 4;
1333 num_insns++;
1334
1335 if (dc->delayed_branch) {
1336 dc->delayed_branch--;
1337 if (!dc->delayed_branch) {
1338 if (dc->tb_flags & DRTI_FLAG)
1339 do_rti(dc);
1340 if (dc->tb_flags & DRTB_FLAG)
1341 do_rtb(dc);
1342 if (dc->tb_flags & DRTE_FLAG)
1343 do_rte(dc);
1344 /* Clear the delay slot flag. */
1345 dc->tb_flags &= ~D_FLAG;
1346 /* If it is a direct jump, try direct chaining. */
1347 if (dc->jmp != JMP_DIRECT) {
1348 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1349 dc->is_jmp = DISAS_JUMP;
1350 }
1351 break;
1352 }
1353 }
1354 if (env->singlestep_enabled)
1355 break;
1356 } while (!dc->is_jmp && !dc->cpustate_changed
1357 && gen_opc_ptr < gen_opc_end
1358 && !singlestep
1359 && (dc->pc < next_page_start)
1360 && num_insns < max_insns);
1361
1362 npc = dc->pc;
1363 if (dc->jmp == JMP_DIRECT) {
1364 if (dc->tb_flags & D_FLAG) {
1365 dc->is_jmp = DISAS_UPDATE;
1366 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1367 sync_jmpstate(dc);
1368 } else
1369 npc = dc->jmp_pc;
1370 }
1371
1372 if (tb->cflags & CF_LAST_IO)
1373 gen_io_end();
1374 /* Force an update if the per-tb cpu state has changed. */
1375 if (dc->is_jmp == DISAS_NEXT
1376 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1377 dc->is_jmp = DISAS_UPDATE;
1378 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1379 }
1380 t_sync_flags(dc);
1381
1382 if (unlikely(env->singlestep_enabled)) {
1383 t_gen_raise_exception(dc, EXCP_DEBUG);
1384 if (dc->is_jmp == DISAS_NEXT)
1385 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1386 } else {
1387 switch(dc->is_jmp) {
1388 case DISAS_NEXT:
1389 gen_goto_tb(dc, 1, npc);
1390 break;
1391 default:
1392 case DISAS_JUMP:
1393 case DISAS_UPDATE:
1394 /* indicate that the hash table must be used
1395 to find the next TB */
1396 tcg_gen_exit_tb(0);
1397 break;
1398 case DISAS_TB_JUMP:
1399 /* nothing more to generate */
1400 break;
1401 }
1402 }
1403 gen_icount_end(tb, num_insns);
1404 *gen_opc_ptr = INDEX_op_end;
1405 if (search_pc) {
1406 j = gen_opc_ptr - gen_opc_buf;
1407 lj++;
1408 while (lj <= j)
1409 gen_opc_instr_start[lj++] = 0;
1410 } else {
1411 tb->size = dc->pc - pc_start;
1412 tb->icount = num_insns;
1413 }
1414
1415 #ifdef DEBUG_DISAS
1416 #if !SIM_COMPAT
1417 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1418 qemu_log("\n");
1419 #if DISAS_GNU
1420 log_target_disas(pc_start, dc->pc - pc_start, 0);
1421 #endif
1422 qemu_log("\nisize=%d osize=%zd\n",
1423 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1424 }
1425 #endif
1426 #endif
1427 assert(!dc->abort_at_next_insn);
1428 }
1429
1430 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1431 {
1432 gen_intermediate_code_internal(env, tb, 0);
1433 }
1434
1435 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1436 {
1437 gen_intermediate_code_internal(env, tb, 1);
1438 }
1439
1440 void cpu_dump_state (CPUState *env, FILE *f,
1441 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1442 int flags)
1443 {
1444 int i;
1445
1446 if (!env || !f)
1447 return;
1448
1449 cpu_fprintf(f, "IN: PC=%x %s\n",
1450 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1451 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
1452 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1453 env->debug, env->imm, env->iflags);
1454 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1455 env->btaken, env->btarget,
1456 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1457 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1458 (env->sregs[SR_MSR] & MSR_EIP),
1459 (env->sregs[SR_MSR] & MSR_IE));
1460
1461 for (i = 0; i < 32; i++) {
1462 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1463 if ((i + 1) % 4 == 0)
1464 cpu_fprintf(f, "\n");
1465 }
1466 cpu_fprintf(f, "\n\n");
1467 }
1468
1469 CPUState *cpu_mb_init (const char *cpu_model)
1470 {
1471 CPUState *env;
1472 static int tcg_initialized = 0;
1473 int i;
1474
1475 env = qemu_mallocz(sizeof(CPUState));
1476
1477 cpu_exec_init(env);
1478 cpu_reset(env);
1479
1480
1481 if (tcg_initialized)
1482 return env;
1483
1484 tcg_initialized = 1;
1485
1486 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1487
1488 env_debug = tcg_global_mem_new(TCG_AREG0,
1489 offsetof(CPUState, debug),
1490 "debug0");
1491 env_iflags = tcg_global_mem_new(TCG_AREG0,
1492 offsetof(CPUState, iflags),
1493 "iflags");
1494 env_imm = tcg_global_mem_new(TCG_AREG0,
1495 offsetof(CPUState, imm),
1496 "imm");
1497 env_btarget = tcg_global_mem_new(TCG_AREG0,
1498 offsetof(CPUState, btarget),
1499 "btarget");
1500 env_btaken = tcg_global_mem_new(TCG_AREG0,
1501 offsetof(CPUState, btaken),
1502 "btaken");
1503 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1504 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1505 offsetof(CPUState, regs[i]),
1506 regnames[i]);
1507 }
1508 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1509 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1510 offsetof(CPUState, sregs[i]),
1511 special_regnames[i]);
1512 }
1513 #define GEN_HELPER 2
1514 #include "helper.h"
1515
1516 return env;
1517 }
1518
1519 void cpu_reset (CPUState *env)
1520 {
1521 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1522 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1523 log_cpu_state(env, 0);
1524 }
1525
1526 memset(env, 0, offsetof(CPUMBState, breakpoints));
1527 tlb_flush(env, 1);
1528
1529 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1530 | PVR0_USE_BARREL_MASK \
1531 | PVR0_USE_DIV_MASK \
1532 | PVR0_USE_HW_MUL_MASK \
1533 | PVR0_USE_EXC_MASK \
1534 | PVR0_USE_ICACHE_MASK \
1535 | PVR0_USE_DCACHE_MASK \
1536 | PVR0_USE_MMU \
1537 | (0xb << 8);
1538 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1539 | PVR2_D_LMB_MASK \
1540 | PVR2_I_OPB_MASK \
1541 | PVR2_I_LMB_MASK \
1542 | PVR2_USE_MSR_INSTR \
1543 | PVR2_USE_PCMP_INSTR \
1544 | PVR2_USE_BARREL_MASK \
1545 | PVR2_USE_DIV_MASK \
1546 | PVR2_USE_HW_MUL_MASK \
1547 | PVR2_USE_MUL64_MASK \
1548 | 0;
1549 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1550 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1551
1552 env->sregs[SR_MSR] = 0;
1553 #if defined(CONFIG_USER_ONLY)
1554 /* start in user mode with interrupts enabled. */
1555 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1556 #else
1557 mmu_init(&env->mmu);
1558 env->mmu.c_mmu = 3;
1559 env->mmu.c_mmu_tlb_access = 3;
1560 env->mmu.c_mmu_zones = 16;
1561 #endif
1562 }
1563
1564 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1565 unsigned long searched_pc, int pc_pos, void *puc)
1566 {
1567 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1568 }
Qemu with PowerPC KVM improvements