Reorganize struct Qcow2Cache for better struct packing
[qemu/agraf.git] / hw / pl110.c
blob06d2dfada694e35e3e15c0def03d6aaddb20d508
1 /*
2 * Arm PrimeCell PL110 Color LCD Controller
4 * Copyright (c) 2005-2009 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GNU LGPL
8 */
10 #include "sysbus.h"
11 #include "console.h"
12 #include "framebuffer.h"
14 #define PL110_CR_EN 0x001
15 #define PL110_CR_BGR 0x100
16 #define PL110_CR_BEBO 0x200
17 #define PL110_CR_BEPO 0x400
18 #define PL110_CR_PWR 0x800
20 enum pl110_bppmode
22 BPP_1,
23 BPP_2,
24 BPP_4,
25 BPP_8,
26 BPP_16,
27 BPP_32
30 typedef struct {
31 SysBusDevice busdev;
32 DisplayState *ds;
34 /* The Versatile/PB uses a slightly modified PL110 controller. */
35 int versatile;
36 uint32_t timing[4];
37 uint32_t cr;
38 uint32_t upbase;
39 uint32_t lpbase;
40 uint32_t int_status;
41 uint32_t int_mask;
42 int cols;
43 int rows;
44 enum pl110_bppmode bpp;
45 int invalidate;
46 uint32_t pallette[256];
47 uint32_t raw_pallette[128];
48 qemu_irq irq;
49 } pl110_state;
51 static const VMStateDescription vmstate_pl110 = {
52 .name = "pl110",
53 .version_id = 1,
54 .minimum_version_id = 1,
55 .fields = (VMStateField[]) {
56 VMSTATE_INT32(versatile, pl110_state),
57 VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
58 VMSTATE_UINT32(cr, pl110_state),
59 VMSTATE_UINT32(upbase, pl110_state),
60 VMSTATE_UINT32(lpbase, pl110_state),
61 VMSTATE_UINT32(int_status, pl110_state),
62 VMSTATE_UINT32(int_mask, pl110_state),
63 VMSTATE_INT32(cols, pl110_state),
64 VMSTATE_INT32(rows, pl110_state),
65 VMSTATE_UINT32(bpp, pl110_state),
66 VMSTATE_INT32(invalidate, pl110_state),
67 VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
68 VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
69 VMSTATE_END_OF_LIST()
73 static const unsigned char pl110_id[] =
74 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
76 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
77 has a different ID. However Linux only looks for the normal ID. */
78 #if 0
79 static const unsigned char pl110_versatile_id[] =
80 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
81 #else
82 #define pl110_versatile_id pl110_id
83 #endif
85 #include "pixel_ops.h"
87 #define BITS 8
88 #include "pl110_template.h"
89 #define BITS 15
90 #include "pl110_template.h"
91 #define BITS 16
92 #include "pl110_template.h"
93 #define BITS 24
94 #include "pl110_template.h"
95 #define BITS 32
96 #include "pl110_template.h"
98 static int pl110_enabled(pl110_state *s)
100 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
103 static void pl110_update_display(void *opaque)
105 pl110_state *s = (pl110_state *)opaque;
106 drawfn* fntable;
107 drawfn fn;
108 int dest_width;
109 int src_width;
110 int bpp_offset;
111 int first;
112 int last;
114 if (!pl110_enabled(s))
115 return;
117 switch (ds_get_bits_per_pixel(s->ds)) {
118 case 0:
119 return;
120 case 8:
121 fntable = pl110_draw_fn_8;
122 dest_width = 1;
123 break;
124 case 15:
125 fntable = pl110_draw_fn_15;
126 dest_width = 2;
127 break;
128 case 16:
129 fntable = pl110_draw_fn_16;
130 dest_width = 2;
131 break;
132 case 24:
133 fntable = pl110_draw_fn_24;
134 dest_width = 3;
135 break;
136 case 32:
137 fntable = pl110_draw_fn_32;
138 dest_width = 4;
139 break;
140 default:
141 fprintf(stderr, "pl110: Bad color depth\n");
142 exit(1);
144 if (s->cr & PL110_CR_BGR)
145 bpp_offset = 0;
146 else
147 bpp_offset = 18;
149 if (s->cr & PL110_CR_BEBO)
150 fn = fntable[s->bpp + 6 + bpp_offset];
151 else if (s->cr & PL110_CR_BEPO)
152 fn = fntable[s->bpp + 12 + bpp_offset];
153 else
154 fn = fntable[s->bpp + bpp_offset];
156 src_width = s->cols;
157 switch (s->bpp) {
158 case BPP_1:
159 src_width >>= 3;
160 break;
161 case BPP_2:
162 src_width >>= 2;
163 break;
164 case BPP_4:
165 src_width >>= 1;
166 break;
167 case BPP_8:
168 break;
169 case BPP_16:
170 src_width <<= 1;
171 break;
172 case BPP_32:
173 src_width <<= 2;
174 break;
176 dest_width *= s->cols;
177 first = 0;
178 framebuffer_update_display(s->ds,
179 s->upbase, s->cols, s->rows,
180 src_width, dest_width, 0,
181 s->invalidate,
182 fn, s->pallette,
183 &first, &last);
184 if (first >= 0) {
185 dpy_update(s->ds, 0, first, s->cols, last - first + 1);
187 s->invalidate = 0;
190 static void pl110_invalidate_display(void * opaque)
192 pl110_state *s = (pl110_state *)opaque;
193 s->invalidate = 1;
194 if (pl110_enabled(s)) {
195 qemu_console_resize(s->ds, s->cols, s->rows);
199 static void pl110_update_pallette(pl110_state *s, int n)
201 int i;
202 uint32_t raw;
203 unsigned int r, g, b;
205 raw = s->raw_pallette[n];
206 n <<= 1;
207 for (i = 0; i < 2; i++) {
208 r = (raw & 0x1f) << 3;
209 raw >>= 5;
210 g = (raw & 0x1f) << 3;
211 raw >>= 5;
212 b = (raw & 0x1f) << 3;
213 /* The I bit is ignored. */
214 raw >>= 6;
215 switch (ds_get_bits_per_pixel(s->ds)) {
216 case 8:
217 s->pallette[n] = rgb_to_pixel8(r, g, b);
218 break;
219 case 15:
220 s->pallette[n] = rgb_to_pixel15(r, g, b);
221 break;
222 case 16:
223 s->pallette[n] = rgb_to_pixel16(r, g, b);
224 break;
225 case 24:
226 case 32:
227 s->pallette[n] = rgb_to_pixel32(r, g, b);
228 break;
230 n++;
234 static void pl110_resize(pl110_state *s, int width, int height)
236 if (width != s->cols || height != s->rows) {
237 if (pl110_enabled(s)) {
238 qemu_console_resize(s->ds, width, height);
241 s->cols = width;
242 s->rows = height;
245 /* Update interrupts. */
246 static void pl110_update(pl110_state *s)
248 /* TODO: Implement interrupts. */
251 static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
253 pl110_state *s = (pl110_state *)opaque;
255 if (offset >= 0xfe0 && offset < 0x1000) {
256 if (s->versatile)
257 return pl110_versatile_id[(offset - 0xfe0) >> 2];
258 else
259 return pl110_id[(offset - 0xfe0) >> 2];
261 if (offset >= 0x200 && offset < 0x400) {
262 return s->raw_pallette[(offset - 0x200) >> 2];
264 switch (offset >> 2) {
265 case 0: /* LCDTiming0 */
266 return s->timing[0];
267 case 1: /* LCDTiming1 */
268 return s->timing[1];
269 case 2: /* LCDTiming2 */
270 return s->timing[2];
271 case 3: /* LCDTiming3 */
272 return s->timing[3];
273 case 4: /* LCDUPBASE */
274 return s->upbase;
275 case 5: /* LCDLPBASE */
276 return s->lpbase;
277 case 6: /* LCDIMSC */
278 if (s->versatile)
279 return s->cr;
280 return s->int_mask;
281 case 7: /* LCDControl */
282 if (s->versatile)
283 return s->int_mask;
284 return s->cr;
285 case 8: /* LCDRIS */
286 return s->int_status;
287 case 9: /* LCDMIS */
288 return s->int_status & s->int_mask;
289 case 11: /* LCDUPCURR */
290 /* TODO: Implement vertical refresh. */
291 return s->upbase;
292 case 12: /* LCDLPCURR */
293 return s->lpbase;
294 default:
295 hw_error("pl110_read: Bad offset %x\n", (int)offset);
296 return 0;
300 static void pl110_write(void *opaque, target_phys_addr_t offset,
301 uint32_t val)
303 pl110_state *s = (pl110_state *)opaque;
304 int n;
306 /* For simplicity invalidate the display whenever a control register
307 is writen to. */
308 s->invalidate = 1;
309 if (offset >= 0x200 && offset < 0x400) {
310 /* Pallette. */
311 n = (offset - 0x200) >> 2;
312 s->raw_pallette[(offset - 0x200) >> 2] = val;
313 pl110_update_pallette(s, n);
314 return;
316 switch (offset >> 2) {
317 case 0: /* LCDTiming0 */
318 s->timing[0] = val;
319 n = ((val & 0xfc) + 4) * 4;
320 pl110_resize(s, n, s->rows);
321 break;
322 case 1: /* LCDTiming1 */
323 s->timing[1] = val;
324 n = (val & 0x3ff) + 1;
325 pl110_resize(s, s->cols, n);
326 break;
327 case 2: /* LCDTiming2 */
328 s->timing[2] = val;
329 break;
330 case 3: /* LCDTiming3 */
331 s->timing[3] = val;
332 break;
333 case 4: /* LCDUPBASE */
334 s->upbase = val;
335 break;
336 case 5: /* LCDLPBASE */
337 s->lpbase = val;
338 break;
339 case 6: /* LCDIMSC */
340 if (s->versatile)
341 goto control;
342 imsc:
343 s->int_mask = val;
344 pl110_update(s);
345 break;
346 case 7: /* LCDControl */
347 if (s->versatile)
348 goto imsc;
349 control:
350 s->cr = val;
351 s->bpp = (val >> 1) & 7;
352 if (pl110_enabled(s)) {
353 qemu_console_resize(s->ds, s->cols, s->rows);
355 break;
356 case 10: /* LCDICR */
357 s->int_status &= ~val;
358 pl110_update(s);
359 break;
360 default:
361 hw_error("pl110_write: Bad offset %x\n", (int)offset);
365 static CPUReadMemoryFunc * const pl110_readfn[] = {
366 pl110_read,
367 pl110_read,
368 pl110_read
371 static CPUWriteMemoryFunc * const pl110_writefn[] = {
372 pl110_write,
373 pl110_write,
374 pl110_write
377 static int pl110_init(SysBusDevice *dev)
379 pl110_state *s = FROM_SYSBUS(pl110_state, dev);
380 int iomemtype;
382 iomemtype = cpu_register_io_memory(pl110_readfn,
383 pl110_writefn, s,
384 DEVICE_NATIVE_ENDIAN);
385 sysbus_init_mmio(dev, 0x1000, iomemtype);
386 sysbus_init_irq(dev, &s->irq);
387 s->ds = graphic_console_init(pl110_update_display,
388 pl110_invalidate_display,
389 NULL, NULL, s);
390 return 0;
393 static int pl110_versatile_init(SysBusDevice *dev)
395 pl110_state *s = FROM_SYSBUS(pl110_state, dev);
396 s->versatile = 1;
397 return pl110_init(dev);
400 static SysBusDeviceInfo pl110_info = {
401 .init = pl110_init,
402 .qdev.name = "pl110",
403 .qdev.size = sizeof(pl110_state),
404 .qdev.vmsd = &vmstate_pl110,
405 .qdev.no_user = 1,
408 static SysBusDeviceInfo pl110_versatile_info = {
409 .init = pl110_versatile_init,
410 .qdev.name = "pl110_versatile",
411 .qdev.size = sizeof(pl110_state),
412 .qdev.vmsd = &vmstate_pl110,
413 .qdev.no_user = 1,
416 static void pl110_register_devices(void)
418 sysbus_register_withprop(&pl110_info);
419 sysbus_register_withprop(&pl110_versatile_info);
422 device_init(pl110_register_devices)