hw/omap_uart.c

   1 /*
   2  * TI OMAP processors UART emulation.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu-char.h"
  21 #include "hw.h"
  22 #include "omap.h"
  23 /* We use pc-style serial ports.  */
  24 #include "pc.h"
  25
  26 /* UARTs */
  27 struct omap_uart_s {
  28     target_phys_addr_t base;
  29     SerialState *serial; /* TODO */
  30     struct omap_target_agent_s *ta;
  31     omap_clk fclk;
  32     qemu_irq irq;
  33
  34     uint8_t eblr;
  35     uint8_t syscontrol;
  36     uint8_t wkup;
  37     uint8_t cfps;
  38     uint8_t mdr[2];
  39     uint8_t scr;
  40     uint8_t clksel;
  41 };
  42
  43 void omap_uart_reset(struct omap_uart_s *s)
  44 {
  45     s->eblr = 0x00;
  46     s->syscontrol = 0;
  47     s->wkup = 0x3f;
  48     s->cfps = 0x69;
  49     s->clksel = 0;
  50 }
  51
  52 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
  53                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
  54                 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
  55 {
  56     struct omap_uart_s *s = (struct omap_uart_s *)
  57             qemu_mallocz(sizeof(struct omap_uart_s));
  58
  59     s->base = base;
  60     s->fclk = fclk;
  61     s->irq = irq;
  62 #ifdef TARGET_WORDS_BIGENDIAN
  63     s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
  64                                chr ?: qemu_chr_open("null", "null", NULL), 1,
  65                                1);
  66 #else
  67     s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
  68                                chr ?: qemu_chr_open("null", "null", NULL), 1,
  69                                0);
  70 #endif
  71     return s;
  72 }
  73
  74 static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
  75 {
  76     struct omap_uart_s *s = (struct omap_uart_s *) opaque;
  77
  78     addr &= 0xff;
  79     switch (addr) {
  80     case 0x20:  /* MDR1 */
  81         return s->mdr[0];
  82     case 0x24:  /* MDR2 */
  83         return s->mdr[1];
  84     case 0x40:  /* SCR */
  85         return s->scr;
  86     case 0x44:  /* SSR */
  87         return 0x0;
  88     case 0x48:  /* EBLR (OMAP2) */
  89         return s->eblr;
  90     case 0x4C:  /* OSC_12M_SEL (OMAP1) */
  91         return s->clksel;
  92     case 0x50:  /* MVR */
  93         return 0x30;
  94     case 0x54:  /* SYSC (OMAP2) */
  95         return s->syscontrol;
  96     case 0x58:  /* SYSS (OMAP2) */
  97         return 1;
  98     case 0x5c:  /* WER (OMAP2) */
  99         return s->wkup;
 100     case 0x60:  /* CFPS (OMAP2) */
 101         return s->cfps;
 102     }
 103
 104     OMAP_BAD_REG(addr);
 105     return 0;
 106 }
 107
 108 static void omap_uart_write(void *opaque, target_phys_addr_t addr,
 109                 uint32_t value)
 110 {
 111     struct omap_uart_s *s = (struct omap_uart_s *) opaque;
 112
 113     addr &= 0xff;
 114     switch (addr) {
 115     case 0x20:  /* MDR1 */
 116         s->mdr[0] = value & 0x7f;
 117         break;
 118     case 0x24:  /* MDR2 */
 119         s->mdr[1] = value & 0xff;
 120         break;
 121     case 0x40:  /* SCR */
 122         s->scr = value & 0xff;
 123         break;
 124     case 0x48:  /* EBLR (OMAP2) */
 125         s->eblr = value & 0xff;
 126         break;
 127     case 0x4C:  /* OSC_12M_SEL (OMAP1) */
 128         s->clksel = value & 1;
 129         break;
 130     case 0x44:  /* SSR */
 131     case 0x50:  /* MVR */
 132     case 0x58:  /* SYSS (OMAP2) */
 133         OMAP_RO_REG(addr);
 134         break;
 135     case 0x54:  /* SYSC (OMAP2) */
 136         s->syscontrol = value & 0x1d;
 137         if (value & 2)
 138             omap_uart_reset(s);
 139         break;
 140     case 0x5c:  /* WER (OMAP2) */
 141         s->wkup = value & 0x7f;
 142         break;
 143     case 0x60:  /* CFPS (OMAP2) */
 144         s->cfps = value & 0xff;
 145         break;
 146     default:
 147         OMAP_BAD_REG(addr);
 148     }
 149 }
 150
 151 static CPUReadMemoryFunc * const omap_uart_readfn[] = {
 152     omap_uart_read,
 153     omap_uart_read,
 154     omap_badwidth_read8,
 155 };
 156
 157 static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
 158     omap_uart_write,
 159     omap_uart_write,
 160     omap_badwidth_write8,
 161 };
 162
 163 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
 164                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 165                 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
 166 {
 167     target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
 168     struct omap_uart_s *s = omap_uart_init(base, irq,
 169                     fclk, iclk, txdma, rxdma, chr);
 170     int iomemtype = cpu_register_io_memory(omap_uart_readfn,
 171                     omap_uart_writefn, s);
 172
 173     s->ta = ta;
 174
 175     cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
 176
 177     return s;
 178 }
 179
 180 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
 181 {
 182     /* TODO: Should reuse or destroy current s->serial */
 183 #ifdef TARGET_WORDS_BIGENDIAN
 184     s->serial = serial_mm_init(s->base, 2, s->irq,
 185                                omap_clk_getrate(s->fclk) / 16,
 186                                chr ?: qemu_chr_open("null", "null", NULL), 1,
 187                                1);
 188 #else
 189     s->serial = serial_mm_init(s->base, 2, s->irq,
 190                                omap_clk_getrate(s->fclk) / 16,
 191                                chr ?: qemu_chr_open("null", "null", NULL), 1,
 192                                0);
 193 #endif
 194 }