hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "usb-ohci.h"
  36 #include "boards.h"
  37 #include "fw_cfg.h"
  38 #include "escc.h"
  39 #include "ide.h"
  40 #include "loader.h"
  41 #include "elf.h"
  42 #include "kvm.h"
  43 #include "kvm_ppc.h"
  44
  45 #define MAX_IDE_BUS 2
  46 #define VGA_BIOS_SIZE 65536
  47 #define CFG_ADDR 0xf0000510
  48
  49 /* temporary frame buffer OSI calls for the video.x driver. The right
  50    solution is to modify the driver to use VGA PCI I/Os */
  51 /* XXX: to be removed. This is no way related to emulation */
  52 static int vga_osi_call (CPUState *env)
  53 {
  54     static int vga_vbl_enabled;
  55     int linesize;
  56
  57 #if 0
  58     printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
  59 #endif
  60
  61     /* same handler as PearPC, coming from the original MOL video
  62        driver. */
  63     switch(env->gpr[5]) {
  64     case 4:
  65         break;
  66     case 28: /* set_vmode */
  67         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  68             env->gpr[3] = 1;
  69         else
  70             env->gpr[3] = 0;
  71         break;
  72     case 29: /* get_vmode_info */
  73         if (env->gpr[6] != 0) {
  74             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  75                 env->gpr[3] = 1;
  76                 break;
  77             }
  78         }
  79         env->gpr[3] = 0;
  80         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  81         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  82         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  83         env->gpr[7] = 85 << 16; /* refresh rate */
  84         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  85         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  86         linesize = (linesize + 3) & ~3;
  87         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  88         break;
  89     case 31: /* set_video power */
  90         env->gpr[3] = 0;
  91         break;
  92     case 39: /* video_ctrl */
  93         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  94             vga_vbl_enabled = env->gpr[6];
  95         env->gpr[3] = 0;
  96         break;
  97     case 47:
  98         break;
  99     case 59: /* set_color */
 100         /* R6 = index, R7 = RGB */
 101         env->gpr[3] = 0;
 102         break;
 103     case 64: /* get color */
 104         /* R6 = index */
 105         env->gpr[3] = 0;
 106         break;
 107     case 116: /* set hwcursor */
 108         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 109         break;
 110     default:
 111         fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
 112                 ppc_dump_gpr(env, 5));
 113         break;
 114     }
 115
 116     return 1; /* osi_call handled */
 117 }
 118
 119 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 120 {
 121     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 122     return 0;
 123 }
 124
 125
 126 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 127 {
 128     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 129 }
 130
 131 static void ppc_heathrow_init (ram_addr_t ram_size,
 132                                const char *boot_device,
 133                                const char *kernel_filename,
 134                                const char *kernel_cmdline,
 135                                const char *initrd_filename,
 136                                const char *cpu_model)
 137 {
 138     CPUState *env = NULL, *envs[MAX_CPUS];
 139     char *filename;
 140     qemu_irq *pic, **heathrow_irqs;
 141     int linux_boot, i;
 142     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 143     uint32_t kernel_base, initrd_base;
 144     int32_t kernel_size, initrd_size;
 145     PCIBus *pci_bus;
 146     MacIONVRAMState *nvr;
 147     int vga_bios_size, bios_size;
 148     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 149     int escc_mem_index, ide_mem_index[2];
 150     uint16_t ppc_boot_device;
 151     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 152     void *fw_cfg;
 153     void *dbdma;
 154     uint8_t *vga_bios_ptr;
 155
 156     linux_boot = (kernel_filename != NULL);
 157
 158     /* init CPUs */
 159     if (cpu_model == NULL)
 160         cpu_model = "G3";
 161     for (i = 0; i < smp_cpus; i++) {
 162         env = cpu_init(cpu_model);
 163         if (!env) {
 164             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 165             exit(1);
 166         }
 167         /* Set time-base frequency to 16.6 Mhz */
 168         cpu_ppc_tb_init(env,  16600000UL);
 169         env->osi_call = vga_osi_call;
 170         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 171         envs[i] = env;
 172     }
 173
 174     /* allocate RAM */
 175     if (ram_size > (2047 << 20)) {
 176         fprintf(stderr,
 177                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 178                 ((unsigned int)ram_size / (1 << 20)));
 179         exit(1);
 180     }
 181
 182     ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", ram_size);
 183     cpu_register_physical_memory(0, ram_size, ram_offset);
 184
 185     /* allocate and load BIOS */
 186     bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE);
 187     if (bios_name == NULL)
 188         bios_name = PROM_FILENAME;
 189     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 190     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 191
 192     /* Load OpenBIOS (ELF) */
 193     if (filename) {
 194         bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
 195                              1, ELF_MACHINE, 0);
 196         qemu_free(filename);
 197     } else {
 198         bios_size = -1;
 199     }
 200     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 201         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 202         exit(1);
 203     }
 204
 205     /* allocate and load VGA BIOS */
 206     vga_bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.vbios", VGA_BIOS_SIZE);
 207     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 208     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 209     if (filename) {
 210         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 211         qemu_free(filename);
 212     } else {
 213         vga_bios_size = -1;
 214     }
 215     if (vga_bios_size < 0) {
 216         /* if no bios is present, we can still work */
 217         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 218                 VGABIOS_FILENAME);
 219         vga_bios_size = 0;
 220     } else {
 221         /* set a specific header (XXX: find real Apple format for NDRV
 222            drivers) */
 223         vga_bios_ptr[0] = 'N';
 224         vga_bios_ptr[1] = 'D';
 225         vga_bios_ptr[2] = 'R';
 226         vga_bios_ptr[3] = 'V';
 227         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 228         vga_bios_size += 8;
 229
 230         /* Round to page boundary */
 231         vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
 232             TARGET_PAGE_MASK;
 233     }
 234
 235     if (linux_boot) {
 236         uint64_t lowaddr = 0;
 237         int bswap_needed;
 238
 239 #ifdef BSWAP_NEEDED
 240         bswap_needed = 1;
 241 #else
 242         bswap_needed = 0;
 243 #endif
 244         kernel_base = KERNEL_LOAD_ADDR;
 245         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 246                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 247         if (kernel_size < 0)
 248             kernel_size = load_aout(kernel_filename, kernel_base,
 249                                     ram_size - kernel_base, bswap_needed,
 250                                     TARGET_PAGE_SIZE);
 251         if (kernel_size < 0)
 252             kernel_size = load_image_targphys(kernel_filename,
 253                                               kernel_base,
 254                                               ram_size - kernel_base);
 255         if (kernel_size < 0) {
 256             hw_error("qemu: could not load kernel '%s'\n",
 257                       kernel_filename);
 258             exit(1);
 259         }
 260         /* load initrd */
 261         if (initrd_filename) {
 262             initrd_base = INITRD_LOAD_ADDR;
 263             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 264                                               ram_size - initrd_base);
 265             if (initrd_size < 0) {
 266                 hw_error("qemu: could not load initial ram disk '%s'\n",
 267                          initrd_filename);
 268                 exit(1);
 269             }
 270         } else {
 271             initrd_base = 0;
 272             initrd_size = 0;
 273         }
 274         ppc_boot_device = 'm';
 275     } else {
 276         kernel_base = 0;
 277         kernel_size = 0;
 278         initrd_base = 0;
 279         initrd_size = 0;
 280         ppc_boot_device = '\0';
 281         for (i = 0; boot_device[i] != '\0'; i++) {
 282             /* TOFIX: for now, the second IDE channel is not properly
 283              *        used by OHW. The Mac floppy disk are not emulated.
 284              *        For now, OHW cannot boot from the network.
 285              */
 286 #if 0
 287             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 288                 ppc_boot_device = boot_device[i];
 289                 break;
 290             }
 291 #else
 292             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 293                 ppc_boot_device = boot_device[i];
 294                 break;
 295             }
 296 #endif
 297         }
 298         if (ppc_boot_device == '\0') {
 299             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 300             exit(1);
 301         }
 302     }
 303
 304     isa_mem_base = 0x80000000;
 305
 306     /* Register 2 MB of ISA IO space */
 307     isa_mmio_init(0xfe000000, 0x00200000, 1);
 308
 309     /* XXX: we register only 1 output pin for heathrow PIC */
 310     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 311     heathrow_irqs[0] =
 312         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 313     /* Connect the heathrow PIC outputs to the 6xx bus */
 314     for (i = 0; i < smp_cpus; i++) {
 315         switch (PPC_INPUT(env)) {
 316         case PPC_FLAGS_INPUT_6xx:
 317             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 318             heathrow_irqs[i][0] =
 319                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 320             break;
 321         default:
 322             hw_error("Bus model not supported on OldWorld Mac machine\n");
 323         }
 324     }
 325
 326     /* init basic PC hardware */
 327     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 328         hw_error("Only 6xx bus is supported on heathrow machine\n");
 329     }
 330     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 331     pci_bus = pci_grackle_init(0xfec00000, pic);
 332     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 333
 334     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 335                                serial_hds[1], ESCC_CLOCK, 4);
 336
 337     for(i = 0; i < nb_nics; i++)
 338         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 339
 340
 341     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 342         fprintf(stderr, "qemu: too many IDE bus\n");
 343         exit(1);
 344     }
 345
 346     /* First IDE channel is a MAC IDE on the MacIO bus */
 347     hd[0] = drive_get(IF_IDE, 0, 0);
 348     hd[1] = drive_get(IF_IDE, 0, 1);
 349     dbdma = DBDMA_init(&dbdma_mem_index);
 350     ide_mem_index[0] = -1;
 351     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 352
 353     /* Second IDE channel is a CMD646 on the PCI bus */
 354     hd[0] = drive_get(IF_IDE, 1, 0);
 355     hd[1] = drive_get(IF_IDE, 1, 1);
 356     hd[3] = hd[2] = NULL;
 357     pci_cmd646_ide_init(pci_bus, hd, 0);
 358
 359     /* cuda also initialize ADB */
 360     cuda_init(&cuda_mem_index, pic[0x12]);
 361
 362     adb_kbd_init(&adb_bus);
 363     adb_mouse_init(&adb_bus);
 364
 365     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
 366     pmac_format_nvram_partition(nvr, 0x2000);
 367
 368     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
 369                dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
 370                escc_mem_index);
 371
 372     if (usb_enabled) {
 373         usb_ohci_init_pci(pci_bus, -1);
 374     }
 375
 376     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 377         graphic_depth = 15;
 378
 379     /* No PCI init: the BIOS will do it */
 380
 381     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 382     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 383     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 384     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 385     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 386     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 387     if (kernel_cmdline) {
 388         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 389         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 390     } else {
 391         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 392     }
 393     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 394     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 395     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 396
 397     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 399     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 400
 401     if (kvm_enabled()) {
 402 #ifdef CONFIG_KVM
 403         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 404 #endif
 405     } else {
 406         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
 407     }
 408
 409     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 410 }
 411
 412 static QEMUMachine heathrow_machine = {
 413     .name = "g3beige",
 414     .desc = "Heathrow based PowerMAC",
 415     .init = ppc_heathrow_init,
 416     .max_cpus = MAX_CPUS,
 417 #ifndef TARGET_PPC64
 418     .is_default = 1,
 419 #endif
 420 };
 421
 422 static void heathrow_machine_init(void)
 423 {
 424     qemu_register_machine(&heathrow_machine);
 425 }
 426
 427 machine_init(heathrow_machine_init);