PPC: Use macio IDE controller for Newworld
[qemu/agraf.git] / cpu-common.h
blob0ec9b72a91feaa4032d3fb22e23a4567d31e6814
1 #ifndef CPU_COMMON_H
2 #define CPU_COMMON_H 1
4 /* CPU interfaces that are target indpendent. */
6 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
7 #define WORDS_ALIGNED
8 #endif
10 #include "bswap.h"
11 #include "qemu-queue.h"
13 /* address in the RAM (different from a physical address) */
14 typedef unsigned long ram_addr_t;
16 /* memory API */
18 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
19 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
21 void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
22 ram_addr_t size,
23 ram_addr_t phys_offset,
24 ram_addr_t region_offset);
25 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
26 ram_addr_t size,
27 ram_addr_t phys_offset)
29 cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
32 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
33 ram_addr_t qemu_ram_alloc(ram_addr_t);
34 void qemu_ram_free(ram_addr_t addr);
35 /* This should only be used for ram local to a device. */
36 void *qemu_get_ram_ptr(ram_addr_t addr);
37 /* This should not be used by devices. */
38 ram_addr_t qemu_ram_addr_from_host(void *ptr);
40 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
41 CPUWriteMemoryFunc * const *mem_write,
42 void *opaque);
43 void cpu_unregister_io_memory(int table_address);
45 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
46 int len, int is_write);
47 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
48 uint8_t *buf, int len)
50 cpu_physical_memory_rw(addr, buf, len, 0);
52 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
53 const uint8_t *buf, int len)
55 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
57 void *cpu_physical_memory_map(target_phys_addr_t addr,
58 target_phys_addr_t *plen,
59 int is_write);
60 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
61 int is_write, target_phys_addr_t access_len);
62 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
63 void cpu_unregister_map_client(void *cookie);
65 struct CPUPhysMemoryClient;
66 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
67 struct CPUPhysMemoryClient {
68 void (*set_memory)(struct CPUPhysMemoryClient *client,
69 target_phys_addr_t start_addr,
70 ram_addr_t size,
71 ram_addr_t phys_offset);
72 int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
73 target_phys_addr_t start_addr,
74 target_phys_addr_t end_addr);
75 int (*migration_log)(struct CPUPhysMemoryClient *client,
76 int enable);
77 QLIST_ENTRY(CPUPhysMemoryClient) list;
80 void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
81 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
83 uint32_t ldub_phys(target_phys_addr_t addr);
84 uint32_t lduw_phys(target_phys_addr_t addr);
85 uint32_t ldl_phys(target_phys_addr_t addr);
86 uint64_t ldq_phys(target_phys_addr_t addr);
87 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
88 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
89 void stb_phys(target_phys_addr_t addr, uint32_t val);
90 void stw_phys(target_phys_addr_t addr, uint32_t val);
91 void stl_phys(target_phys_addr_t addr, uint32_t val);
92 void stq_phys(target_phys_addr_t addr, uint64_t val);
94 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
95 const uint8_t *buf, int len);
97 #define IO_MEM_SHIFT 3
99 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
100 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
101 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
102 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
104 /* Acts like a ROM when read and like a device when written. */
105 #define IO_MEM_ROMD (1)
106 #define IO_MEM_SUBPAGE (2)
107 #define IO_MEM_SUBWIDTH (4)
109 #endif /* !CPU_COMMON_H */