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ppc: Make hbrev table const
[qemu/agraf.git] / target-sparc / ldst_helper.c
blob9bec7a92f7a33deaa240c0b1609805a4fae4d3db
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 //#define DEBUG_MMU
24 //#define DEBUG_MXCC
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
27 //#define DEBUG_ASI
28 //#define DEBUG_CACHE_CONTROL
29
30 #ifdef DEBUG_MMU
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
33 #else
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
35 #endif
36
37 #ifdef DEBUG_MXCC
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
40 #else
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
42 #endif
43
44 #ifdef DEBUG_ASI
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
47 #endif
48
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
54 #endif
55
56 #ifdef TARGET_SPARC64
57 #ifndef TARGET_ABI32
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
59 #else
60 #define AM_CHECK(env1) (1)
61 #endif
62 #endif
63
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
66
67 #if !defined(CONFIG_USER_ONLY)
68 #include "softmmu_exec.h"
69 #define MMUSUFFIX _mmu
70 #define ALIGNED_ONLY
71
72 #define SHIFT 0
73 #include "softmmu_template.h"
74
75 #define SHIFT 1
76 #include "softmmu_template.h"
77
78 #define SHIFT 2
79 #include "softmmu_template.h"
80
81 #define SHIFT 3
82 #include "softmmu_template.h"
83 #endif
84
85 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
86 /* Calculates TSB pointer value for fault page size 8k or 64k */
87 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
88 uint64_t tag_access_register,
89 int page_size)
90 {
91 uint64_t tsb_base = tsb_register & ~0x1fffULL;
92 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
93 int tsb_size = tsb_register & 0xf;
94
95 /* discard lower 13 bits which hold tag access context */
96 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
97
98 /* now reorder bits */
99 uint64_t tsb_base_mask = ~0x1fffULL;
100 uint64_t va = tag_access_va;
101
102 /* move va bits to correct position */
103 if (page_size == 8*1024) {
104 va >>= 9;
105 } else if (page_size == 64*1024) {
106 va >>= 12;
107 }
108
109 if (tsb_size) {
110 tsb_base_mask <<= tsb_size;
111 }
112
113 /* calculate tsb_base mask and adjust va if split is in use */
114 if (tsb_split) {
115 if (page_size == 8*1024) {
116 va &= ~(1ULL << (13 + tsb_size));
117 } else if (page_size == 64*1024) {
118 va |= (1ULL << (13 + tsb_size));
119 }
120 tsb_base_mask <<= 1;
121 }
122
123 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
124 }
125
126 /* Calculates tag target register value by reordering bits
127 in tag access register */
128 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
129 {
130 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
131 }
132
133 static void replace_tlb_entry(SparcTLBEntry *tlb,
134 uint64_t tlb_tag, uint64_t tlb_tte,
135 CPUSPARCState *env1)
136 {
137 target_ulong mask, size, va, offset;
138
139 /* flush page range if translation is valid */
140 if (TTE_IS_VALID(tlb->tte)) {
141
142 mask = 0xffffffffffffe000ULL;
143 mask <<= 3 * ((tlb->tte >> 61) & 3);
144 size = ~mask + 1;
145
146 va = tlb->tag & mask;
147
148 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
149 tlb_flush_page(env1, va + offset);
150 }
151 }
152
153 tlb->tag = tlb_tag;
154 tlb->tte = tlb_tte;
155 }
156
157 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
158 const char *strmmu, CPUSPARCState *env1)
159 {
160 unsigned int i;
161 target_ulong mask;
162 uint64_t context;
163
164 int is_demap_context = (demap_addr >> 6) & 1;
165
166 /* demap context */
167 switch ((demap_addr >> 4) & 3) {
168 case 0: /* primary */
169 context = env1->dmmu.mmu_primary_context;
170 break;
171 case 1: /* secondary */
172 context = env1->dmmu.mmu_secondary_context;
173 break;
174 case 2: /* nucleus */
175 context = 0;
176 break;
177 case 3: /* reserved */
178 default:
179 return;
180 }
181
182 for (i = 0; i < 64; i++) {
183 if (TTE_IS_VALID(tlb[i].tte)) {
184
185 if (is_demap_context) {
186 /* will remove non-global entries matching context value */
187 if (TTE_IS_GLOBAL(tlb[i].tte) ||
188 !tlb_compare_context(&tlb[i], context)) {
189 continue;
190 }
191 } else {
192 /* demap page
193 will remove any entry matching VA */
194 mask = 0xffffffffffffe000ULL;
195 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
196
197 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
198 continue;
199 }
200
201 /* entry should be global or matching context value */
202 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
203 !tlb_compare_context(&tlb[i], context)) {
204 continue;
205 }
206 }
207
208 replace_tlb_entry(&tlb[i], 0, 0, env1);
209 #ifdef DEBUG_MMU
210 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
211 dump_mmu(stdout, fprintf, env1);
212 #endif
213 }
214 }
215 }
216
217 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
218 uint64_t tlb_tag, uint64_t tlb_tte,
219 const char *strmmu, CPUSPARCState *env1)
220 {
221 unsigned int i, replace_used;
222
223 /* Try replacing invalid entry */
224 for (i = 0; i < 64; i++) {
225 if (!TTE_IS_VALID(tlb[i].tte)) {
226 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
227 #ifdef DEBUG_MMU
228 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
229 dump_mmu(stdout, fprintf, env1);
230 #endif
231 return;
232 }
233 }
234
235 /* All entries are valid, try replacing unlocked entry */
236
237 for (replace_used = 0; replace_used < 2; ++replace_used) {
238
239 /* Used entries are not replaced on first pass */
240
241 for (i = 0; i < 64; i++) {
242 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
243
244 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
245 #ifdef DEBUG_MMU
246 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
247 strmmu, (replace_used ? "used" : "unused"), i);
248 dump_mmu(stdout, fprintf, env1);
249 #endif
250 return;
251 }
252 }
253
254 /* Now reset used bit and search for unused entries again */
255
256 for (i = 0; i < 64; i++) {
257 TTE_SET_UNUSED(tlb[i].tte);
258 }
259 }
260
261 #ifdef DEBUG_MMU
262 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
263 #endif
264 /* error state? */
265 }
266
267 #endif
268
269 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
270 {
271 #ifdef TARGET_SPARC64
272 if (AM_CHECK(env1)) {
273 addr &= 0xffffffffULL;
274 }
275 #endif
276 return addr;
277 }
278
279 /* returns true if access using this ASI is to have address translated by MMU
280 otherwise access is to raw physical address */
281 static inline int is_translating_asi(int asi)
282 {
283 #ifdef TARGET_SPARC64
284 /* Ultrasparc IIi translating asi
285 - note this list is defined by cpu implementation
286 */
287 switch (asi) {
288 case 0x04 ... 0x11:
289 case 0x16 ... 0x19:
290 case 0x1E ... 0x1F:
291 case 0x24 ... 0x2C:
292 case 0x70 ... 0x73:
293 case 0x78 ... 0x79:
294 case 0x80 ... 0xFF:
295 return 1;
296
297 default:
298 return 0;
299 }
300 #else
301 /* TODO: check sparc32 bits */
302 return 0;
303 #endif
304 }
305
306 static inline target_ulong asi_address_mask(CPUSPARCState *env,
307 int asi, target_ulong addr)
308 {
309 if (is_translating_asi(asi)) {
310 return address_mask(env, addr);
311 } else {
312 return addr;
313 }
314 }
315
316 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
317 {
318 if (addr & align) {
319 #ifdef DEBUG_UNALIGNED
320 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
321 "\n", addr, env->pc);
322 #endif
323 helper_raise_exception(env, TT_UNALIGNED);
324 }
325 }
326
327 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
328 defined(DEBUG_MXCC)
329 static void dump_mxcc(CPUSPARCState *env)
330 {
331 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
332 "\n",
333 env->mxccdata[0], env->mxccdata[1],
334 env->mxccdata[2], env->mxccdata[3]);
335 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
336 "\n"
337 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
338 "\n",
339 env->mxccregs[0], env->mxccregs[1],
340 env->mxccregs[2], env->mxccregs[3],
341 env->mxccregs[4], env->mxccregs[5],
342 env->mxccregs[6], env->mxccregs[7]);
343 }
344 #endif
345
346 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
347 && defined(DEBUG_ASI)
348 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
349 uint64_t r1)
350 {
351 switch (size) {
352 case 1:
353 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
354 addr, asi, r1 & 0xff);
355 break;
356 case 2:
357 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
358 addr, asi, r1 & 0xffff);
359 break;
360 case 4:
361 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
362 addr, asi, r1 & 0xffffffff);
363 break;
364 case 8:
365 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
366 addr, asi, r1);
367 break;
368 }
369 }
370 #endif
371
372 #ifndef TARGET_SPARC64
373 #ifndef CONFIG_USER_ONLY
374
375
376 /* Leon3 cache control */
377
378 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
379 uint64_t val, int size)
380 {
381 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
382 addr, val, size);
383
384 if (size != 4) {
385 DPRINTF_CACHE_CONTROL("32bits only\n");
386 return;
387 }
388
389 switch (addr) {
390 case 0x00: /* Cache control */
391
392 /* These values must always be read as zeros */
393 val &= ~CACHE_CTRL_FD;
394 val &= ~CACHE_CTRL_FI;
395 val &= ~CACHE_CTRL_IB;
396 val &= ~CACHE_CTRL_IP;
397 val &= ~CACHE_CTRL_DP;
398
399 env->cache_control = val;
400 break;
401 case 0x04: /* Instruction cache configuration */
402 case 0x08: /* Data cache configuration */
403 /* Read Only */
404 break;
405 default:
406 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
407 break;
408 };
409 }
410
411 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
412 int size)
413 {
414 uint64_t ret = 0;
415
416 if (size != 4) {
417 DPRINTF_CACHE_CONTROL("32bits only\n");
418 return 0;
419 }
420
421 switch (addr) {
422 case 0x00: /* Cache control */
423 ret = env->cache_control;
424 break;
425
426 /* Configuration registers are read and only always keep those
427 predefined values */
428
429 case 0x04: /* Instruction cache configuration */
430 ret = 0x10220000;
431 break;
432 case 0x08: /* Data cache configuration */
433 ret = 0x18220000;
434 break;
435 default:
436 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
437 break;
438 };
439 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
440 addr, ret, size);
441 return ret;
442 }
443
444 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
445 int sign)
446 {
447 uint64_t ret = 0;
448 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
449 uint32_t last_addr = addr;
450 #endif
451
452 helper_check_align(env, addr, size - 1);
453 switch (asi) {
454 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
455 switch (addr) {
456 case 0x00: /* Leon3 Cache Control */
457 case 0x08: /* Leon3 Instruction Cache config */
458 case 0x0C: /* Leon3 Date Cache config */
459 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
460 ret = leon3_cache_control_ld(env, addr, size);
461 }
462 break;
463 case 0x01c00a00: /* MXCC control register */
464 if (size == 8) {
465 ret = env->mxccregs[3];
466 } else {
467 qemu_log_mask(LOG_UNIMP,
468 "%08x: unimplemented access size: %d\n", addr,
469 size);
470 }
471 break;
472 case 0x01c00a04: /* MXCC control register */
473 if (size == 4) {
474 ret = env->mxccregs[3];
475 } else {
476 qemu_log_mask(LOG_UNIMP,
477 "%08x: unimplemented access size: %d\n", addr,
478 size);
479 }
480 break;
481 case 0x01c00c00: /* Module reset register */
482 if (size == 8) {
483 ret = env->mxccregs[5];
484 /* should we do something here? */
485 } else {
486 qemu_log_mask(LOG_UNIMP,
487 "%08x: unimplemented access size: %d\n", addr,
488 size);
489 }
490 break;
491 case 0x01c00f00: /* MBus port address register */
492 if (size == 8) {
493 ret = env->mxccregs[7];
494 } else {
495 qemu_log_mask(LOG_UNIMP,
496 "%08x: unimplemented access size: %d\n", addr,
497 size);
498 }
499 break;
500 default:
501 qemu_log_mask(LOG_UNIMP,
502 "%08x: unimplemented address, size: %d\n", addr,
503 size);
504 break;
505 }
506 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
507 "addr = %08x -> ret = %" PRIx64 ","
508 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
509 #ifdef DEBUG_MXCC
510 dump_mxcc(env);
511 #endif
512 break;
513 case 3: /* MMU probe */
514 {
515 int mmulev;
516
517 mmulev = (addr >> 8) & 15;
518 if (mmulev > 4) {
519 ret = 0;
520 } else {
521 ret = mmu_probe(env, addr, mmulev);
522 }
523 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
524 addr, mmulev, ret);
525 }
526 break;
527 case 4: /* read MMU regs */
528 {
529 int reg = (addr >> 8) & 0x1f;
530
531 ret = env->mmuregs[reg];
532 if (reg == 3) { /* Fault status cleared on read */
533 env->mmuregs[3] = 0;
534 } else if (reg == 0x13) { /* Fault status read */
535 ret = env->mmuregs[3];
536 } else if (reg == 0x14) { /* Fault address read */
537 ret = env->mmuregs[4];
538 }
539 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
540 }
541 break;
542 case 5: /* Turbosparc ITLB Diagnostic */
543 case 6: /* Turbosparc DTLB Diagnostic */
544 case 7: /* Turbosparc IOTLB Diagnostic */
545 break;
546 case 9: /* Supervisor code access */
547 switch (size) {
548 case 1:
549 ret = cpu_ldub_code(env, addr);
550 break;
551 case 2:
552 ret = cpu_lduw_code(env, addr);
553 break;
554 default:
555 case 4:
556 ret = cpu_ldl_code(env, addr);
557 break;
558 case 8:
559 ret = cpu_ldq_code(env, addr);
560 break;
561 }
562 break;
563 case 0xa: /* User data access */
564 switch (size) {
565 case 1:
566 ret = cpu_ldub_user(env, addr);
567 break;
568 case 2:
569 ret = cpu_lduw_user(env, addr);
570 break;
571 default:
572 case 4:
573 ret = cpu_ldl_user(env, addr);
574 break;
575 case 8:
576 ret = cpu_ldq_user(env, addr);
577 break;
578 }
579 break;
580 case 0xb: /* Supervisor data access */
581 switch (size) {
582 case 1:
583 ret = cpu_ldub_kernel(env, addr);
584 break;
585 case 2:
586 ret = cpu_lduw_kernel(env, addr);
587 break;
588 default:
589 case 4:
590 ret = cpu_ldl_kernel(env, addr);
591 break;
592 case 8:
593 ret = cpu_ldq_kernel(env, addr);
594 break;
595 }
596 break;
597 case 0xc: /* I-cache tag */
598 case 0xd: /* I-cache data */
599 case 0xe: /* D-cache tag */
600 case 0xf: /* D-cache data */
601 break;
602 case 0x20: /* MMU passthrough */
603 switch (size) {
604 case 1:
605 ret = ldub_phys(addr);
606 break;
607 case 2:
608 ret = lduw_phys(addr);
609 break;
610 default:
611 case 4:
612 ret = ldl_phys(addr);
613 break;
614 case 8:
615 ret = ldq_phys(addr);
616 break;
617 }
618 break;
619 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
620 switch (size) {
621 case 1:
622 ret = ldub_phys((target_phys_addr_t)addr
623 | ((target_phys_addr_t)(asi & 0xf) << 32));
624 break;
625 case 2:
626 ret = lduw_phys((target_phys_addr_t)addr
627 | ((target_phys_addr_t)(asi & 0xf) << 32));
628 break;
629 default:
630 case 4:
631 ret = ldl_phys((target_phys_addr_t)addr
632 | ((target_phys_addr_t)(asi & 0xf) << 32));
633 break;
634 case 8:
635 ret = ldq_phys((target_phys_addr_t)addr
636 | ((target_phys_addr_t)(asi & 0xf) << 32));
637 break;
638 }
639 break;
640 case 0x30: /* Turbosparc secondary cache diagnostic */
641 case 0x31: /* Turbosparc RAM snoop */
642 case 0x32: /* Turbosparc page table descriptor diagnostic */
643 case 0x39: /* data cache diagnostic register */
644 ret = 0;
645 break;
646 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
647 {
648 int reg = (addr >> 8) & 3;
649
650 switch (reg) {
651 case 0: /* Breakpoint Value (Addr) */
652 ret = env->mmubpregs[reg];
653 break;
654 case 1: /* Breakpoint Mask */
655 ret = env->mmubpregs[reg];
656 break;
657 case 2: /* Breakpoint Control */
658 ret = env->mmubpregs[reg];
659 break;
660 case 3: /* Breakpoint Status */
661 ret = env->mmubpregs[reg];
662 env->mmubpregs[reg] = 0ULL;
663 break;
664 }
665 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
666 ret);
667 }
668 break;
669 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
670 ret = env->mmubpctrv;
671 break;
672 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
673 ret = env->mmubpctrc;
674 break;
675 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
676 ret = env->mmubpctrs;
677 break;
678 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
679 ret = env->mmubpaction;
680 break;
681 case 8: /* User code access, XXX */
682 default:
683 cpu_unassigned_access(env, addr, 0, 0, asi, size);
684 ret = 0;
685 break;
686 }
687 if (sign) {
688 switch (size) {
689 case 1:
690 ret = (int8_t) ret;
691 break;
692 case 2:
693 ret = (int16_t) ret;
694 break;
695 case 4:
696 ret = (int32_t) ret;
697 break;
698 default:
699 break;
700 }
701 }
702 #ifdef DEBUG_ASI
703 dump_asi("read ", last_addr, asi, size, ret);
704 #endif
705 return ret;
706 }
707
708 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
709 int size)
710 {
711 helper_check_align(env, addr, size - 1);
712 switch (asi) {
713 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
714 switch (addr) {
715 case 0x00: /* Leon3 Cache Control */
716 case 0x08: /* Leon3 Instruction Cache config */
717 case 0x0C: /* Leon3 Date Cache config */
718 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
719 leon3_cache_control_st(env, addr, val, size);
720 }
721 break;
722
723 case 0x01c00000: /* MXCC stream data register 0 */
724 if (size == 8) {
725 env->mxccdata[0] = val;
726 } else {
727 qemu_log_mask(LOG_UNIMP,
728 "%08x: unimplemented access size: %d\n", addr,
729 size);
730 }
731 break;
732 case 0x01c00008: /* MXCC stream data register 1 */
733 if (size == 8) {
734 env->mxccdata[1] = val;
735 } else {
736 qemu_log_mask(LOG_UNIMP,
737 "%08x: unimplemented access size: %d\n", addr,
738 size);
739 }
740 break;
741 case 0x01c00010: /* MXCC stream data register 2 */
742 if (size == 8) {
743 env->mxccdata[2] = val;
744 } else {
745 qemu_log_mask(LOG_UNIMP,
746 "%08x: unimplemented access size: %d\n", addr,
747 size);
748 }
749 break;
750 case 0x01c00018: /* MXCC stream data register 3 */
751 if (size == 8) {
752 env->mxccdata[3] = val;
753 } else {
754 qemu_log_mask(LOG_UNIMP,
755 "%08x: unimplemented access size: %d\n", addr,
756 size);
757 }
758 break;
759 case 0x01c00100: /* MXCC stream source */
760 if (size == 8) {
761 env->mxccregs[0] = val;
762 } else {
763 qemu_log_mask(LOG_UNIMP,
764 "%08x: unimplemented access size: %d\n", addr,
765 size);
766 }
767 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
768 0);
769 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
770 8);
771 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
772 16);
773 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
774 24);
775 break;
776 case 0x01c00200: /* MXCC stream destination */
777 if (size == 8) {
778 env->mxccregs[1] = val;
779 } else {
780 qemu_log_mask(LOG_UNIMP,
781 "%08x: unimplemented access size: %d\n", addr,
782 size);
783 }
784 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
785 env->mxccdata[0]);
786 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
787 env->mxccdata[1]);
788 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
789 env->mxccdata[2]);
790 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
791 env->mxccdata[3]);
792 break;
793 case 0x01c00a00: /* MXCC control register */
794 if (size == 8) {
795 env->mxccregs[3] = val;
796 } else {
797 qemu_log_mask(LOG_UNIMP,
798 "%08x: unimplemented access size: %d\n", addr,
799 size);
800 }
801 break;
802 case 0x01c00a04: /* MXCC control register */
803 if (size == 4) {
804 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
805 | val;
806 } else {
807 qemu_log_mask(LOG_UNIMP,
808 "%08x: unimplemented access size: %d\n", addr,
809 size);
810 }
811 break;
812 case 0x01c00e00: /* MXCC error register */
813 /* writing a 1 bit clears the error */
814 if (size == 8) {
815 env->mxccregs[6] &= ~val;
816 } else {
817 qemu_log_mask(LOG_UNIMP,
818 "%08x: unimplemented access size: %d\n", addr,
819 size);
820 }
821 break;
822 case 0x01c00f00: /* MBus port address register */
823 if (size == 8) {
824 env->mxccregs[7] = val;
825 } else {
826 qemu_log_mask(LOG_UNIMP,
827 "%08x: unimplemented access size: %d\n", addr,
828 size);
829 }
830 break;
831 default:
832 qemu_log_mask(LOG_UNIMP,
833 "%08x: unimplemented address, size: %d\n", addr,
834 size);
835 break;
836 }
837 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
838 asi, size, addr, val);
839 #ifdef DEBUG_MXCC
840 dump_mxcc(env);
841 #endif
842 break;
843 case 3: /* MMU flush */
844 {
845 int mmulev;
846
847 mmulev = (addr >> 8) & 15;
848 DPRINTF_MMU("mmu flush level %d\n", mmulev);
849 switch (mmulev) {
850 case 0: /* flush page */
851 tlb_flush_page(env, addr & 0xfffff000);
852 break;
853 case 1: /* flush segment (256k) */
854 case 2: /* flush region (16M) */
855 case 3: /* flush context (4G) */
856 case 4: /* flush entire */
857 tlb_flush(env, 1);
858 break;
859 default:
860 break;
861 }
862 #ifdef DEBUG_MMU
863 dump_mmu(stdout, fprintf, env);
864 #endif
865 }
866 break;
867 case 4: /* write MMU regs */
868 {
869 int reg = (addr >> 8) & 0x1f;
870 uint32_t oldreg;
871
872 oldreg = env->mmuregs[reg];
873 switch (reg) {
874 case 0: /* Control Register */
875 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
876 (val & 0x00ffffff);
877 /* Mappings generated during no-fault mode or MMU
878 disabled mode are invalid in normal mode */
879 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
880 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
881 tlb_flush(env, 1);
882 }
883 break;
884 case 1: /* Context Table Pointer Register */
885 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
886 break;
887 case 2: /* Context Register */
888 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
889 if (oldreg != env->mmuregs[reg]) {
890 /* we flush when the MMU context changes because
891 QEMU has no MMU context support */
892 tlb_flush(env, 1);
893 }
894 break;
895 case 3: /* Synchronous Fault Status Register with Clear */
896 case 4: /* Synchronous Fault Address Register */
897 break;
898 case 0x10: /* TLB Replacement Control Register */
899 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
900 break;
901 case 0x13: /* Synchronous Fault Status Register with Read
902 and Clear */
903 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
904 break;
905 case 0x14: /* Synchronous Fault Address Register */
906 env->mmuregs[4] = val;
907 break;
908 default:
909 env->mmuregs[reg] = val;
910 break;
911 }
912 if (oldreg != env->mmuregs[reg]) {
913 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
914 reg, oldreg, env->mmuregs[reg]);
915 }
916 #ifdef DEBUG_MMU
917 dump_mmu(stdout, fprintf, env);
918 #endif
919 }
920 break;
921 case 5: /* Turbosparc ITLB Diagnostic */
922 case 6: /* Turbosparc DTLB Diagnostic */
923 case 7: /* Turbosparc IOTLB Diagnostic */
924 break;
925 case 0xa: /* User data access */
926 switch (size) {
927 case 1:
928 cpu_stb_user(env, addr, val);
929 break;
930 case 2:
931 cpu_stw_user(env, addr, val);
932 break;
933 default:
934 case 4:
935 cpu_stl_user(env, addr, val);
936 break;
937 case 8:
938 cpu_stq_user(env, addr, val);
939 break;
940 }
941 break;
942 case 0xb: /* Supervisor data access */
943 switch (size) {
944 case 1:
945 cpu_stb_kernel(env, addr, val);
946 break;
947 case 2:
948 cpu_stw_kernel(env, addr, val);
949 break;
950 default:
951 case 4:
952 cpu_stl_kernel(env, addr, val);
953 break;
954 case 8:
955 cpu_stq_kernel(env, addr, val);
956 break;
957 }
958 break;
959 case 0xc: /* I-cache tag */
960 case 0xd: /* I-cache data */
961 case 0xe: /* D-cache tag */
962 case 0xf: /* D-cache data */
963 case 0x10: /* I/D-cache flush page */
964 case 0x11: /* I/D-cache flush segment */
965 case 0x12: /* I/D-cache flush region */
966 case 0x13: /* I/D-cache flush context */
967 case 0x14: /* I/D-cache flush user */
968 break;
969 case 0x17: /* Block copy, sta access */
970 {
971 /* val = src
972 addr = dst
973 copy 32 bytes */
974 unsigned int i;
975 uint32_t src = val & ~3, dst = addr & ~3, temp;
976
977 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
978 temp = cpu_ldl_kernel(env, src);
979 cpu_stl_kernel(env, dst, temp);
980 }
981 }
982 break;
983 case 0x1f: /* Block fill, stda access */
984 {
985 /* addr = dst
986 fill 32 bytes with val */
987 unsigned int i;
988 uint32_t dst = addr & 7;
989
990 for (i = 0; i < 32; i += 8, dst += 8) {
991 cpu_stq_kernel(env, dst, val);
992 }
993 }
994 break;
995 case 0x20: /* MMU passthrough */
996 {
997 switch (size) {
998 case 1:
999 stb_phys(addr, val);
1000 break;
1001 case 2:
1002 stw_phys(addr, val);
1003 break;
1004 case 4:
1005 default:
1006 stl_phys(addr, val);
1007 break;
1008 case 8:
1009 stq_phys(addr, val);
1010 break;
1011 }
1012 }
1013 break;
1014 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1015 {
1016 switch (size) {
1017 case 1:
1018 stb_phys((target_phys_addr_t)addr
1019 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1020 break;
1021 case 2:
1022 stw_phys((target_phys_addr_t)addr
1023 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1024 break;
1025 case 4:
1026 default:
1027 stl_phys((target_phys_addr_t)addr
1028 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1029 break;
1030 case 8:
1031 stq_phys((target_phys_addr_t)addr
1032 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1033 break;
1034 }
1035 }
1036 break;
1037 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1038 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1039 Turbosparc snoop RAM */
1040 case 0x32: /* store buffer control or Turbosparc page table
1041 descriptor diagnostic */
1042 case 0x36: /* I-cache flash clear */
1043 case 0x37: /* D-cache flash clear */
1044 break;
1045 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1046 {
1047 int reg = (addr >> 8) & 3;
1048
1049 switch (reg) {
1050 case 0: /* Breakpoint Value (Addr) */
1051 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1052 break;
1053 case 1: /* Breakpoint Mask */
1054 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1055 break;
1056 case 2: /* Breakpoint Control */
1057 env->mmubpregs[reg] = (val & 0x7fULL);
1058 break;
1059 case 3: /* Breakpoint Status */
1060 env->mmubpregs[reg] = (val & 0xfULL);
1061 break;
1062 }
1063 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1064 env->mmuregs[reg]);
1065 }
1066 break;
1067 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1068 env->mmubpctrv = val & 0xffffffff;
1069 break;
1070 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1071 env->mmubpctrc = val & 0x3;
1072 break;
1073 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1074 env->mmubpctrs = val & 0x3;
1075 break;
1076 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1077 env->mmubpaction = val & 0x1fff;
1078 break;
1079 case 8: /* User code access, XXX */
1080 case 9: /* Supervisor code access, XXX */
1081 default:
1082 cpu_unassigned_access(env, addr, 1, 0, asi, size);
1083 break;
1084 }
1085 #ifdef DEBUG_ASI
1086 dump_asi("write", addr, asi, size, val);
1087 #endif
1088 }
1089
1090 #endif /* CONFIG_USER_ONLY */
1091 #else /* TARGET_SPARC64 */
1092
1093 #ifdef CONFIG_USER_ONLY
1094 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1095 int sign)
1096 {
1097 uint64_t ret = 0;
1098 #if defined(DEBUG_ASI)
1099 target_ulong last_addr = addr;
1100 #endif
1101
1102 if (asi < 0x80) {
1103 helper_raise_exception(env, TT_PRIV_ACT);
1104 }
1105
1106 helper_check_align(env, addr, size - 1);
1107 addr = asi_address_mask(env, asi, addr);
1108
1109 switch (asi) {
1110 case 0x82: /* Primary no-fault */
1111 case 0x8a: /* Primary no-fault LE */
1112 if (page_check_range(addr, size, PAGE_READ) == -1) {
1113 #ifdef DEBUG_ASI
1114 dump_asi("read ", last_addr, asi, size, ret);
1115 #endif
1116 return 0;
1117 }
1118 /* Fall through */
1119 case 0x80: /* Primary */
1120 case 0x88: /* Primary LE */
1121 {
1122 switch (size) {
1123 case 1:
1124 ret = ldub_raw(addr);
1125 break;
1126 case 2:
1127 ret = lduw_raw(addr);
1128 break;
1129 case 4:
1130 ret = ldl_raw(addr);
1131 break;
1132 default:
1133 case 8:
1134 ret = ldq_raw(addr);
1135 break;
1136 }
1137 }
1138 break;
1139 case 0x83: /* Secondary no-fault */
1140 case 0x8b: /* Secondary no-fault LE */
1141 if (page_check_range(addr, size, PAGE_READ) == -1) {
1142 #ifdef DEBUG_ASI
1143 dump_asi("read ", last_addr, asi, size, ret);
1144 #endif
1145 return 0;
1146 }
1147 /* Fall through */
1148 case 0x81: /* Secondary */
1149 case 0x89: /* Secondary LE */
1150 /* XXX */
1151 break;
1152 default:
1153 break;
1154 }
1155
1156 /* Convert from little endian */
1157 switch (asi) {
1158 case 0x88: /* Primary LE */
1159 case 0x89: /* Secondary LE */
1160 case 0x8a: /* Primary no-fault LE */
1161 case 0x8b: /* Secondary no-fault LE */
1162 switch (size) {
1163 case 2:
1164 ret = bswap16(ret);
1165 break;
1166 case 4:
1167 ret = bswap32(ret);
1168 break;
1169 case 8:
1170 ret = bswap64(ret);
1171 break;
1172 default:
1173 break;
1174 }
1175 default:
1176 break;
1177 }
1178
1179 /* Convert to signed number */
1180 if (sign) {
1181 switch (size) {
1182 case 1:
1183 ret = (int8_t) ret;
1184 break;
1185 case 2:
1186 ret = (int16_t) ret;
1187 break;
1188 case 4:
1189 ret = (int32_t) ret;
1190 break;
1191 default:
1192 break;
1193 }
1194 }
1195 #ifdef DEBUG_ASI
1196 dump_asi("read ", last_addr, asi, size, ret);
1197 #endif
1198 return ret;
1199 }
1200
1201 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1202 int asi, int size)
1203 {
1204 #ifdef DEBUG_ASI
1205 dump_asi("write", addr, asi, size, val);
1206 #endif
1207 if (asi < 0x80) {
1208 helper_raise_exception(env, TT_PRIV_ACT);
1209 }
1210
1211 helper_check_align(env, addr, size - 1);
1212 addr = asi_address_mask(env, asi, addr);
1213
1214 /* Convert to little endian */
1215 switch (asi) {
1216 case 0x88: /* Primary LE */
1217 case 0x89: /* Secondary LE */
1218 switch (size) {
1219 case 2:
1220 val = bswap16(val);
1221 break;
1222 case 4:
1223 val = bswap32(val);
1224 break;
1225 case 8:
1226 val = bswap64(val);
1227 break;
1228 default:
1229 break;
1230 }
1231 default:
1232 break;
1233 }
1234
1235 switch (asi) {
1236 case 0x80: /* Primary */
1237 case 0x88: /* Primary LE */
1238 {
1239 switch (size) {
1240 case 1:
1241 stb_raw(addr, val);
1242 break;
1243 case 2:
1244 stw_raw(addr, val);
1245 break;
1246 case 4:
1247 stl_raw(addr, val);
1248 break;
1249 case 8:
1250 default:
1251 stq_raw(addr, val);
1252 break;
1253 }
1254 }
1255 break;
1256 case 0x81: /* Secondary */
1257 case 0x89: /* Secondary LE */
1258 /* XXX */
1259 return;
1260
1261 case 0x82: /* Primary no-fault, RO */
1262 case 0x83: /* Secondary no-fault, RO */
1263 case 0x8a: /* Primary no-fault LE, RO */
1264 case 0x8b: /* Secondary no-fault LE, RO */
1265 default:
1266 helper_raise_exception(env, TT_DATA_ACCESS);
1267 return;
1268 }
1269 }
1270
1271 #else /* CONFIG_USER_ONLY */
1272
1273 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1274 int sign)
1275 {
1276 uint64_t ret = 0;
1277 #if defined(DEBUG_ASI)
1278 target_ulong last_addr = addr;
1279 #endif
1280
1281 asi &= 0xff;
1282
1283 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1284 || (cpu_has_hypervisor(env)
1285 && asi >= 0x30 && asi < 0x80
1286 && !(env->hpstate & HS_PRIV))) {
1287 helper_raise_exception(env, TT_PRIV_ACT);
1288 }
1289
1290 helper_check_align(env, addr, size - 1);
1291 addr = asi_address_mask(env, asi, addr);
1292
1293 /* process nonfaulting loads first */
1294 if ((asi & 0xf6) == 0x82) {
1295 int mmu_idx;
1296
1297 /* secondary space access has lowest asi bit equal to 1 */
1298 if (env->pstate & PS_PRIV) {
1299 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1300 } else {
1301 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1302 }
1303
1304 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1305 #ifdef DEBUG_ASI
1306 dump_asi("read ", last_addr, asi, size, ret);
1307 #endif
1308 /* env->exception_index is set in get_physical_address_data(). */
1309 helper_raise_exception(env, env->exception_index);
1310 }
1311
1312 /* convert nonfaulting load ASIs to normal load ASIs */
1313 asi &= ~0x02;
1314 }
1315
1316 switch (asi) {
1317 case 0x10: /* As if user primary */
1318 case 0x11: /* As if user secondary */
1319 case 0x18: /* As if user primary LE */
1320 case 0x19: /* As if user secondary LE */
1321 case 0x80: /* Primary */
1322 case 0x81: /* Secondary */
1323 case 0x88: /* Primary LE */
1324 case 0x89: /* Secondary LE */
1325 case 0xe2: /* UA2007 Primary block init */
1326 case 0xe3: /* UA2007 Secondary block init */
1327 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1328 if (cpu_hypervisor_mode(env)) {
1329 switch (size) {
1330 case 1:
1331 ret = cpu_ldub_hypv(env, addr);
1332 break;
1333 case 2:
1334 ret = cpu_lduw_hypv(env, addr);
1335 break;
1336 case 4:
1337 ret = cpu_ldl_hypv(env, addr);
1338 break;
1339 default:
1340 case 8:
1341 ret = cpu_ldq_hypv(env, addr);
1342 break;
1343 }
1344 } else {
1345 /* secondary space access has lowest asi bit equal to 1 */
1346 if (asi & 1) {
1347 switch (size) {
1348 case 1:
1349 ret = cpu_ldub_kernel_secondary(env, addr);
1350 break;
1351 case 2:
1352 ret = cpu_lduw_kernel_secondary(env, addr);
1353 break;
1354 case 4:
1355 ret = cpu_ldl_kernel_secondary(env, addr);
1356 break;
1357 default:
1358 case 8:
1359 ret = cpu_ldq_kernel_secondary(env, addr);
1360 break;
1361 }
1362 } else {
1363 switch (size) {
1364 case 1:
1365 ret = cpu_ldub_kernel(env, addr);
1366 break;
1367 case 2:
1368 ret = cpu_lduw_kernel(env, addr);
1369 break;
1370 case 4:
1371 ret = cpu_ldl_kernel(env, addr);
1372 break;
1373 default:
1374 case 8:
1375 ret = cpu_ldq_kernel(env, addr);
1376 break;
1377 }
1378 }
1379 }
1380 } else {
1381 /* secondary space access has lowest asi bit equal to 1 */
1382 if (asi & 1) {
1383 switch (size) {
1384 case 1:
1385 ret = cpu_ldub_user_secondary(env, addr);
1386 break;
1387 case 2:
1388 ret = cpu_lduw_user_secondary(env, addr);
1389 break;
1390 case 4:
1391 ret = cpu_ldl_user_secondary(env, addr);
1392 break;
1393 default:
1394 case 8:
1395 ret = cpu_ldq_user_secondary(env, addr);
1396 break;
1397 }
1398 } else {
1399 switch (size) {
1400 case 1:
1401 ret = cpu_ldub_user(env, addr);
1402 break;
1403 case 2:
1404 ret = cpu_lduw_user(env, addr);
1405 break;
1406 case 4:
1407 ret = cpu_ldl_user(env, addr);
1408 break;
1409 default:
1410 case 8:
1411 ret = cpu_ldq_user(env, addr);
1412 break;
1413 }
1414 }
1415 }
1416 break;
1417 case 0x14: /* Bypass */
1418 case 0x15: /* Bypass, non-cacheable */
1419 case 0x1c: /* Bypass LE */
1420 case 0x1d: /* Bypass, non-cacheable LE */
1421 {
1422 switch (size) {
1423 case 1:
1424 ret = ldub_phys(addr);
1425 break;
1426 case 2:
1427 ret = lduw_phys(addr);
1428 break;
1429 case 4:
1430 ret = ldl_phys(addr);
1431 break;
1432 default:
1433 case 8:
1434 ret = ldq_phys(addr);
1435 break;
1436 }
1437 break;
1438 }
1439 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1440 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1441 Only ldda allowed */
1442 helper_raise_exception(env, TT_ILL_INSN);
1443 return 0;
1444 case 0x04: /* Nucleus */
1445 case 0x0c: /* Nucleus Little Endian (LE) */
1446 {
1447 switch (size) {
1448 case 1:
1449 ret = cpu_ldub_nucleus(env, addr);
1450 break;
1451 case 2:
1452 ret = cpu_lduw_nucleus(env, addr);
1453 break;
1454 case 4:
1455 ret = cpu_ldl_nucleus(env, addr);
1456 break;
1457 default:
1458 case 8:
1459 ret = cpu_ldq_nucleus(env, addr);
1460 break;
1461 }
1462 break;
1463 }
1464 case 0x4a: /* UPA config */
1465 /* XXX */
1466 break;
1467 case 0x45: /* LSU */
1468 ret = env->lsu;
1469 break;
1470 case 0x50: /* I-MMU regs */
1471 {
1472 int reg = (addr >> 3) & 0xf;
1473
1474 if (reg == 0) {
1475 /* I-TSB Tag Target register */
1476 ret = ultrasparc_tag_target(env->immu.tag_access);
1477 } else {
1478 ret = env->immuregs[reg];
1479 }
1480
1481 break;
1482 }
1483 case 0x51: /* I-MMU 8k TSB pointer */
1484 {
1485 /* env->immuregs[5] holds I-MMU TSB register value
1486 env->immuregs[6] holds I-MMU Tag Access register value */
1487 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1488 8*1024);
1489 break;
1490 }
1491 case 0x52: /* I-MMU 64k TSB pointer */
1492 {
1493 /* env->immuregs[5] holds I-MMU TSB register value
1494 env->immuregs[6] holds I-MMU Tag Access register value */
1495 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1496 64*1024);
1497 break;
1498 }
1499 case 0x55: /* I-MMU data access */
1500 {
1501 int reg = (addr >> 3) & 0x3f;
1502
1503 ret = env->itlb[reg].tte;
1504 break;
1505 }
1506 case 0x56: /* I-MMU tag read */
1507 {
1508 int reg = (addr >> 3) & 0x3f;
1509
1510 ret = env->itlb[reg].tag;
1511 break;
1512 }
1513 case 0x58: /* D-MMU regs */
1514 {
1515 int reg = (addr >> 3) & 0xf;
1516
1517 if (reg == 0) {
1518 /* D-TSB Tag Target register */
1519 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1520 } else {
1521 ret = env->dmmuregs[reg];
1522 }
1523 break;
1524 }
1525 case 0x59: /* D-MMU 8k TSB pointer */
1526 {
1527 /* env->dmmuregs[5] holds D-MMU TSB register value
1528 env->dmmuregs[6] holds D-MMU Tag Access register value */
1529 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1530 8*1024);
1531 break;
1532 }
1533 case 0x5a: /* D-MMU 64k TSB pointer */
1534 {
1535 /* env->dmmuregs[5] holds D-MMU TSB register value
1536 env->dmmuregs[6] holds D-MMU Tag Access register value */
1537 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1538 64*1024);
1539 break;
1540 }
1541 case 0x5d: /* D-MMU data access */
1542 {
1543 int reg = (addr >> 3) & 0x3f;
1544
1545 ret = env->dtlb[reg].tte;
1546 break;
1547 }
1548 case 0x5e: /* D-MMU tag read */
1549 {
1550 int reg = (addr >> 3) & 0x3f;
1551
1552 ret = env->dtlb[reg].tag;
1553 break;
1554 }
1555 case 0x48: /* Interrupt dispatch, RO */
1556 break;
1557 case 0x49: /* Interrupt data receive */
1558 ret = env->ivec_status;
1559 break;
1560 case 0x7f: /* Incoming interrupt vector, RO */
1561 {
1562 int reg = (addr >> 4) & 0x3;
1563 if (reg < 3) {
1564 ret = env->ivec_data[reg];
1565 }
1566 break;
1567 }
1568 case 0x46: /* D-cache data */
1569 case 0x47: /* D-cache tag access */
1570 case 0x4b: /* E-cache error enable */
1571 case 0x4c: /* E-cache asynchronous fault status */
1572 case 0x4d: /* E-cache asynchronous fault address */
1573 case 0x4e: /* E-cache tag data */
1574 case 0x66: /* I-cache instruction access */
1575 case 0x67: /* I-cache tag access */
1576 case 0x6e: /* I-cache predecode */
1577 case 0x6f: /* I-cache LRU etc. */
1578 case 0x76: /* E-cache tag */
1579 case 0x7e: /* E-cache tag */
1580 break;
1581 case 0x5b: /* D-MMU data pointer */
1582 case 0x54: /* I-MMU data in, WO */
1583 case 0x57: /* I-MMU demap, WO */
1584 case 0x5c: /* D-MMU data in, WO */
1585 case 0x5f: /* D-MMU demap, WO */
1586 case 0x77: /* Interrupt vector, WO */
1587 default:
1588 cpu_unassigned_access(env, addr, 0, 0, 1, size);
1589 ret = 0;
1590 break;
1591 }
1592
1593 /* Convert from little endian */
1594 switch (asi) {
1595 case 0x0c: /* Nucleus Little Endian (LE) */
1596 case 0x18: /* As if user primary LE */
1597 case 0x19: /* As if user secondary LE */
1598 case 0x1c: /* Bypass LE */
1599 case 0x1d: /* Bypass, non-cacheable LE */
1600 case 0x88: /* Primary LE */
1601 case 0x89: /* Secondary LE */
1602 switch(size) {
1603 case 2:
1604 ret = bswap16(ret);
1605 break;
1606 case 4:
1607 ret = bswap32(ret);
1608 break;
1609 case 8:
1610 ret = bswap64(ret);
1611 break;
1612 default:
1613 break;
1614 }
1615 default:
1616 break;
1617 }
1618
1619 /* Convert to signed number */
1620 if (sign) {
1621 switch (size) {
1622 case 1:
1623 ret = (int8_t) ret;
1624 break;
1625 case 2:
1626 ret = (int16_t) ret;
1627 break;
1628 case 4:
1629 ret = (int32_t) ret;
1630 break;
1631 default:
1632 break;
1633 }
1634 }
1635 #ifdef DEBUG_ASI
1636 dump_asi("read ", last_addr, asi, size, ret);
1637 #endif
1638 return ret;
1639 }
1640
1641 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1642 int asi, int size)
1643 {
1644 #ifdef DEBUG_ASI
1645 dump_asi("write", addr, asi, size, val);
1646 #endif
1647
1648 asi &= 0xff;
1649
1650 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1651 || (cpu_has_hypervisor(env)
1652 && asi >= 0x30 && asi < 0x80
1653 && !(env->hpstate & HS_PRIV))) {
1654 helper_raise_exception(env, TT_PRIV_ACT);
1655 }
1656
1657 helper_check_align(env, addr, size - 1);
1658 addr = asi_address_mask(env, asi, addr);
1659
1660 /* Convert to little endian */
1661 switch (asi) {
1662 case 0x0c: /* Nucleus Little Endian (LE) */
1663 case 0x18: /* As if user primary LE */
1664 case 0x19: /* As if user secondary LE */
1665 case 0x1c: /* Bypass LE */
1666 case 0x1d: /* Bypass, non-cacheable LE */
1667 case 0x88: /* Primary LE */
1668 case 0x89: /* Secondary LE */
1669 switch (size) {
1670 case 2:
1671 val = bswap16(val);
1672 break;
1673 case 4:
1674 val = bswap32(val);
1675 break;
1676 case 8:
1677 val = bswap64(val);
1678 break;
1679 default:
1680 break;
1681 }
1682 default:
1683 break;
1684 }
1685
1686 switch (asi) {
1687 case 0x10: /* As if user primary */
1688 case 0x11: /* As if user secondary */
1689 case 0x18: /* As if user primary LE */
1690 case 0x19: /* As if user secondary LE */
1691 case 0x80: /* Primary */
1692 case 0x81: /* Secondary */
1693 case 0x88: /* Primary LE */
1694 case 0x89: /* Secondary LE */
1695 case 0xe2: /* UA2007 Primary block init */
1696 case 0xe3: /* UA2007 Secondary block init */
1697 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1698 if (cpu_hypervisor_mode(env)) {
1699 switch (size) {
1700 case 1:
1701 cpu_stb_hypv(env, addr, val);
1702 break;
1703 case 2:
1704 cpu_stw_hypv(env, addr, val);
1705 break;
1706 case 4:
1707 cpu_stl_hypv(env, addr, val);
1708 break;
1709 case 8:
1710 default:
1711 cpu_stq_hypv(env, addr, val);
1712 break;
1713 }
1714 } else {
1715 /* secondary space access has lowest asi bit equal to 1 */
1716 if (asi & 1) {
1717 switch (size) {
1718 case 1:
1719 cpu_stb_kernel_secondary(env, addr, val);
1720 break;
1721 case 2:
1722 cpu_stw_kernel_secondary(env, addr, val);
1723 break;
1724 case 4:
1725 cpu_stl_kernel_secondary(env, addr, val);
1726 break;
1727 case 8:
1728 default:
1729 cpu_stq_kernel_secondary(env, addr, val);
1730 break;
1731 }
1732 } else {
1733 switch (size) {
1734 case 1:
1735 cpu_stb_kernel(env, addr, val);
1736 break;
1737 case 2:
1738 cpu_stw_kernel(env, addr, val);
1739 break;
1740 case 4:
1741 cpu_stl_kernel(env, addr, val);
1742 break;
1743 case 8:
1744 default:
1745 cpu_stq_kernel(env, addr, val);
1746 break;
1747 }
1748 }
1749 }
1750 } else {
1751 /* secondary space access has lowest asi bit equal to 1 */
1752 if (asi & 1) {
1753 switch (size) {
1754 case 1:
1755 cpu_stb_user_secondary(env, addr, val);
1756 break;
1757 case 2:
1758 cpu_stw_user_secondary(env, addr, val);
1759 break;
1760 case 4:
1761 cpu_stl_user_secondary(env, addr, val);
1762 break;
1763 case 8:
1764 default:
1765 cpu_stq_user_secondary(env, addr, val);
1766 break;
1767 }
1768 } else {
1769 switch (size) {
1770 case 1:
1771 cpu_stb_user(env, addr, val);
1772 break;
1773 case 2:
1774 cpu_stw_user(env, addr, val);
1775 break;
1776 case 4:
1777 cpu_stl_user(env, addr, val);
1778 break;
1779 case 8:
1780 default:
1781 cpu_stq_user(env, addr, val);
1782 break;
1783 }
1784 }
1785 }
1786 break;
1787 case 0x14: /* Bypass */
1788 case 0x15: /* Bypass, non-cacheable */
1789 case 0x1c: /* Bypass LE */
1790 case 0x1d: /* Bypass, non-cacheable LE */
1791 {
1792 switch (size) {
1793 case 1:
1794 stb_phys(addr, val);
1795 break;
1796 case 2:
1797 stw_phys(addr, val);
1798 break;
1799 case 4:
1800 stl_phys(addr, val);
1801 break;
1802 case 8:
1803 default:
1804 stq_phys(addr, val);
1805 break;
1806 }
1807 }
1808 return;
1809 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1810 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1811 Only ldda allowed */
1812 helper_raise_exception(env, TT_ILL_INSN);
1813 return;
1814 case 0x04: /* Nucleus */
1815 case 0x0c: /* Nucleus Little Endian (LE) */
1816 {
1817 switch (size) {
1818 case 1:
1819 cpu_stb_nucleus(env, addr, val);
1820 break;
1821 case 2:
1822 cpu_stw_nucleus(env, addr, val);
1823 break;
1824 case 4:
1825 cpu_stl_nucleus(env, addr, val);
1826 break;
1827 default:
1828 case 8:
1829 cpu_stq_nucleus(env, addr, val);
1830 break;
1831 }
1832 break;
1833 }
1834
1835 case 0x4a: /* UPA config */
1836 /* XXX */
1837 return;
1838 case 0x45: /* LSU */
1839 {
1840 uint64_t oldreg;
1841
1842 oldreg = env->lsu;
1843 env->lsu = val & (DMMU_E | IMMU_E);
1844 /* Mappings generated during D/I MMU disabled mode are
1845 invalid in normal mode */
1846 if (oldreg != env->lsu) {
1847 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1848 oldreg, env->lsu);
1849 #ifdef DEBUG_MMU
1850 dump_mmu(stdout, fprintf, env1);
1851 #endif
1852 tlb_flush(env, 1);
1853 }
1854 return;
1855 }
1856 case 0x50: /* I-MMU regs */
1857 {
1858 int reg = (addr >> 3) & 0xf;
1859 uint64_t oldreg;
1860
1861 oldreg = env->immuregs[reg];
1862 switch (reg) {
1863 case 0: /* RO */
1864 return;
1865 case 1: /* Not in I-MMU */
1866 case 2:
1867 return;
1868 case 3: /* SFSR */
1869 if ((val & 1) == 0) {
1870 val = 0; /* Clear SFSR */
1871 }
1872 env->immu.sfsr = val;
1873 break;
1874 case 4: /* RO */
1875 return;
1876 case 5: /* TSB access */
1877 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1878 PRIx64 "\n", env->immu.tsb, val);
1879 env->immu.tsb = val;
1880 break;
1881 case 6: /* Tag access */
1882 env->immu.tag_access = val;
1883 break;
1884 case 7:
1885 case 8:
1886 return;
1887 default:
1888 break;
1889 }
1890
1891 if (oldreg != env->immuregs[reg]) {
1892 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1893 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1894 }
1895 #ifdef DEBUG_MMU
1896 dump_mmu(stdout, fprintf, env);
1897 #endif
1898 return;
1899 }
1900 case 0x54: /* I-MMU data in */
1901 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1902 return;
1903 case 0x55: /* I-MMU data access */
1904 {
1905 /* TODO: auto demap */
1906
1907 unsigned int i = (addr >> 3) & 0x3f;
1908
1909 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1910
1911 #ifdef DEBUG_MMU
1912 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1913 dump_mmu(stdout, fprintf, env);
1914 #endif
1915 return;
1916 }
1917 case 0x57: /* I-MMU demap */
1918 demap_tlb(env->itlb, addr, "immu", env);
1919 return;
1920 case 0x58: /* D-MMU regs */
1921 {
1922 int reg = (addr >> 3) & 0xf;
1923 uint64_t oldreg;
1924
1925 oldreg = env->dmmuregs[reg];
1926 switch (reg) {
1927 case 0: /* RO */
1928 case 4:
1929 return;
1930 case 3: /* SFSR */
1931 if ((val & 1) == 0) {
1932 val = 0; /* Clear SFSR, Fault address */
1933 env->dmmu.sfar = 0;
1934 }
1935 env->dmmu.sfsr = val;
1936 break;
1937 case 1: /* Primary context */
1938 env->dmmu.mmu_primary_context = val;
1939 /* can be optimized to only flush MMU_USER_IDX
1940 and MMU_KERNEL_IDX entries */
1941 tlb_flush(env, 1);
1942 break;
1943 case 2: /* Secondary context */
1944 env->dmmu.mmu_secondary_context = val;
1945 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1946 and MMU_KERNEL_SECONDARY_IDX entries */
1947 tlb_flush(env, 1);
1948 break;
1949 case 5: /* TSB access */
1950 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1951 PRIx64 "\n", env->dmmu.tsb, val);
1952 env->dmmu.tsb = val;
1953 break;
1954 case 6: /* Tag access */
1955 env->dmmu.tag_access = val;
1956 break;
1957 case 7: /* Virtual Watchpoint */
1958 case 8: /* Physical Watchpoint */
1959 default:
1960 env->dmmuregs[reg] = val;
1961 break;
1962 }
1963
1964 if (oldreg != env->dmmuregs[reg]) {
1965 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1966 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1967 }
1968 #ifdef DEBUG_MMU
1969 dump_mmu(stdout, fprintf, env);
1970 #endif
1971 return;
1972 }
1973 case 0x5c: /* D-MMU data in */
1974 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1975 return;
1976 case 0x5d: /* D-MMU data access */
1977 {
1978 unsigned int i = (addr >> 3) & 0x3f;
1979
1980 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1981
1982 #ifdef DEBUG_MMU
1983 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1984 dump_mmu(stdout, fprintf, env);
1985 #endif
1986 return;
1987 }
1988 case 0x5f: /* D-MMU demap */
1989 demap_tlb(env->dtlb, addr, "dmmu", env);
1990 return;
1991 case 0x49: /* Interrupt data receive */
1992 env->ivec_status = val & 0x20;
1993 return;
1994 case 0x46: /* D-cache data */
1995 case 0x47: /* D-cache tag access */
1996 case 0x4b: /* E-cache error enable */
1997 case 0x4c: /* E-cache asynchronous fault status */
1998 case 0x4d: /* E-cache asynchronous fault address */
1999 case 0x4e: /* E-cache tag data */
2000 case 0x66: /* I-cache instruction access */
2001 case 0x67: /* I-cache tag access */
2002 case 0x6e: /* I-cache predecode */
2003 case 0x6f: /* I-cache LRU etc. */
2004 case 0x76: /* E-cache tag */
2005 case 0x7e: /* E-cache tag */
2006 return;
2007 case 0x51: /* I-MMU 8k TSB pointer, RO */
2008 case 0x52: /* I-MMU 64k TSB pointer, RO */
2009 case 0x56: /* I-MMU tag read, RO */
2010 case 0x59: /* D-MMU 8k TSB pointer, RO */
2011 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2012 case 0x5b: /* D-MMU data pointer, RO */
2013 case 0x5e: /* D-MMU tag read, RO */
2014 case 0x48: /* Interrupt dispatch, RO */
2015 case 0x7f: /* Incoming interrupt vector, RO */
2016 case 0x82: /* Primary no-fault, RO */
2017 case 0x83: /* Secondary no-fault, RO */
2018 case 0x8a: /* Primary no-fault LE, RO */
2019 case 0x8b: /* Secondary no-fault LE, RO */
2020 default:
2021 cpu_unassigned_access(env, addr, 1, 0, 1, size);
2022 return;
2023 }
2024 }
2025 #endif /* CONFIG_USER_ONLY */
2026
2027 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2028 {
2029 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2030 || (cpu_has_hypervisor(env)
2031 && asi >= 0x30 && asi < 0x80
2032 && !(env->hpstate & HS_PRIV))) {
2033 helper_raise_exception(env, TT_PRIV_ACT);
2034 }
2035
2036 addr = asi_address_mask(env, asi, addr);
2037
2038 switch (asi) {
2039 #if !defined(CONFIG_USER_ONLY)
2040 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2041 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2042 helper_check_align(env, addr, 0xf);
2043 if (rd == 0) {
2044 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2045 if (asi == 0x2c) {
2046 bswap64s(&env->gregs[1]);
2047 }
2048 } else if (rd < 8) {
2049 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2050 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2051 if (asi == 0x2c) {
2052 bswap64s(&env->gregs[rd]);
2053 bswap64s(&env->gregs[rd + 1]);
2054 }
2055 } else {
2056 env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
2057 env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2058 if (asi == 0x2c) {
2059 bswap64s(&env->regwptr[rd]);
2060 bswap64s(&env->regwptr[rd + 1]);
2061 }
2062 }
2063 break;
2064 #endif
2065 default:
2066 helper_check_align(env, addr, 0x3);
2067 if (rd == 0) {
2068 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2069 } else if (rd < 8) {
2070 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2071 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2072 } else {
2073 env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2074 env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2075 }
2076 break;
2077 }
2078 }
2079
2080 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2081 int rd)
2082 {
2083 unsigned int i;
2084 target_ulong val;
2085
2086 helper_check_align(env, addr, 3);
2087 addr = asi_address_mask(env, asi, addr);
2088
2089 switch (asi) {
2090 case 0xf0: /* UA2007/JPS1 Block load primary */
2091 case 0xf1: /* UA2007/JPS1 Block load secondary */
2092 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2093 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2094 if (rd & 7) {
2095 helper_raise_exception(env, TT_ILL_INSN);
2096 return;
2097 }
2098 helper_check_align(env, addr, 0x3f);
2099 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2100 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2101 }
2102 return;
2103
2104 case 0x16: /* UA2007 Block load primary, user privilege */
2105 case 0x17: /* UA2007 Block load secondary, user privilege */
2106 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2107 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2108 case 0x70: /* JPS1 Block load primary, user privilege */
2109 case 0x71: /* JPS1 Block load secondary, user privilege */
2110 case 0x78: /* JPS1 Block load primary LE, user privilege */
2111 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2112 if (rd & 7) {
2113 helper_raise_exception(env, TT_ILL_INSN);
2114 return;
2115 }
2116 helper_check_align(env, addr, 0x3f);
2117 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2118 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2119 }
2120 return;
2121
2122 default:
2123 break;
2124 }
2125
2126 switch (size) {
2127 default:
2128 case 4:
2129 val = helper_ld_asi(env, addr, asi, size, 0);
2130 if (rd & 1) {
2131 env->fpr[rd / 2].l.lower = val;
2132 } else {
2133 env->fpr[rd / 2].l.upper = val;
2134 }
2135 break;
2136 case 8:
2137 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2138 break;
2139 case 16:
2140 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2141 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2142 break;
2143 }
2144 }
2145
2146 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2147 int rd)
2148 {
2149 unsigned int i;
2150 target_ulong val;
2151
2152 helper_check_align(env, addr, 3);
2153 addr = asi_address_mask(env, asi, addr);
2154
2155 switch (asi) {
2156 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2157 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2158 case 0xf0: /* UA2007/JPS1 Block store primary */
2159 case 0xf1: /* UA2007/JPS1 Block store secondary */
2160 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2161 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2162 if (rd & 7) {
2163 helper_raise_exception(env, TT_ILL_INSN);
2164 return;
2165 }
2166 helper_check_align(env, addr, 0x3f);
2167 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2168 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2169 }
2170
2171 return;
2172 case 0x16: /* UA2007 Block load primary, user privilege */
2173 case 0x17: /* UA2007 Block load secondary, user privilege */
2174 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2175 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2176 case 0x70: /* JPS1 Block store primary, user privilege */
2177 case 0x71: /* JPS1 Block store secondary, user privilege */
2178 case 0x78: /* JPS1 Block load primary LE, user privilege */
2179 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2180 if (rd & 7) {
2181 helper_raise_exception(env, TT_ILL_INSN);
2182 return;
2183 }
2184 helper_check_align(env, addr, 0x3f);
2185 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2186 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2187 }
2188
2189 return;
2190 default:
2191 break;
2192 }
2193
2194 switch (size) {
2195 default:
2196 case 4:
2197 if (rd & 1) {
2198 val = env->fpr[rd / 2].l.lower;
2199 } else {
2200 val = env->fpr[rd / 2].l.upper;
2201 }
2202 helper_st_asi(env, addr, val, asi, size);
2203 break;
2204 case 8:
2205 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2206 break;
2207 case 16:
2208 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2209 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2210 break;
2211 }
2212 }
2213
2214 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2215 target_ulong val1, target_ulong val2, uint32_t asi)
2216 {
2217 target_ulong ret;
2218
2219 val2 &= 0xffffffffUL;
2220 ret = helper_ld_asi(env, addr, asi, 4, 0);
2221 ret &= 0xffffffffUL;
2222 if (val2 == ret) {
2223 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2224 }
2225 return ret;
2226 }
2227
2228 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2229 target_ulong val1, target_ulong val2,
2230 uint32_t asi)
2231 {
2232 target_ulong ret;
2233
2234 ret = helper_ld_asi(env, addr, asi, 8, 0);
2235 if (val2 == ret) {
2236 helper_st_asi(env, addr, val1, asi, 8);
2237 }
2238 return ret;
2239 }
2240 #endif /* TARGET_SPARC64 */
2241
2242 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2243 {
2244 /* XXX add 128 bit load */
2245 CPU_QuadU u;
2246
2247 helper_check_align(env, addr, 7);
2248 #if !defined(CONFIG_USER_ONLY)
2249 switch (mem_idx) {
2250 case MMU_USER_IDX:
2251 u.ll.upper = cpu_ldq_user(env, addr);
2252 u.ll.lower = cpu_ldq_user(env, addr + 8);
2253 QT0 = u.q;
2254 break;
2255 case MMU_KERNEL_IDX:
2256 u.ll.upper = cpu_ldq_kernel(env, addr);
2257 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2258 QT0 = u.q;
2259 break;
2260 #ifdef TARGET_SPARC64
2261 case MMU_HYPV_IDX:
2262 u.ll.upper = cpu_ldq_hypv(env, addr);
2263 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2264 QT0 = u.q;
2265 break;
2266 #endif
2267 default:
2268 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2269 break;
2270 }
2271 #else
2272 u.ll.upper = ldq_raw(address_mask(env, addr));
2273 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2274 QT0 = u.q;
2275 #endif
2276 }
2277
2278 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2279 {
2280 /* XXX add 128 bit store */
2281 CPU_QuadU u;
2282
2283 helper_check_align(env, addr, 7);
2284 #if !defined(CONFIG_USER_ONLY)
2285 switch (mem_idx) {
2286 case MMU_USER_IDX:
2287 u.q = QT0;
2288 cpu_stq_user(env, addr, u.ll.upper);
2289 cpu_stq_user(env, addr + 8, u.ll.lower);
2290 break;
2291 case MMU_KERNEL_IDX:
2292 u.q = QT0;
2293 cpu_stq_kernel(env, addr, u.ll.upper);
2294 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2295 break;
2296 #ifdef TARGET_SPARC64
2297 case MMU_HYPV_IDX:
2298 u.q = QT0;
2299 cpu_stq_hypv(env, addr, u.ll.upper);
2300 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2301 break;
2302 #endif
2303 default:
2304 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2305 break;
2306 }
2307 #else
2308 u.q = QT0;
2309 stq_raw(address_mask(env, addr), u.ll.upper);
2310 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2311 #endif
2312 }
2313
2314 #if !defined(CONFIG_USER_ONLY)
2315 #ifndef TARGET_SPARC64
2316 void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
2317 int is_write, int is_exec, int is_asi, int size)
2318 {
2319 int fault_type;
2320
2321 #ifdef DEBUG_UNASSIGNED
2322 if (is_asi) {
2323 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2324 " asi 0x%02x from " TARGET_FMT_lx "\n",
2325 is_exec ? "exec" : is_write ? "write" : "read", size,
2326 size == 1 ? "" : "s", addr, is_asi, env->pc);
2327 } else {
2328 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2329 " from " TARGET_FMT_lx "\n",
2330 is_exec ? "exec" : is_write ? "write" : "read", size,
2331 size == 1 ? "" : "s", addr, env->pc);
2332 }
2333 #endif
2334 /* Don't overwrite translation and access faults */
2335 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2336 if ((fault_type > 4) || (fault_type == 0)) {
2337 env->mmuregs[3] = 0; /* Fault status register */
2338 if (is_asi) {
2339 env->mmuregs[3] |= 1 << 16;
2340 }
2341 if (env->psrs) {
2342 env->mmuregs[3] |= 1 << 5;
2343 }
2344 if (is_exec) {
2345 env->mmuregs[3] |= 1 << 6;
2346 }
2347 if (is_write) {
2348 env->mmuregs[3] |= 1 << 7;
2349 }
2350 env->mmuregs[3] |= (5 << 2) | 2;
2351 /* SuperSPARC will never place instruction fault addresses in the FAR */
2352 if (!is_exec) {
2353 env->mmuregs[4] = addr; /* Fault address register */
2354 }
2355 }
2356 /* overflow (same type fault was not read before another fault) */
2357 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2358 env->mmuregs[3] |= 1;
2359 }
2360
2361 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2362 if (is_exec) {
2363 helper_raise_exception(env, TT_CODE_ACCESS);
2364 } else {
2365 helper_raise_exception(env, TT_DATA_ACCESS);
2366 }
2367 }
2368
2369 /* flush neverland mappings created during no-fault mode,
2370 so the sequential MMU faults report proper fault types */
2371 if (env->mmuregs[0] & MMU_NF) {
2372 tlb_flush(env, 1);
2373 }
2374 }
2375 #else
2376 void cpu_unassigned_access(CPUSPARCState *env, target_phys_addr_t addr,
2377 int is_write, int is_exec, int is_asi, int size)
2378 {
2379 #ifdef DEBUG_UNASSIGNED
2380 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2381 "\n", addr, env->pc);
2382 #endif
2383
2384 if (is_exec) {
2385 helper_raise_exception(env, TT_CODE_ACCESS);
2386 } else {
2387 helper_raise_exception(env, TT_DATA_ACCESS);
2388 }
2389 }
2390 #endif
2391 #endif
2392
2393 #if !defined(CONFIG_USER_ONLY)
2394 /* XXX: make it generic ? */
2395 static void cpu_restore_state2(CPUSPARCState *env, uintptr_t retaddr)
2396 {
2397 TranslationBlock *tb;
2398
2399 if (retaddr) {
2400 /* now we have a real cpu fault */
2401 tb = tb_find_pc(retaddr);
2402 if (tb) {
2403 /* the PC is inside the translated code. It means that we have
2404 a virtual CPU fault */
2405 cpu_restore_state(tb, env, retaddr);
2406 }
2407 }
2408 }
2409
2410 void do_unaligned_access(CPUSPARCState *env, target_ulong addr, int is_write,
2411 int is_user, uintptr_t retaddr)
2412 {
2413 #ifdef DEBUG_UNALIGNED
2414 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2415 "\n", addr, env->pc);
2416 #endif
2417 cpu_restore_state2(env, retaddr);
2418 helper_raise_exception(env, TT_UNALIGNED);
2419 }
2420
2421 /* try to fill the TLB and return an exception if error. If retaddr is
2422 NULL, it means that the function was called in C code (i.e. not
2423 from generated code or from helper.c) */
2424 /* XXX: fix it to restore all registers */
2425 void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx,
2426 uintptr_t retaddr)
2427 {
2428 int ret;
2429
2430 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
2431 if (ret) {
2432 cpu_restore_state2(env, retaddr);
2433 cpu_loop_exit(env);
2434 }
2435 }
2436 #endif
Qemu with PowerPC KVM improvements