PPC: e500: Define addresses as always 64bit
[qemu/agraf.git] / hw / qxl.h
blob31029503fe45d98f9f3e60a51e70972546546521
1 #include "qemu-common.h"
3 #include "console.h"
4 #include "hw.h"
5 #include "pci.h"
6 #include "vga_int.h"
7 #include "qemu-thread.h"
9 #include "ui/qemu-spice.h"
10 #include "ui/spice-display.h"
12 enum qxl_mode {
13 QXL_MODE_UNDEFINED,
14 QXL_MODE_VGA,
15 QXL_MODE_COMPAT, /* spice 0.4.x */
16 QXL_MODE_NATIVE,
19 #ifndef QXL_VRAM64_RANGE_INDEX
20 #define QXL_VRAM64_RANGE_INDEX 4
21 #endif
23 #define QXL_UNDEFINED_IO UINT32_MAX
25 #define QXL_NUM_DIRTY_RECTS 64
27 typedef struct PCIQXLDevice {
28 PCIDevice pci;
29 SimpleSpiceDisplay ssd;
30 int id;
31 uint32_t debug;
32 uint32_t guestdebug;
33 uint32_t cmdlog;
34 enum qxl_mode mode;
35 uint32_t cmdflags;
36 int generation;
37 uint32_t revision;
39 int32_t num_memslots;
40 int32_t num_surfaces;
42 uint32_t current_async;
43 QemuMutex async_lock;
45 struct guest_slots {
46 QXLMemSlot slot;
47 void *ptr;
48 uint64_t size;
49 uint64_t delta;
50 uint32_t active;
51 } guest_slots[NUM_MEMSLOTS];
53 struct guest_primary {
54 QXLSurfaceCreate surface;
55 uint32_t commands;
56 uint32_t resized;
57 int32_t qxl_stride;
58 uint32_t abs_stride;
59 uint32_t bits_pp;
60 uint32_t bytes_pp;
61 uint8_t *data;
62 } guest_primary;
64 struct surfaces {
65 QXLPHYSICAL cmds[NUM_SURFACES];
66 uint32_t count;
67 uint32_t max;
68 } guest_surfaces;
69 QXLPHYSICAL guest_cursor;
71 QemuMutex track_lock;
73 /* thread signaling */
74 QemuThread main;
75 int pipe[2];
77 /* ram pci bar */
78 QXLRam *ram;
79 VGACommonState vga;
80 uint32_t num_free_res;
81 QXLReleaseInfo *last_release;
82 uint32_t last_release_offset;
83 uint32_t oom_running;
85 /* rom pci bar */
86 QXLRom shadow_rom;
87 QXLRom *rom;
88 QXLModes *modes;
89 uint32_t rom_size;
90 MemoryRegion rom_bar;
92 /* vram pci bar */
93 uint32_t vram_size;
94 MemoryRegion vram_bar;
95 uint32_t vram32_size;
96 MemoryRegion vram32_bar;
98 /* io bar */
99 MemoryRegion io_bar;
101 /* user-friendly properties (in megabytes) */
102 uint32_t ram_size_mb;
103 uint32_t vram_size_mb;
104 uint32_t vram32_size_mb;
106 /* qxl_render_update state */
107 int render_update_cookie_num;
108 int num_dirty_rects;
109 QXLRect dirty[QXL_NUM_DIRTY_RECTS];
110 QEMUBH *update_area_bh;
111 } PCIQXLDevice;
113 #define PANIC_ON(x) if ((x)) { \
114 printf("%s: PANIC %s failed\n", __FUNCTION__, #x); \
115 abort(); \
118 #define dprint(_qxl, _level, _fmt, ...) \
119 do { \
120 if (_qxl->debug >= _level) { \
121 fprintf(stderr, "qxl-%d: ", _qxl->id); \
122 fprintf(stderr, _fmt, ## __VA_ARGS__); \
124 } while (0)
126 #define QXL_DEFAULT_REVISION QXL_REVISION_STABLE_V10
128 /* qxl.c */
129 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL phys, int group_id);
130 void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) GCC_FMT_ATTR(2, 3);
132 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
133 struct QXLRect *area, struct QXLRect *dirty_rects,
134 uint32_t num_dirty_rects,
135 uint32_t clear_dirty_region,
136 qxl_async_io async, QXLCookie *cookie);
137 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
138 uint32_t count);
139 void qxl_spice_oom(PCIQXLDevice *qxl);
140 void qxl_spice_reset_memslots(PCIQXLDevice *qxl);
141 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl);
142 void qxl_spice_reset_cursor(PCIQXLDevice *qxl);
144 /* qxl-logger.c */
145 int qxl_log_cmd_cursor(PCIQXLDevice *qxl, QXLCursorCmd *cmd, int group_id);
146 int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext);
148 /* qxl-render.c */
149 void qxl_render_resize(PCIQXLDevice *qxl);
150 void qxl_render_update(PCIQXLDevice *qxl);
151 int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext);
152 void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie);
153 void qxl_render_update_area_bh(void *opaque);