| commit | 4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770 | |
| author | Max Filippov <jcmvbkbc@gmail.com> | |
| Wed, 5 Dec 2012 03:15:21 +0000 (5 07:15 +0400) | ||
| committer | Blue Swirl <blauwirbel@gmail.com> | |
| Sat, 8 Dec 2012 18:48:26 +0000 (8 18:48 +0000) | ||
| tree | 60e3cc172d4aa177b460d5e72b176a8bd3c95915 | treesnapshot (tar.gz zip) |
| parent | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 | commitdiff |
target-xtensa: implement CACHEATTR SR
In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>