fix event fallout in grlib_apbuart.c
[qemu/aliguori.git] / hw / mcf_uart.c
blob35b1a0155cbca8ee4b33aaf9d92dab81a2c35dc0
1 /*
2 * ColdFire UART emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
7 */
8 #include "hw.h"
9 #include "mcf.h"
10 #include "qemu-char.h"
12 typedef struct {
13 uint8_t mr[2];
14 uint8_t sr;
15 uint8_t isr;
16 uint8_t imr;
17 uint8_t bg1;
18 uint8_t bg2;
19 uint8_t fifo[4];
20 uint8_t tb;
21 int current_mr;
22 int fifo_len;
23 int tx_enabled;
24 int rx_enabled;
25 qemu_irq irq;
26 CharDriverState *chr;
27 } mcf_uart_state;
29 /* UART Status Register bits. */
30 #define MCF_UART_RxRDY 0x01
31 #define MCF_UART_FFULL 0x02
32 #define MCF_UART_TxRDY 0x04
33 #define MCF_UART_TxEMP 0x08
34 #define MCF_UART_OE 0x10
35 #define MCF_UART_PE 0x20
36 #define MCF_UART_FE 0x40
37 #define MCF_UART_RB 0x80
39 /* Interrupt flags. */
40 #define MCF_UART_TxINT 0x01
41 #define MCF_UART_RxINT 0x02
42 #define MCF_UART_DBINT 0x04
43 #define MCF_UART_COSINT 0x80
45 /* UMR1 flags. */
46 #define MCF_UART_BC0 0x01
47 #define MCF_UART_BC1 0x02
48 #define MCF_UART_PT 0x04
49 #define MCF_UART_PM0 0x08
50 #define MCF_UART_PM1 0x10
51 #define MCF_UART_ERR 0x20
52 #define MCF_UART_RxIRQ 0x40
53 #define MCF_UART_RxRTS 0x80
55 static void mcf_uart_update_handlers(mcf_uart_state *s);
57 static void mcf_uart_update(mcf_uart_state *s)
59 s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT);
60 if (s->sr & MCF_UART_TxRDY)
61 s->isr |= MCF_UART_TxINT;
62 if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
63 ? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
64 s->isr |= MCF_UART_RxINT;
66 qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
69 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr)
71 mcf_uart_state *s = (mcf_uart_state *)opaque;
72 switch (addr & 0x3f) {
73 case 0x00:
74 return s->mr[s->current_mr];
75 case 0x04:
76 return s->sr;
77 case 0x0c:
79 uint8_t val;
80 int i;
82 if (s->fifo_len == 0)
83 return 0;
85 val = s->fifo[0];
86 s->fifo_len--;
87 for (i = 0; i < s->fifo_len; i++)
88 s->fifo[i] = s->fifo[i + 1];
89 s->sr &= ~MCF_UART_FFULL;
90 if (s->fifo_len == 0)
91 s->sr &= ~MCF_UART_RxRDY;
92 mcf_uart_update(s);
93 mcf_uart_update_handlers(s);
94 return val;
96 case 0x10:
97 /* TODO: Implement IPCR. */
98 return 0;
99 case 0x14:
100 return s->isr;
101 case 0x18:
102 return s->bg1;
103 case 0x1c:
104 return s->bg2;
105 default:
106 return 0;
110 /* Update TxRDY flag and set data if present and enabled. */
111 static void mcf_uart_do_tx(mcf_uart_state *s)
113 if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
114 if (s->chr)
115 qemu_chr_fe_write(s->chr, (unsigned char *)&s->tb, 1);
116 s->sr |= MCF_UART_TxEMP;
118 if (s->tx_enabled) {
119 s->sr |= MCF_UART_TxRDY;
120 } else {
121 s->sr &= ~MCF_UART_TxRDY;
123 mcf_uart_update_handlers(s);
126 static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
128 /* Misc command. */
129 switch ((cmd >> 4) & 3) {
130 case 0: /* No-op. */
131 break;
132 case 1: /* Reset mode register pointer. */
133 s->current_mr = 0;
134 break;
135 case 2: /* Reset receiver. */
136 s->rx_enabled = 0;
137 s->fifo_len = 0;
138 s->sr &= ~(MCF_UART_RxRDY | MCF_UART_FFULL);
139 mcf_uart_update_handlers(s);
140 break;
141 case 3: /* Reset transmitter. */
142 s->tx_enabled = 0;
143 s->sr |= MCF_UART_TxEMP;
144 s->sr &= ~MCF_UART_TxRDY;
145 mcf_uart_update_handlers(s);
146 break;
147 case 4: /* Reset error status. */
148 break;
149 case 5: /* Reset break-change interrupt. */
150 s->isr &= ~MCF_UART_DBINT;
151 break;
152 case 6: /* Start break. */
153 case 7: /* Stop break. */
154 break;
157 /* Transmitter command. */
158 switch ((cmd >> 2) & 3) {
159 case 0: /* No-op. */
160 break;
161 case 1: /* Enable. */
162 s->tx_enabled = 1;
163 mcf_uart_do_tx(s);
164 break;
165 case 2: /* Disable. */
166 s->tx_enabled = 0;
167 mcf_uart_do_tx(s);
168 break;
169 case 3: /* Reserved. */
170 fprintf(stderr, "mcf_uart: Bad TX command\n");
171 break;
174 /* Receiver command. */
175 switch (cmd & 3) {
176 case 0: /* No-op. */
177 break;
178 case 1: /* Enable. */
179 s->rx_enabled = 1;
180 mcf_uart_update_handlers(s);
181 break;
182 case 2:
183 s->rx_enabled = 0;
184 mcf_uart_update_handlers(s);
185 break;
186 case 3: /* Reserved. */
187 fprintf(stderr, "mcf_uart: Bad RX command\n");
188 break;
192 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val)
194 mcf_uart_state *s = (mcf_uart_state *)opaque;
195 switch (addr & 0x3f) {
196 case 0x00:
197 s->mr[s->current_mr] = val;
198 s->current_mr = 1;
199 break;
200 case 0x04:
201 /* CSR is ignored. */
202 break;
203 case 0x08: /* Command Register. */
204 mcf_do_command(s, val);
205 break;
206 case 0x0c: /* Transmit Buffer. */
207 s->sr &= ~MCF_UART_TxEMP;
208 s->tb = val;
209 mcf_uart_do_tx(s);
210 mcf_uart_update_handlers(s);
211 break;
212 case 0x10:
213 /* ACR is ignored. */
214 break;
215 case 0x14:
216 s->imr = val;
217 break;
218 default:
219 break;
221 mcf_uart_update(s);
224 static void mcf_uart_reset(mcf_uart_state *s)
226 s->fifo_len = 0;
227 s->mr[0] = 0;
228 s->mr[1] = 0;
229 s->sr = MCF_UART_TxEMP;
230 s->tx_enabled = 0;
231 s->rx_enabled = 0;
232 s->isr = 0;
233 s->imr = 0;
234 mcf_uart_update_handlers(s);
237 static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
239 /* Break events overwrite the last byte if the fifo is full. */
240 if (s->fifo_len == 4)
241 s->fifo_len--;
243 s->fifo[s->fifo_len] = data;
244 s->fifo_len++;
245 s->sr |= MCF_UART_RxRDY;
246 if (s->fifo_len == 4)
247 s->sr |= MCF_UART_FFULL;
249 mcf_uart_update_handlers(s);
250 mcf_uart_update(s);
253 static int mcf_uart_event(void *opaque, int event, void *data)
255 mcf_uart_state *s = (mcf_uart_state *)opaque;
257 switch (event) {
258 case CHR_EVENT_BREAK:
259 s->isr |= MCF_UART_DBINT;
260 mcf_uart_push_byte(s, 0);
261 break;
262 default:
263 break;
265 return 0;
268 static int mcf_uart_can_receive(mcf_uart_state *s)
270 return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
273 static void mcf_uart_receive(mcf_uart_state *s, const uint8_t *buf, int size)
275 mcf_uart_push_byte(s, buf[0]);
278 static void mcf_uart_receive_handler(void *opaque)
280 mcf_uart_state *s = opaque;
281 uint8_t buf[32];
282 int size;
284 size = mcf_uart_can_receive(s);
285 size = MIN(size, sizeof(buf));
286 size = qemu_chr_fe_read(s->chr, buf, size);
288 mcf_uart_receive(s, buf, size);
291 static void mcf_uart_update_handlers(mcf_uart_state *s)
293 if (mcf_uart_can_receive(s) > 0) {
294 qemu_chr_fe_set_handlers(s->chr, mcf_uart_receive_handler,
295 NULL, mcf_uart_event, s);
296 } else {
297 qemu_chr_fe_set_handlers(s->chr, NULL, NULL, mcf_uart_event, s);
301 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
303 mcf_uart_state *s;
305 s = qemu_mallocz(sizeof(mcf_uart_state));
306 s->chr = chr;
307 s->irq = irq;
308 if (chr) {
309 qemu_chr_fe_open(chr);
311 mcf_uart_reset(s);
312 return s;
316 static CPUReadMemoryFunc * const mcf_uart_readfn[] = {
317 mcf_uart_read,
318 mcf_uart_read,
319 mcf_uart_read
322 static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
323 mcf_uart_write,
324 mcf_uart_write,
325 mcf_uart_write
328 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
329 CharDriverState *chr)
331 mcf_uart_state *s;
332 int iomemtype;
334 s = mcf_uart_init(irq, chr);
335 iomemtype = cpu_register_io_memory(mcf_uart_readfn,
336 mcf_uart_writefn, s,
337 DEVICE_NATIVE_ENDIAN);
338 cpu_register_physical_memory(base, 0x40, iomemtype);