hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msix.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42 #include "blockdev.h"
  43 #include "ui/qemu-spice.h"
  44 #include "memory.h"
  45
  46 /* output Bochs bios info messages */
  47 //#define DEBUG_BIOS
  48
  49 /* debug PC/ISA interrupts */
  50 //#define DEBUG_IRQ
  51
  52 #ifdef DEBUG_IRQ
  53 #define DPRINTF(fmt, ...)                                       \
  54     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  55 #else
  56 #define DPRINTF(fmt, ...)
  57 #endif
  58
  59 #define BIOS_FILENAME "bios.bin"
  60
  61 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  62
  63 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  64 #define ACPI_DATA_SIZE       0x10000
  65 #define BIOS_CFG_IOPORT 0x510
  66 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  67 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  68 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  69 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  70 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  71
  72 #define MSI_ADDR_BASE 0xfee00000
  73
  74 #define E820_NR_ENTRIES         16
  75
  76 struct e820_entry {
  77     uint64_t address;
  78     uint64_t length;
  79     uint32_t type;
  80 } __attribute((__packed__, __aligned__(4)));
  81
  82 struct e820_table {
  83     uint32_t count;
  84     struct e820_entry entry[E820_NR_ENTRIES];
  85 } __attribute((__packed__, __aligned__(4)));
  86
  87 static struct e820_table e820_table;
  88 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  89
  90 void isa_irq_handler(void *opaque, int n, int level)
  91 {
  92     IsaIrqState *isa = (IsaIrqState *)opaque;
  93
  94     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
  95     if (n < 16) {
  96         qemu_set_irq(isa->i8259[n], level);
  97     }
  98     if (isa->ioapic)
  99         qemu_set_irq(isa->ioapic[n], level);
 100 };
 101
 102 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 103 {
 104 }
 105
 106 /* MSDOS compatibility mode FPU exception support */
 107 static qemu_irq ferr_irq;
 108
 109 void pc_register_ferr_irq(qemu_irq irq)
 110 {
 111     ferr_irq = irq;
 112 }
 113
 114 /* XXX: add IGNNE support */
 115 void cpu_set_ferr(CPUX86State *s)
 116 {
 117     qemu_irq_raise(ferr_irq);
 118 }
 119
 120 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 121 {
 122     qemu_irq_lower(ferr_irq);
 123 }
 124
 125 /* TSC handling */
 126 uint64_t cpu_get_tsc(CPUX86State *env)
 127 {
 128     return cpu_get_ticks();
 129 }
 130
 131 /* SMM support */
 132
 133 static cpu_set_smm_t smm_set;
 134 static void *smm_arg;
 135
 136 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 137 {
 138     assert(smm_set == NULL);
 139     assert(smm_arg == NULL);
 140     smm_set = callback;
 141     smm_arg = arg;
 142 }
 143
 144 void cpu_smm_update(CPUState *env)
 145 {
 146     if (smm_set && smm_arg && env == first_cpu)
 147         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 148 }
 149
 150
 151 /* IRQ handling */
 152 int cpu_get_pic_interrupt(CPUState *env)
 153 {
 154     int intno;
 155
 156     intno = apic_get_interrupt(env->apic_state);
 157     if (intno >= 0) {
 158         /* set irq request if a PIC irq is still pending */
 159         /* XXX: improve that */
 160         pic_update_irq(isa_pic);
 161         return intno;
 162     }
 163     /* read the irq from the PIC */
 164     if (!apic_accept_pic_intr(env->apic_state)) {
 165         return -1;
 166     }
 167
 168     intno = pic_read_irq(isa_pic);
 169     return intno;
 170 }
 171
 172 static void pic_irq_request(void *opaque, int irq, int level)
 173 {
 174     CPUState *env = first_cpu;
 175
 176     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 177     if (env->apic_state) {
 178         while (env) {
 179             if (apic_accept_pic_intr(env->apic_state)) {
 180                 apic_deliver_pic_intr(env->apic_state, level);
 181             }
 182             env = env->next_cpu;
 183         }
 184     } else {
 185         if (level)
 186             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 187         else
 188             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 189     }
 190 }
 191
 192 /* PC cmos mappings */
 193
 194 #define REG_EQUIPMENT_BYTE          0x14
 195
 196 static int cmos_get_fd_drive_type(FDriveType fd0)
 197 {
 198     int val;
 199
 200     switch (fd0) {
 201     case FDRIVE_DRV_144:
 202         /* 1.44 Mb 3"5 drive */
 203         val = 4;
 204         break;
 205     case FDRIVE_DRV_288:
 206         /* 2.88 Mb 3"5 drive */
 207         val = 5;
 208         break;
 209     case FDRIVE_DRV_120:
 210         /* 1.2 Mb 5"5 drive */
 211         val = 2;
 212         break;
 213     case FDRIVE_DRV_NONE:
 214     default:
 215         val = 0;
 216         break;
 217     }
 218     return val;
 219 }
 220
 221 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 222                          ISADevice *s)
 223 {
 224     int cylinders, heads, sectors;
 225     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 226     rtc_set_memory(s, type_ofs, 47);
 227     rtc_set_memory(s, info_ofs, cylinders);
 228     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 229     rtc_set_memory(s, info_ofs + 2, heads);
 230     rtc_set_memory(s, info_ofs + 3, 0xff);
 231     rtc_set_memory(s, info_ofs + 4, 0xff);
 232     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 233     rtc_set_memory(s, info_ofs + 6, cylinders);
 234     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 235     rtc_set_memory(s, info_ofs + 8, sectors);
 236 }
 237
 238 /* convert boot_device letter to something recognizable by the bios */
 239 static int boot_device2nibble(char boot_device)
 240 {
 241     switch(boot_device) {
 242     case 'a':
 243     case 'b':
 244         return 0x01; /* floppy boot */
 245     case 'c':
 246         return 0x02; /* hard drive boot */
 247     case 'd':
 248         return 0x03; /* CD-ROM boot */
 249     case 'n':
 250         return 0x04; /* Network boot */
 251     }
 252     return 0;
 253 }
 254
 255 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 256 {
 257 #define PC_MAX_BOOT_DEVICES 3
 258     int nbds, bds[3] = { 0, };
 259     int i;
 260
 261     nbds = strlen(boot_device);
 262     if (nbds > PC_MAX_BOOT_DEVICES) {
 263         error_report("Too many boot devices for PC");
 264         return(1);
 265     }
 266     for (i = 0; i < nbds; i++) {
 267         bds[i] = boot_device2nibble(boot_device[i]);
 268         if (bds[i] == 0) {
 269             error_report("Invalid boot device for PC: '%c'",
 270                          boot_device[i]);
 271             return(1);
 272         }
 273     }
 274     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 275     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 276     return(0);
 277 }
 278
 279 static int pc_boot_set(void *opaque, const char *boot_device)
 280 {
 281     return set_boot_dev(opaque, boot_device, 0);
 282 }
 283
 284 typedef struct pc_cmos_init_late_arg {
 285     ISADevice *rtc_state;
 286     BusState *idebus0, *idebus1;
 287 } pc_cmos_init_late_arg;
 288
 289 static void pc_cmos_init_late(void *opaque)
 290 {
 291     pc_cmos_init_late_arg *arg = opaque;
 292     ISADevice *s = arg->rtc_state;
 293     int val;
 294     BlockDriverState *hd_table[4];
 295     int i;
 296
 297     ide_get_bs(hd_table, arg->idebus0);
 298     ide_get_bs(hd_table + 2, arg->idebus1);
 299
 300     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 301     if (hd_table[0])
 302         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 303     if (hd_table[1])
 304         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 305
 306     val = 0;
 307     for (i = 0; i < 4; i++) {
 308         if (hd_table[i]) {
 309             int cylinders, heads, sectors, translation;
 310             /* NOTE: bdrv_get_geometry_hint() returns the physical
 311                 geometry.  It is always such that: 1 <= sects <= 63, 1
 312                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 313                 geometry can be different if a translation is done. */
 314             translation = bdrv_get_translation_hint(hd_table[i]);
 315             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 316                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 317                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 318                     /* No translation. */
 319                     translation = 0;
 320                 } else {
 321                     /* LBA translation. */
 322                     translation = 1;
 323                 }
 324             } else {
 325                 translation--;
 326             }
 327             val |= translation << (i * 2);
 328         }
 329     }
 330     rtc_set_memory(s, 0x39, val);
 331
 332     qemu_unregister_reset(pc_cmos_init_late, opaque);
 333 }
 334
 335 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 336                   const char *boot_device,
 337                   BusState *idebus0, BusState *idebus1,
 338                   ISADevice *s)
 339 {
 340     int val, nb, nb_heads, max_track, last_sect, i;
 341     FDriveType fd_type[2];
 342     DriveInfo *fd[2];
 343     static pc_cmos_init_late_arg arg;
 344
 345     /* various important CMOS locations needed by PC/Bochs bios */
 346
 347     /* memory size */
 348     val = 640; /* base memory in K */
 349     rtc_set_memory(s, 0x15, val);
 350     rtc_set_memory(s, 0x16, val >> 8);
 351
 352     val = (ram_size / 1024) - 1024;
 353     if (val > 65535)
 354         val = 65535;
 355     rtc_set_memory(s, 0x17, val);
 356     rtc_set_memory(s, 0x18, val >> 8);
 357     rtc_set_memory(s, 0x30, val);
 358     rtc_set_memory(s, 0x31, val >> 8);
 359
 360     if (above_4g_mem_size) {
 361         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 362         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 363         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 364     }
 365
 366     if (ram_size > (16 * 1024 * 1024))
 367         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 368     else
 369         val = 0;
 370     if (val > 65535)
 371         val = 65535;
 372     rtc_set_memory(s, 0x34, val);
 373     rtc_set_memory(s, 0x35, val >> 8);
 374
 375     /* set the number of CPU */
 376     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 377
 378     /* set boot devices, and disable floppy signature check if requested */
 379     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 380         exit(1);
 381     }
 382
 383     /* floppy type */
 384     for (i = 0; i < 2; i++) {
 385         fd[i] = drive_get(IF_FLOPPY, 0, i);
 386         if (fd[i] && bdrv_is_inserted(fd[i]->bdrv)) {
 387             bdrv_get_floppy_geometry_hint(fd[i]->bdrv, &nb_heads, &max_track,
 388                                           &last_sect, FDRIVE_DRV_NONE,
 389                                           &fd_type[i]);
 390         } else {
 391             fd_type[i] = FDRIVE_DRV_NONE;
 392         }
 393     }
 394     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 395         cmos_get_fd_drive_type(fd_type[1]);
 396     rtc_set_memory(s, 0x10, val);
 397
 398     val = 0;
 399     nb = 0;
 400     if (fd_type[0] < FDRIVE_DRV_NONE) {
 401         nb++;
 402     }
 403     if (fd_type[1] < FDRIVE_DRV_NONE) {
 404         nb++;
 405     }
 406     switch (nb) {
 407     case 0:
 408         break;
 409     case 1:
 410         val |= 0x01; /* 1 drive, ready for boot */
 411         break;
 412     case 2:
 413         val |= 0x41; /* 2 drives, ready for boot */
 414         break;
 415     }
 416     val |= 0x02; /* FPU is there */
 417     val |= 0x04; /* PS/2 mouse installed */
 418     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 419
 420     /* hard drives */
 421     arg.rtc_state = s;
 422     arg.idebus0 = idebus0;
 423     arg.idebus1 = idebus1;
 424     qemu_register_reset(pc_cmos_init_late, &arg);
 425 }
 426
 427 /* port 92 stuff: could be split off */
 428 typedef struct Port92State {
 429     ISADevice dev;
 430     uint8_t outport;
 431     qemu_irq *a20_out;
 432 } Port92State;
 433
 434 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 435 {
 436     Port92State *s = opaque;
 437
 438     DPRINTF("port92: write 0x%02x\n", val);
 439     s->outport = val;
 440     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 441     if (val & 1) {
 442         qemu_system_reset_request();
 443     }
 444 }
 445
 446 static uint32_t port92_read(void *opaque, uint32_t addr)
 447 {
 448     Port92State *s = opaque;
 449     uint32_t ret;
 450
 451     ret = s->outport;
 452     DPRINTF("port92: read 0x%02x\n", ret);
 453     return ret;
 454 }
 455
 456 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 457 {
 458     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 459
 460     s->a20_out = a20_out;
 461 }
 462
 463 static const VMStateDescription vmstate_port92_isa = {
 464     .name = "port92",
 465     .version_id = 1,
 466     .minimum_version_id = 1,
 467     .minimum_version_id_old = 1,
 468     .fields      = (VMStateField []) {
 469         VMSTATE_UINT8(outport, Port92State),
 470         VMSTATE_END_OF_LIST()
 471     }
 472 };
 473
 474 static void port92_reset(DeviceState *d)
 475 {
 476     Port92State *s = container_of(d, Port92State, dev.qdev);
 477
 478     s->outport &= ~1;
 479 }
 480
 481 static int port92_initfn(ISADevice *dev)
 482 {
 483     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 484
 485     register_ioport_read(0x92, 1, 1, port92_read, s);
 486     register_ioport_write(0x92, 1, 1, port92_write, s);
 487     isa_init_ioport(dev, 0x92);
 488     s->outport = 0;
 489     return 0;
 490 }
 491
 492 static ISADeviceInfo port92_info = {
 493     .qdev.name     = "port92",
 494     .qdev.size     = sizeof(Port92State),
 495     .qdev.vmsd     = &vmstate_port92_isa,
 496     .qdev.no_user  = 1,
 497     .qdev.reset    = port92_reset,
 498     .init          = port92_initfn,
 499 };
 500
 501 static void port92_register(void)
 502 {
 503     isa_qdev_register(&port92_info);
 504 }
 505 device_init(port92_register)
 506
 507 static void handle_a20_line_change(void *opaque, int irq, int level)
 508 {
 509     CPUState *cpu = opaque;
 510
 511     /* XXX: send to all CPUs ? */
 512     /* XXX: add logic to handle multiple A20 line sources */
 513     cpu_x86_set_a20(cpu, level);
 514 }
 515
 516 /***********************************************************/
 517 /* Bochs BIOS debug ports */
 518
 519 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 520 {
 521     static const char shutdown_str[8] = "Shutdown";
 522     static int shutdown_index = 0;
 523
 524     switch(addr) {
 525         /* Bochs BIOS messages */
 526     case 0x400:
 527     case 0x401:
 528         /* used to be panic, now unused */
 529         break;
 530     case 0x402:
 531     case 0x403:
 532 #ifdef DEBUG_BIOS
 533         fprintf(stderr, "%c", val);
 534 #endif
 535         break;
 536     case 0x8900:
 537         /* same as Bochs power off */
 538         if (val == shutdown_str[shutdown_index]) {
 539             shutdown_index++;
 540             if (shutdown_index == 8) {
 541                 shutdown_index = 0;
 542                 qemu_system_shutdown_request();
 543             }
 544         } else {
 545             shutdown_index = 0;
 546         }
 547         break;
 548
 549         /* LGPL'ed VGA BIOS messages */
 550     case 0x501:
 551     case 0x502:
 552         exit((val << 1) | 1);
 553     case 0x500:
 554     case 0x503:
 555 #ifdef DEBUG_BIOS
 556         fprintf(stderr, "%c", val);
 557 #endif
 558         break;
 559     }
 560 }
 561
 562 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 563 {
 564     int index = le32_to_cpu(e820_table.count);
 565     struct e820_entry *entry;
 566
 567     if (index >= E820_NR_ENTRIES)
 568         return -EBUSY;
 569     entry = &e820_table.entry[index++];
 570
 571     entry->address = cpu_to_le64(address);
 572     entry->length = cpu_to_le64(length);
 573     entry->type = cpu_to_le32(type);
 574
 575     e820_table.count = cpu_to_le32(index);
 576     return index;
 577 }
 578
 579 static void *bochs_bios_init(void)
 580 {
 581     void *fw_cfg;
 582     uint8_t *smbios_table;
 583     size_t smbios_len;
 584     uint64_t *numa_fw_cfg;
 585     int i, j;
 586
 587     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 588     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 589     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 590     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 591     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 592
 593     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 594     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 595     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 596     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 597     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 598
 599     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 600
 601     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 602     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 603     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 604                      acpi_tables_len);
 605     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 606
 607     smbios_table = smbios_get_table(&smbios_len);
 608     if (smbios_table)
 609         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 610                          smbios_table, smbios_len);
 611     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 612                      sizeof(struct e820_table));
 613
 614     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 615                      sizeof(struct hpet_fw_config));
 616     /* allocate memory for the NUMA channel: one (64bit) word for the number
 617      * of nodes, one word for each VCPU->node and one word for each node to
 618      * hold the amount of memory.
 619      */
 620     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 621     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 622     for (i = 0; i < smp_cpus; i++) {
 623         for (j = 0; j < nb_numa_nodes; j++) {
 624             if (node_cpumask[j] & (1 << i)) {
 625                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 626                 break;
 627             }
 628         }
 629     }
 630     for (i = 0; i < nb_numa_nodes; i++) {
 631         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 632     }
 633     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 634                      (1 + smp_cpus + nb_numa_nodes) * 8);
 635
 636     return fw_cfg;
 637 }
 638
 639 static long get_file_size(FILE *f)
 640 {
 641     long where, size;
 642
 643     /* XXX: on Unix systems, using fstat() probably makes more sense */
 644
 645     where = ftell(f);
 646     fseek(f, 0, SEEK_END);
 647     size = ftell(f);
 648     fseek(f, where, SEEK_SET);
 649
 650     return size;
 651 }
 652
 653 static void load_linux(void *fw_cfg,
 654                        const char *kernel_filename,
 655                        const char *initrd_filename,
 656                        const char *kernel_cmdline,
 657                        target_phys_addr_t max_ram_size)
 658 {
 659     uint16_t protocol;
 660     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 661     uint32_t initrd_max;
 662     uint8_t header[8192], *setup, *kernel, *initrd_data;
 663     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 664     FILE *f;
 665     char *vmode;
 666
 667     /* Align to 16 bytes as a paranoia measure */
 668     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 669
 670     /* load the kernel header */
 671     f = fopen(kernel_filename, "rb");
 672     if (!f || !(kernel_size = get_file_size(f)) ||
 673         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 674         MIN(ARRAY_SIZE(header), kernel_size)) {
 675         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 676                 kernel_filename, strerror(errno));
 677         exit(1);
 678     }
 679
 680     /* kernel protocol version */
 681 #if 0
 682     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 683 #endif
 684     if (ldl_p(header+0x202) == 0x53726448)
 685         protocol = lduw_p(header+0x206);
 686     else {
 687         /* This looks like a multiboot kernel. If it is, let's stop
 688            treating it like a Linux kernel. */
 689         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 690                            kernel_cmdline, kernel_size, header))
 691             return;
 692         protocol = 0;
 693     }
 694
 695     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 696         /* Low kernel */
 697         real_addr    = 0x90000;
 698         cmdline_addr = 0x9a000 - cmdline_size;
 699         prot_addr    = 0x10000;
 700     } else if (protocol < 0x202) {
 701         /* High but ancient kernel */
 702         real_addr    = 0x90000;
 703         cmdline_addr = 0x9a000 - cmdline_size;
 704         prot_addr    = 0x100000;
 705     } else {
 706         /* High and recent kernel */
 707         real_addr    = 0x10000;
 708         cmdline_addr = 0x20000;
 709         prot_addr    = 0x100000;
 710     }
 711
 712 #if 0
 713     fprintf(stderr,
 714             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 715             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 716             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 717             real_addr,
 718             cmdline_addr,
 719             prot_addr);
 720 #endif
 721
 722     /* highest address for loading the initrd */
 723     if (protocol >= 0x203)
 724         initrd_max = ldl_p(header+0x22c);
 725     else
 726         initrd_max = 0x37ffffff;
 727
 728     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 729         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 730
 731     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 732     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 733     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 734                      (uint8_t*)strdup(kernel_cmdline),
 735                      strlen(kernel_cmdline)+1);
 736
 737     if (protocol >= 0x202) {
 738         stl_p(header+0x228, cmdline_addr);
 739     } else {
 740         stw_p(header+0x20, 0xA33F);
 741         stw_p(header+0x22, cmdline_addr-real_addr);
 742     }
 743
 744     /* handle vga= parameter */
 745     vmode = strstr(kernel_cmdline, "vga=");
 746     if (vmode) {
 747         unsigned int video_mode;
 748         /* skip "vga=" */
 749         vmode += 4;
 750         if (!strncmp(vmode, "normal", 6)) {
 751             video_mode = 0xffff;
 752         } else if (!strncmp(vmode, "ext", 3)) {
 753             video_mode = 0xfffe;
 754         } else if (!strncmp(vmode, "ask", 3)) {
 755             video_mode = 0xfffd;
 756         } else {
 757             video_mode = strtol(vmode, NULL, 0);
 758         }
 759         stw_p(header+0x1fa, video_mode);
 760     }
 761
 762     /* loader type */
 763     /* High nybble = B reserved for Qemu; low nybble is revision number.
 764        If this code is substantially changed, you may want to consider
 765        incrementing the revision. */
 766     if (protocol >= 0x200)
 767         header[0x210] = 0xB0;
 768
 769     /* heap */
 770     if (protocol >= 0x201) {
 771         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 772         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 773     }
 774
 775     /* load initrd */
 776     if (initrd_filename) {
 777         if (protocol < 0x200) {
 778             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 779             exit(1);
 780         }
 781
 782         initrd_size = get_image_size(initrd_filename);
 783         if (initrd_size < 0) {
 784             fprintf(stderr, "qemu: error reading initrd %s\n",
 785                     initrd_filename);
 786             exit(1);
 787         }
 788
 789         initrd_addr = (initrd_max-initrd_size) & ~4095;
 790
 791         initrd_data = qemu_malloc(initrd_size);
 792         load_image(initrd_filename, initrd_data);
 793
 794         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 795         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 796         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 797
 798         stl_p(header+0x218, initrd_addr);
 799         stl_p(header+0x21c, initrd_size);
 800     }
 801
 802     /* load kernel and setup */
 803     setup_size = header[0x1f1];
 804     if (setup_size == 0)
 805         setup_size = 4;
 806     setup_size = (setup_size+1)*512;
 807     kernel_size -= setup_size;
 808
 809     setup  = qemu_malloc(setup_size);
 810     kernel = qemu_malloc(kernel_size);
 811     fseek(f, 0, SEEK_SET);
 812     if (fread(setup, 1, setup_size, f) != setup_size) {
 813         fprintf(stderr, "fread() failed\n");
 814         exit(1);
 815     }
 816     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 817         fprintf(stderr, "fread() failed\n");
 818         exit(1);
 819     }
 820     fclose(f);
 821     memcpy(setup, header, MIN(sizeof(header), setup_size));
 822
 823     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 824     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 825     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 826
 827     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 828     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 829     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 830
 831     option_rom[nb_option_roms].name = "linuxboot.bin";
 832     option_rom[nb_option_roms].bootindex = 0;
 833     nb_option_roms++;
 834 }
 835
 836 #define NE2000_NB_MAX 6
 837
 838 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 839                                               0x280, 0x380 };
 840 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 841
 842 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 843 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 844
 845 void pc_init_ne2k_isa(NICInfo *nd)
 846 {
 847     static int nb_ne2k = 0;
 848
 849     if (nb_ne2k == NE2000_NB_MAX)
 850         return;
 851     isa_ne2000_init(ne2000_io[nb_ne2k],
 852                     ne2000_irq[nb_ne2k], nd);
 853     nb_ne2k++;
 854 }
 855
 856 int cpu_is_bsp(CPUState *env)
 857 {
 858     /* We hard-wire the BSP to the first CPU. */
 859     return env->cpu_index == 0;
 860 }
 861
 862 DeviceState *cpu_get_current_apic(void)
 863 {
 864     if (cpu_single_env) {
 865         return cpu_single_env->apic_state;
 866     } else {
 867         return NULL;
 868     }
 869 }
 870
 871 static DeviceState *apic_init(void *env, uint8_t apic_id)
 872 {
 873     DeviceState *dev;
 874     SysBusDevice *d;
 875     static int apic_mapped;
 876
 877     dev = qdev_create(NULL, "apic");
 878     qdev_prop_set_uint8(dev, "id", apic_id);
 879     qdev_prop_set_ptr(dev, "cpu_env", env);
 880     qdev_init_nofail(dev);
 881     d = sysbus_from_qdev(dev);
 882
 883     /* XXX: mapping more APICs at the same memory location */
 884     if (apic_mapped == 0) {
 885         /* NOTE: the APIC is directly connected to the CPU - it is not
 886            on the global memory bus. */
 887         /* XXX: what if the base changes? */
 888         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 889         apic_mapped = 1;
 890     }
 891
 892     msix_supported = 1;
 893
 894     return dev;
 895 }
 896
 897 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 898    BIOS will read it and start S3 resume at POST Entry */
 899 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 900 {
 901     ISADevice *s = opaque;
 902
 903     if (level) {
 904         rtc_set_memory(s, 0xF, 0xFE);
 905     }
 906 }
 907
 908 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 909 {
 910     CPUState *s = opaque;
 911
 912     if (level) {
 913         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 914     }
 915 }
 916
 917 static void pc_cpu_reset(void *opaque)
 918 {
 919     CPUState *env = opaque;
 920
 921     cpu_reset(env);
 922     env->halted = !cpu_is_bsp(env);
 923 }
 924
 925 static CPUState *pc_new_cpu(const char *cpu_model)
 926 {
 927     CPUState *env;
 928
 929     env = cpu_init(cpu_model);
 930     if (!env) {
 931         fprintf(stderr, "Unable to find x86 CPU definition\n");
 932         exit(1);
 933     }
 934     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 935         env->cpuid_apic_id = env->cpu_index;
 936         env->apic_state = apic_init(env, env->cpuid_apic_id);
 937     }
 938     qemu_register_reset(pc_cpu_reset, env);
 939     pc_cpu_reset(env);
 940     return env;
 941 }
 942
 943 void pc_cpus_init(const char *cpu_model)
 944 {
 945     int i;
 946
 947     /* init CPUs */
 948     if (cpu_model == NULL) {
 949 #ifdef TARGET_X86_64
 950         cpu_model = "qemu64";
 951 #else
 952         cpu_model = "qemu32";
 953 #endif
 954     }
 955
 956     for(i = 0; i < smp_cpus; i++) {
 957         pc_new_cpu(cpu_model);
 958     }
 959 }
 960
 961 void pc_memory_init(MemoryRegion *system_memory,
 962                     const char *kernel_filename,
 963                     const char *kernel_cmdline,
 964                     const char *initrd_filename,
 965                     ram_addr_t below_4g_mem_size,
 966                     ram_addr_t above_4g_mem_size)
 967 {
 968     char *filename;
 969     int ret, linux_boot, i;
 970     MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr;
 971     MemoryRegion *ram_below_4g, *ram_above_4g;
 972     int bios_size, isa_bios_size;
 973     void *fw_cfg;
 974
 975     linux_boot = (kernel_filename != NULL);
 976
 977     /* Allocate RAM.  We allocate it as a single memory region and use
 978      * aliases to address portions of it, mostly for backwards compatiblity
 979      * with older qemus that used qemu_ram_alloc().
 980      */
 981     ram = qemu_malloc(sizeof(*ram));
 982     memory_region_init_ram(ram, NULL, "pc.ram",
 983                            below_4g_mem_size + above_4g_mem_size);
 984     ram_below_4g = qemu_malloc(sizeof(*ram_below_4g));
 985     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 986                              0, below_4g_mem_size);
 987     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 988     if (above_4g_mem_size > 0) {
 989         ram_above_4g = qemu_malloc(sizeof(*ram_above_4g));
 990         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
 991                                  below_4g_mem_size, above_4g_mem_size);
 992         memory_region_add_subregion(system_memory, 0x100000000ULL,
 993                                     ram_above_4g);
 994     }
 995
 996     /* BIOS load */
 997     if (bios_name == NULL)
 998         bios_name = BIOS_FILENAME;
 999     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1000     if (filename) {
1001         bios_size = get_image_size(filename);
1002     } else {
1003         bios_size = -1;
1004     }
1005     if (bios_size <= 0 ||
1006         (bios_size % 65536) != 0) {
1007         goto bios_error;
1008     }
1009     bios = qemu_malloc(sizeof(*bios));
1010     memory_region_init_ram(bios, NULL, "pc.bios", bios_size);
1011     memory_region_set_readonly(bios, true);
1012     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1013     if (ret != 0) {
1014     bios_error:
1015         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1016         exit(1);
1017     }
1018     if (filename) {
1019         qemu_free(filename);
1020     }
1021     /* map the last 128KB of the BIOS in ISA space */
1022     isa_bios_size = bios_size;
1023     if (isa_bios_size > (128 * 1024))
1024         isa_bios_size = 128 * 1024;
1025     isa_bios = qemu_malloc(sizeof(*isa_bios));
1026     memory_region_init_alias(isa_bios, "isa-bios", bios,
1027                              bios_size - isa_bios_size, isa_bios_size);
1028     memory_region_add_subregion_overlap(system_memory,
1029                                         0x100000 - isa_bios_size,
1030                                         isa_bios,
1031                                         1);
1032     memory_region_set_readonly(isa_bios, true);
1033
1034     option_rom_mr = qemu_malloc(sizeof(*option_rom_mr));
1035     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1036     memory_region_add_subregion_overlap(system_memory,
1037                                         PC_ROM_MIN_VGA,
1038                                         option_rom_mr,
1039                                         1);
1040
1041     /* map all the bios at the top of memory */
1042     memory_region_add_subregion(system_memory,
1043                                 (uint32_t)(-bios_size),
1044                                 bios);
1045
1046     fw_cfg = bochs_bios_init();
1047     rom_set_fw(fw_cfg);
1048
1049     if (linux_boot) {
1050         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1051     }
1052
1053     for (i = 0; i < nb_option_roms; i++) {
1054         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1055     }
1056 }
1057
1058 qemu_irq *pc_allocate_cpu_irq(void)
1059 {
1060     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1061 }
1062
1063 void pc_vga_init(PCIBus *pci_bus)
1064 {
1065     if (cirrus_vga_enabled) {
1066         if (pci_bus) {
1067             pci_cirrus_vga_init(pci_bus);
1068         } else {
1069             isa_cirrus_vga_init();
1070         }
1071     } else if (vmsvga_enabled) {
1072         if (pci_bus) {
1073             if (!pci_vmsvga_init(pci_bus)) {
1074                 fprintf(stderr, "Warning: vmware_vga not available,"
1075                         " using standard VGA instead\n");
1076                 pci_vga_init(pci_bus);
1077             }
1078         } else {
1079             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1080         }
1081 #ifdef CONFIG_SPICE
1082     } else if (qxl_enabled) {
1083         if (pci_bus)
1084             pci_create_simple(pci_bus, -1, "qxl-vga");
1085         else
1086             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1087 #endif
1088     } else if (std_vga_enabled) {
1089         if (pci_bus) {
1090             pci_vga_init(pci_bus);
1091         } else {
1092             isa_vga_init();
1093         }
1094     }
1095
1096     /*
1097      * sga does not suppress normal vga output. So a machine can have both a
1098      * vga card and sga manually enabled. Output will be seen on both.
1099      * For nographic case, sga is enabled at all times
1100      */
1101     if (display_type == DT_NOGRAPHIC) {
1102         isa_create_simple("sga");
1103     }
1104 }
1105
1106 static void cpu_request_exit(void *opaque, int irq, int level)
1107 {
1108     CPUState *env = cpu_single_env;
1109
1110     if (env && level) {
1111         cpu_exit(env);
1112     }
1113 }
1114
1115 void pc_basic_device_init(qemu_irq *isa_irq,
1116                           ISADevice **rtc_state,
1117                           bool no_vmport)
1118 {
1119     int i;
1120     DriveInfo *fd[MAX_FD];
1121     qemu_irq rtc_irq = NULL;
1122     qemu_irq *a20_line;
1123     ISADevice *i8042, *port92, *vmmouse, *pit;
1124     qemu_irq *cpu_exit_irq;
1125
1126     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1127
1128     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1129
1130     if (!no_hpet) {
1131         DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1132
1133         if (hpet) {
1134             for (i = 0; i < 24; i++) {
1135                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
1136             }
1137             rtc_irq = qdev_get_gpio_in(hpet, 0);
1138         }
1139     }
1140     *rtc_state = rtc_init(2000, rtc_irq);
1141
1142     qemu_register_boot_set(pc_boot_set, *rtc_state);
1143
1144     pit = pit_init(0x40, 0);
1145     pcspk_init(pit);
1146
1147     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1148         if (serial_hds[i]) {
1149             serial_isa_init(i, serial_hds[i]);
1150         }
1151     }
1152
1153     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1154         if (parallel_hds[i]) {
1155             parallel_init(i, parallel_hds[i]);
1156         }
1157     }
1158
1159     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1160     i8042 = isa_create_simple("i8042");
1161     i8042_setup_a20_line(i8042, &a20_line[0]);
1162     if (!no_vmport) {
1163         vmport_init();
1164         vmmouse = isa_try_create("vmmouse");
1165     } else {
1166         vmmouse = NULL;
1167     }
1168     if (vmmouse) {
1169         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1170         qdev_init_nofail(&vmmouse->qdev);
1171     }
1172     port92 = isa_create_simple("port92");
1173     port92_init(port92, &a20_line[1]);
1174
1175     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1176     DMA_init(0, cpu_exit_irq);
1177
1178     for(i = 0; i < MAX_FD; i++) {
1179         fd[i] = drive_get(IF_FLOPPY, 0, i);
1180     }
1181     fdctrl_init_isa(fd);
1182 }
1183
1184 void pc_pci_device_init(PCIBus *pci_bus)
1185 {
1186     int max_bus;
1187     int bus;
1188
1189     max_bus = drive_get_max_bus(IF_SCSI);
1190     for (bus = 0; bus <= max_bus; bus++) {
1191         pci_create_simple(pci_bus, -1, "lsi53c895a");
1192     }
1193 }