hw/gpio/puv3_gpio.c

   1 /*
   2  * GPIO device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14
  15 #undef DEBUG_PUV3
  16 #include "hw/unicore32/puv3.h"
  17 #include "qemu/module.h"
  18 #include "qemu/log.h"
  19
  20 #define TYPE_PUV3_GPIO "puv3_gpio"
  21 #define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
  22
  23 typedef struct PUV3GPIOState {
  24     SysBusDevice parent_obj;
  25
  26     MemoryRegion iomem;
  27     qemu_irq irq[9];
  28
  29     uint32_t reg_GPLR;
  30     uint32_t reg_GPDR;
  31     uint32_t reg_GPIR;
  32 } PUV3GPIOState;
  33
  34 static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
  35         unsigned size)
  36 {
  37     PUV3GPIOState *s = opaque;
  38     uint32_t ret = 0;
  39
  40     switch (offset) {
  41     case 0x00:
  42         ret = s->reg_GPLR;
  43         break;
  44     case 0x04:
  45         ret = s->reg_GPDR;
  46         break;
  47     case 0x20:
  48         ret = s->reg_GPIR;
  49         break;
  50     default:
  51         qemu_log_mask(LOG_GUEST_ERROR,
  52                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  53                       __func__, offset);
  54     }
  55     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  56
  57     return ret;
  58 }
  59
  60 static void puv3_gpio_write(void *opaque, hwaddr offset,
  61         uint64_t value, unsigned size)
  62 {
  63     PUV3GPIOState *s = opaque;
  64
  65     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  66     switch (offset) {
  67     case 0x04:
  68         s->reg_GPDR = value;
  69         break;
  70     case 0x08:
  71         if (s->reg_GPDR & value) {
  72             s->reg_GPLR |= value;
  73         } else {
  74             qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
  75                           __func__);
  76         }
  77         break;
  78     case 0x0c:
  79         if (s->reg_GPDR & value) {
  80             s->reg_GPLR &= ~value;
  81         } else {
  82             qemu_log_mask(LOG_GUEST_ERROR, "%s: Write gpio input port\n",
  83                           __func__);
  84         }
  85         break;
  86     case 0x10: /* GRER */
  87     case 0x14: /* GFER */
  88     case 0x18: /* GEDR */
  89         break;
  90     case 0x20: /* GPIR */
  91         s->reg_GPIR = value;
  92         break;
  93     default:
  94         qemu_log_mask(LOG_GUEST_ERROR,
  95                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  96                       __func__, offset);
  97     }
  98 }
  99
 100 static const MemoryRegionOps puv3_gpio_ops = {
 101     .read = puv3_gpio_read,
 102     .write = puv3_gpio_write,
 103     .impl = {
 104         .min_access_size = 4,
 105         .max_access_size = 4,
 106     },
 107     .endianness = DEVICE_NATIVE_ENDIAN,
 108 };
 109
 110 static void puv3_gpio_realize(DeviceState *dev, Error **errp)
 111 {
 112     PUV3GPIOState *s = PUV3_GPIO(dev);
 113     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 114
 115     s->reg_GPLR = 0;
 116     s->reg_GPDR = 0;
 117
 118     /* FIXME: these irqs not handled yet */
 119     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]);
 120     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]);
 121     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]);
 122     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]);
 123     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]);
 124     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]);
 125     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]);
 126     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]);
 127     sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]);
 128
 129     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
 130             PUV3_REGS_OFFSET);
 131     sysbus_init_mmio(sbd, &s->iomem);
 132 }
 133
 134 static void puv3_gpio_class_init(ObjectClass *klass, void *data)
 135 {
 136     DeviceClass *dc = DEVICE_CLASS(klass);
 137
 138     dc->realize = puv3_gpio_realize;
 139 }
 140
 141 static const TypeInfo puv3_gpio_info = {
 142     .name = TYPE_PUV3_GPIO,
 143     .parent = TYPE_SYS_BUS_DEVICE,
 144     .instance_size = sizeof(PUV3GPIOState),
 145     .class_init = puv3_gpio_class_init,
 146 };
 147
 148 static void puv3_gpio_register_type(void)
 149 {
 150     type_register_static(&puv3_gpio_info);
 151 }
 152
 153 type_init(puv3_gpio_register_type)