hw/intc/arm_gicv2m.c

   1 /*
   2  *  GICv2m extension for MSI/MSI-x support with a GICv2-based system
   3  *
   4  * Copyright (C) 2015 Linaro, All rights reserved.
   5  *
   6  * Author: Christoffer Dall <christoffer.dall@linaro.org>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /* This file implements an emulated GICv2m widget as described in the ARM
  23  * Server Base System Architecture (SBSA) specification Version 2.2
  24  * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined
  25  * identification registers and with a single non-secure MSI register frame.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/irq.h"
  32 #include "hw/pci/msi.h"
  33 #include "hw/qdev-properties.h"
  34 #include "sysemu/kvm.h"
  35 #include "qemu/log.h"
  36 #include "qemu/module.h"
  37
  38 #define TYPE_ARM_GICV2M "arm-gicv2m"
  39 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M)
  40
  41 #define GICV2M_NUM_SPI_MAX 128
  42
  43 #define V2M_MSI_TYPER           0x008
  44 #define V2M_MSI_SETSPI_NS       0x040
  45 #define V2M_MSI_IIDR            0xFCC
  46 #define V2M_IIDR0               0xFD0
  47 #define V2M_IIDR11              0xFFC
  48
  49 #define PRODUCT_ID_QEMU         0x51 /* ASCII code Q */
  50
  51 typedef struct ARMGICv2mState {
  52     SysBusDevice parent_obj;
  53
  54     MemoryRegion iomem;
  55     qemu_irq spi[GICV2M_NUM_SPI_MAX];
  56
  57     uint32_t base_spi;
  58     uint32_t num_spi;
  59 } ARMGICv2mState;
  60
  61 static void gicv2m_set_irq(void *opaque, int irq)
  62 {
  63     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  64
  65     qemu_irq_pulse(s->spi[irq]);
  66 }
  67
  68 static uint64_t gicv2m_read(void *opaque, hwaddr offset,
  69                             unsigned size)
  70 {
  71     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  72     uint32_t val;
  73
  74     if (size != 4) {
  75         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size);
  76         return 0;
  77     }
  78
  79     switch (offset) {
  80     case V2M_MSI_TYPER:
  81         val = (s->base_spi + 32) << 16;
  82         val |= s->num_spi;
  83         return val;
  84     case V2M_MSI_IIDR:
  85         /* We don't have any valid implementor so we leave that field as zero
  86          * and we return 0 in the arch revision as per the spec.
  87          */
  88         return (PRODUCT_ID_QEMU << 20);
  89     case V2M_IIDR0 ... V2M_IIDR11:
  90         /* We do not implement any optional identification registers and the
  91          * mandatory MSI_PIDR2 register reads as 0x0, so we capture all
  92          * implementation defined registers here.
  93          */
  94         return 0;
  95     default:
  96         qemu_log_mask(LOG_GUEST_ERROR,
  97                       "gicv2m_read: Bad offset %x\n", (int)offset);
  98         return 0;
  99     }
 100 }
 101
 102 static void gicv2m_write(void *opaque, hwaddr offset,
 103                         uint64_t value, unsigned size)
 104 {
 105     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
 106
 107     if (size != 2 && size != 4) {
 108         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size);
 109         return;
 110     }
 111
 112     switch (offset) {
 113     case V2M_MSI_SETSPI_NS: {
 114         int spi;
 115
 116         spi = (value & 0x3ff) - (s->base_spi + 32);
 117         if (spi >= 0 && spi < s->num_spi) {
 118             gicv2m_set_irq(s, spi);
 119         }
 120         return;
 121     }
 122     default:
 123         qemu_log_mask(LOG_GUEST_ERROR,
 124                       "gicv2m_write: Bad offset %x\n", (int)offset);
 125     }
 126 }
 127
 128 static const MemoryRegionOps gicv2m_ops = {
 129     .read = gicv2m_read,
 130     .write = gicv2m_write,
 131     .endianness = DEVICE_LITTLE_ENDIAN,
 132 };
 133
 134 static void gicv2m_realize(DeviceState *dev, Error **errp)
 135 {
 136     ARMGICv2mState *s = ARM_GICV2M(dev);
 137     int i;
 138
 139     if (s->num_spi > GICV2M_NUM_SPI_MAX) {
 140         error_setg(errp,
 141                    "requested %u SPIs exceeds GICv2m frame maximum %d",
 142                    s->num_spi, GICV2M_NUM_SPI_MAX);
 143         return;
 144     }
 145
 146     if (s->base_spi + 32 > 1020 - s->num_spi) {
 147         error_setg(errp,
 148                    "requested base SPI %u+%u exceeds max. number 1020",
 149                    s->base_spi + 32, s->num_spi);
 150         return;
 151     }
 152
 153     for (i = 0; i < s->num_spi; i++) {
 154         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]);
 155     }
 156
 157     msi_nonbroken = true;
 158     kvm_gsi_direct_mapping = true;
 159     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 160 }
 161
 162 static void gicv2m_init(Object *obj)
 163 {
 164     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 165     ARMGICv2mState *s = ARM_GICV2M(obj);
 166
 167     memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s,
 168                           "gicv2m", 0x1000);
 169     sysbus_init_mmio(sbd, &s->iomem);
 170 }
 171
 172 static Property gicv2m_properties[] = {
 173     DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),
 174     DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64),
 175     DEFINE_PROP_END_OF_LIST(),
 176 };
 177
 178 static void gicv2m_class_init(ObjectClass *klass, void *data)
 179 {
 180     DeviceClass *dc = DEVICE_CLASS(klass);
 181
 182     device_class_set_props(dc, gicv2m_properties);
 183     dc->realize = gicv2m_realize;
 184 }
 185
 186 static const TypeInfo gicv2m_info = {
 187     .name          = TYPE_ARM_GICV2M,
 188     .parent        = TYPE_SYS_BUS_DEVICE,
 189     .instance_size = sizeof(ARMGICv2mState),
 190     .instance_init = gicv2m_init,
 191     .class_init    = gicv2m_class_init,
 192 };
 193
 194 static void gicv2m_register_types(void)
 195 {
 196     type_register_static(&gicv2m_info);
 197 }
 198
 199 type_init(gicv2m_register_types)