hw/intc/xilinx_intc.c

   1 /*
   2  * QEMU Xilinx OPB Interrupt Controller.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "qemu/module.h"
  28 #include "hw/irq.h"
  29 #include "hw/qdev-properties.h"
  30
  31 #define D(x)
  32
  33 #define R_ISR       0
  34 #define R_IPR       1
  35 #define R_IER       2
  36 #define R_IAR       3
  37 #define R_SIE       4
  38 #define R_CIE       5
  39 #define R_IVR       6
  40 #define R_MER       7
  41 #define R_MAX       8
  42
  43 #define TYPE_XILINX_INTC "xlnx.xps-intc"
  44 #define XILINX_INTC(obj) OBJECT_CHECK(struct xlx_pic, (obj), TYPE_XILINX_INTC)
  45
  46 struct xlx_pic
  47 {
  48     SysBusDevice parent_obj;
  49
  50     MemoryRegion mmio;
  51     qemu_irq parent_irq;
  52
  53     /* Configuration reg chosen at synthesis-time. QEMU populates
  54        the bits at board-setup.  */
  55     uint32_t c_kind_of_intr;
  56
  57     /* Runtime control registers.  */
  58     uint32_t regs[R_MAX];
  59     /* state of the interrupt input pins */
  60     uint32_t irq_pin_state;
  61 };
  62
  63 static void update_irq(struct xlx_pic *p)
  64 {
  65     uint32_t i;
  66
  67     /* level triggered interrupt */
  68     if (p->regs[R_MER] & 2) {
  69         p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;
  70     }
  71
  72     /* Update the pending register.  */
  73     p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
  74
  75     /* Update the vector register.  */
  76     for (i = 0; i < 32; i++) {
  77         if (p->regs[R_IPR] & (1U << i)) {
  78             break;
  79         }
  80     }
  81     if (i == 32)
  82         i = ~0;
  83
  84     p->regs[R_IVR] = i;
  85     qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
  86 }
  87
  88 static uint64_t
  89 pic_read(void *opaque, hwaddr addr, unsigned int size)
  90 {
  91     struct xlx_pic *p = opaque;
  92     uint32_t r = 0;
  93
  94     addr >>= 2;
  95     switch (addr)
  96     {
  97         default:
  98             if (addr < ARRAY_SIZE(p->regs))
  99                 r = p->regs[addr];
 100             break;
 101
 102     }
 103     D(printf("%s %x=%x\n", __func__, addr * 4, r));
 104     return r;
 105 }
 106
 107 static void
 108 pic_write(void *opaque, hwaddr addr,
 109           uint64_t val64, unsigned int size)
 110 {
 111     struct xlx_pic *p = opaque;
 112     uint32_t value = val64;
 113
 114     addr >>= 2;
 115     D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
 116     switch (addr)
 117     {
 118         case R_IAR:
 119             p->regs[R_ISR] &= ~value; /* ACK.  */
 120             break;
 121         case R_SIE:
 122             p->regs[R_IER] |= value;  /* Atomic set ie.  */
 123             break;
 124         case R_CIE:
 125             p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
 126             break;
 127         case R_MER:
 128             p->regs[R_MER] = value & 0x3;
 129             break;
 130         case R_ISR:
 131             if ((p->regs[R_MER] & 2)) {
 132                 break;
 133             }
 134             /* fallthrough */
 135         default:
 136             if (addr < ARRAY_SIZE(p->regs))
 137                 p->regs[addr] = value;
 138             break;
 139     }
 140     update_irq(p);
 141 }
 142
 143 static const MemoryRegionOps pic_ops = {
 144     .read = pic_read,
 145     .write = pic_write,
 146     .endianness = DEVICE_NATIVE_ENDIAN,
 147     .valid = {
 148         .min_access_size = 4,
 149         .max_access_size = 4
 150     }
 151 };
 152
 153 static void irq_handler(void *opaque, int irq, int level)
 154 {
 155     struct xlx_pic *p = opaque;
 156
 157     /* edge triggered interrupt */
 158     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
 159         p->regs[R_ISR] |= (level << irq);
 160     }
 161
 162     p->irq_pin_state &= ~(1 << irq);
 163     p->irq_pin_state |= level << irq;
 164     update_irq(p);
 165 }
 166
 167 static void xilinx_intc_init(Object *obj)
 168 {
 169     struct xlx_pic *p = XILINX_INTC(obj);
 170
 171     qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
 172     sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
 173
 174     memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc",
 175                           R_MAX * 4);
 176     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
 177 }
 178
 179 static Property xilinx_intc_properties[] = {
 180     DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
 181     DEFINE_PROP_END_OF_LIST(),
 182 };
 183
 184 static void xilinx_intc_class_init(ObjectClass *klass, void *data)
 185 {
 186     DeviceClass *dc = DEVICE_CLASS(klass);
 187
 188     device_class_set_props(dc, xilinx_intc_properties);
 189 }
 190
 191 static const TypeInfo xilinx_intc_info = {
 192     .name          = TYPE_XILINX_INTC,
 193     .parent        = TYPE_SYS_BUS_DEVICE,
 194     .instance_size = sizeof(struct xlx_pic),
 195     .instance_init = xilinx_intc_init,
 196     .class_init    = xilinx_intc_class_init,
 197 };
 198
 199 static void xilinx_intc_register_types(void)
 200 {
 201     type_register_static(&xilinx_intc_info);
 202 }
 203
 204 type_init(xilinx_intc_register_types)