hw/misc/mips_cpc.c

   1 /*
   2  * Cluster Power Controller emulation
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "hw/sysbus.h"
  26 #include "migration/vmstate.h"
  27
  28 #include "hw/misc/mips_cpc.h"
  29 #include "hw/qdev-properties.h"
  30
  31 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
  32 {
  33     return (1ULL << cpc->num_vp) - 1;
  34 }
  35
  36 static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
  37 {
  38     MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;
  39
  40     cpu_reset(cs);
  41     cpc->vp_running |= 1ULL << cs->cpu_index;
  42 }
  43
  44 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
  45 {
  46     CPUState *cs = first_cpu;
  47
  48     CPU_FOREACH(cs) {
  49         uint64_t i = 1ULL << cs->cpu_index;
  50         if (i & vp_run & ~cpc->vp_running) {
  51             /*
  52              * To avoid racing with a CPU we are just kicking off.
  53              * We do the final bit of preparation for the work in
  54              * the target CPUs context.
  55              */
  56             async_safe_run_on_cpu(cs, mips_cpu_reset_async_work,
  57                                   RUN_ON_CPU_HOST_PTR(cpc));
  58         }
  59     }
  60 }
  61
  62 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
  63 {
  64     CPUState *cs = first_cpu;
  65
  66     CPU_FOREACH(cs) {
  67         uint64_t i = 1ULL << cs->cpu_index;
  68         if (i & vp_stop & cpc->vp_running) {
  69             cpu_interrupt(cs, CPU_INTERRUPT_HALT);
  70             cpc->vp_running &= ~i;
  71         }
  72     }
  73 }
  74
  75 static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
  76                       unsigned size)
  77 {
  78     MIPSCPCState *s = opaque;
  79
  80     switch (offset) {
  81     case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
  82     case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
  83         cpc_run_vp(s, data & cpc_vp_run_mask(s));
  84         break;
  85     case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
  86     case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
  87         cpc_stop_vp(s, data & cpc_vp_run_mask(s));
  88         break;
  89     default:
  90         qemu_log_mask(LOG_UNIMP,
  91                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
  92         break;
  93     }
  94
  95     return;
  96 }
  97
  98 static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
  99 {
 100     MIPSCPCState *s = opaque;
 101
 102     switch (offset) {
 103     case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
 104     case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
 105         return s->vp_running;
 106     default:
 107         qemu_log_mask(LOG_UNIMP,
 108                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
 109         return 0;
 110     }
 111 }
 112
 113 static const MemoryRegionOps cpc_ops = {
 114     .read = cpc_read,
 115     .write = cpc_write,
 116     .endianness = DEVICE_NATIVE_ENDIAN,
 117     .impl = {
 118         .max_access_size = 8,
 119     },
 120 };
 121
 122 static void mips_cpc_init(Object *obj)
 123 {
 124     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 125     MIPSCPCState *s = MIPS_CPC(obj);
 126
 127     memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
 128                           CPC_ADDRSPACE_SZ);
 129     sysbus_init_mmio(sbd, &s->mr);
 130 }
 131
 132 static void mips_cpc_realize(DeviceState *dev, Error **errp)
 133 {
 134     MIPSCPCState *s = MIPS_CPC(dev);
 135
 136     if (s->vp_start_running > cpc_vp_run_mask(s)) {
 137         error_setg(errp,
 138                    "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
 139                    s->vp_running, s->num_vp);
 140         return;
 141     }
 142 }
 143
 144 static void mips_cpc_reset(DeviceState *dev)
 145 {
 146     MIPSCPCState *s = MIPS_CPC(dev);
 147
 148     /* Reflect the fact that all VPs are halted on reset */
 149     s->vp_running = 0;
 150
 151     /* Put selected VPs into run state */
 152     cpc_run_vp(s, s->vp_start_running);
 153 }
 154
 155 static const VMStateDescription vmstate_mips_cpc = {
 156     .name = "mips-cpc",
 157     .version_id = 0,
 158     .minimum_version_id = 0,
 159     .fields = (VMStateField[]) {
 160         VMSTATE_UINT64(vp_running, MIPSCPCState),
 161         VMSTATE_END_OF_LIST()
 162     },
 163 };
 164
 165 static Property mips_cpc_properties[] = {
 166     DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
 167     DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
 168     DEFINE_PROP_END_OF_LIST(),
 169 };
 170
 171 static void mips_cpc_class_init(ObjectClass *klass, void *data)
 172 {
 173     DeviceClass *dc = DEVICE_CLASS(klass);
 174
 175     dc->realize = mips_cpc_realize;
 176     dc->reset = mips_cpc_reset;
 177     dc->vmsd = &vmstate_mips_cpc;
 178     device_class_set_props(dc, mips_cpc_properties);
 179 }
 180
 181 static const TypeInfo mips_cpc_info = {
 182     .name          = TYPE_MIPS_CPC,
 183     .parent        = TYPE_SYS_BUS_DEVICE,
 184     .instance_size = sizeof(MIPSCPCState),
 185     .instance_init = mips_cpc_init,
 186     .class_init    = mips_cpc_class_init,
 187 };
 188
 189 static void mips_cpc_register_types(void)
 190 {
 191     type_register_static(&mips_cpc_info);
 192 }
 193
 194 type_init(mips_cpc_register_types)