qapi/error: Check format string argument in error_*prepend()
[qemu/armbru.git] / hw / ppc / ppce500_spin.c
blob66c1065db245a748148b368e7b43bf45b9f2a5e4
1 /*
2 * QEMU PowerPC e500v2 ePAPR spinning code
4 * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Alexander Graf, <agraf@suse.de>
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * This code is not really a device, but models an interface that usually
22 * firmware takes care of. It's used when QEMU plays the role of firmware.
24 * Specification:
26 * https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf
30 #include "qemu/osdep.h"
31 #include "qemu/module.h"
32 #include "qemu/units.h"
33 #include "hw/hw.h"
34 #include "hw/sysbus.h"
35 #include "sysemu/hw_accel.h"
36 #include "e500.h"
38 #define MAX_CPUS 32
40 typedef struct spin_info {
41 uint64_t addr;
42 uint64_t r3;
43 uint32_t resv;
44 uint32_t pir;
45 uint64_t reserved;
46 } QEMU_PACKED SpinInfo;
48 #define TYPE_E500_SPIN "e500-spin"
49 #define E500_SPIN(obj) OBJECT_CHECK(SpinState, (obj), TYPE_E500_SPIN)
51 typedef struct SpinState {
52 SysBusDevice parent_obj;
54 MemoryRegion iomem;
55 SpinInfo spin[MAX_CPUS];
56 } SpinState;
58 static void spin_reset(DeviceState *dev)
60 SpinState *s = E500_SPIN(dev);
61 int i;
63 for (i = 0; i < MAX_CPUS; i++) {
64 SpinInfo *info = &s->spin[i];
66 stl_p(&info->pir, i);
67 stq_p(&info->r3, i);
68 stq_p(&info->addr, 1);
72 static void mmubooke_create_initial_mapping(CPUPPCState *env,
73 target_ulong va,
74 hwaddr pa,
75 hwaddr len)
77 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
78 hwaddr size;
80 size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
81 tlb->mas1 = MAS1_VALID | size;
82 tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
83 tlb->mas7_3 = pa & TARGET_PAGE_MASK;
84 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
85 env->tlb_dirty = true;
88 static void spin_kick(CPUState *cs, run_on_cpu_data data)
90 PowerPCCPU *cpu = POWERPC_CPU(cs);
91 CPUPPCState *env = &cpu->env;
92 SpinInfo *curspin = data.host_ptr;
93 hwaddr map_size = 64 * MiB;
94 hwaddr map_start;
96 cpu_synchronize_state(cs);
97 stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]);
98 env->nip = ldq_p(&curspin->addr) & (map_size - 1);
99 env->gpr[3] = ldq_p(&curspin->r3);
100 env->gpr[4] = 0;
101 env->gpr[5] = 0;
102 env->gpr[6] = 0;
103 env->gpr[7] = map_size;
104 env->gpr[8] = 0;
105 env->gpr[9] = 0;
107 map_start = ldq_p(&curspin->addr) & ~(map_size - 1);
108 mmubooke_create_initial_mapping(env, 0, map_start, map_size);
110 cs->halted = 0;
111 cs->exception_index = -1;
112 cs->stopped = false;
113 qemu_cpu_kick(cs);
116 static void spin_write(void *opaque, hwaddr addr, uint64_t value,
117 unsigned len)
119 SpinState *s = opaque;
120 int env_idx = addr / sizeof(SpinInfo);
121 CPUState *cpu;
122 SpinInfo *curspin = &s->spin[env_idx];
123 uint8_t *curspin_p = (uint8_t*)curspin;
125 cpu = qemu_get_cpu(env_idx);
126 if (cpu == NULL) {
127 /* Unknown CPU */
128 return;
131 if (cpu->cpu_index == 0) {
132 /* primary CPU doesn't spin */
133 return;
136 curspin_p = &curspin_p[addr % sizeof(SpinInfo)];
137 switch (len) {
138 case 1:
139 stb_p(curspin_p, value);
140 break;
141 case 2:
142 stw_p(curspin_p, value);
143 break;
144 case 4:
145 stl_p(curspin_p, value);
146 break;
149 if (!(ldq_p(&curspin->addr) & 1)) {
150 /* run CPU */
151 run_on_cpu(cpu, spin_kick, RUN_ON_CPU_HOST_PTR(curspin));
155 static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len)
157 SpinState *s = opaque;
158 uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
160 switch (len) {
161 case 1:
162 return ldub_p(spin_p);
163 case 2:
164 return lduw_p(spin_p);
165 case 4:
166 return ldl_p(spin_p);
167 default:
168 hw_error("ppce500: unexpected %s with len = %u", __func__, len);
172 static const MemoryRegionOps spin_rw_ops = {
173 .read = spin_read,
174 .write = spin_write,
175 .endianness = DEVICE_BIG_ENDIAN,
178 static void ppce500_spin_initfn(Object *obj)
180 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
181 SpinState *s = E500_SPIN(dev);
183 memory_region_init_io(&s->iomem, obj, &spin_rw_ops, s,
184 "e500 spin pv device", sizeof(SpinInfo) * MAX_CPUS);
185 sysbus_init_mmio(dev, &s->iomem);
188 static void ppce500_spin_class_init(ObjectClass *klass, void *data)
190 DeviceClass *dc = DEVICE_CLASS(klass);
192 dc->reset = spin_reset;
195 static const TypeInfo ppce500_spin_info = {
196 .name = TYPE_E500_SPIN,
197 .parent = TYPE_SYS_BUS_DEVICE,
198 .instance_size = sizeof(SpinState),
199 .instance_init = ppce500_spin_initfn,
200 .class_init = ppce500_spin_class_init,
203 static void ppce500_spin_register_types(void)
205 type_register_static(&ppce500_spin_info);
208 type_init(ppce500_spin_register_types)