hw/timer/puv3_ost.c

   1 /*
   2  * OSTimer device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/irq.h"
  15 #include "hw/ptimer.h"
  16 #include "qemu/module.h"
  17 #include "qemu/log.h"
  18
  19 #undef DEBUG_PUV3
  20 #include "hw/unicore32/puv3.h"
  21
  22 #define TYPE_PUV3_OST "puv3_ost"
  23 #define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
  24
  25 /* puv3 ostimer implementation. */
  26 typedef struct PUV3OSTState {
  27     SysBusDevice parent_obj;
  28
  29     MemoryRegion iomem;
  30     qemu_irq irq;
  31     ptimer_state *ptimer;
  32
  33     uint32_t reg_OSMR0;
  34     uint32_t reg_OSCR;
  35     uint32_t reg_OSSR;
  36     uint32_t reg_OIER;
  37 } PUV3OSTState;
  38
  39 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  40         unsigned size)
  41 {
  42     PUV3OSTState *s = opaque;
  43     uint32_t ret = 0;
  44
  45     switch (offset) {
  46     case 0x10: /* Counter Register */
  47         ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  48         break;
  49     case 0x14: /* Status Register */
  50         ret = s->reg_OSSR;
  51         break;
  52     case 0x1c: /* Interrupt Enable Register */
  53         ret = s->reg_OIER;
  54         break;
  55     default:
  56         qemu_log_mask(LOG_GUEST_ERROR,
  57                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  58                       __func__, offset);
  59     }
  60     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  61     return ret;
  62 }
  63
  64 static void puv3_ost_write(void *opaque, hwaddr offset,
  65         uint64_t value, unsigned size)
  66 {
  67     PUV3OSTState *s = opaque;
  68
  69     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  70     switch (offset) {
  71     case 0x00: /* Match Register 0 */
  72         ptimer_transaction_begin(s->ptimer);
  73         s->reg_OSMR0 = value;
  74         if (s->reg_OSMR0 > s->reg_OSCR) {
  75             ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  76         } else {
  77             ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  78                     (0xffffffff - s->reg_OSCR));
  79         }
  80         ptimer_run(s->ptimer, 2);
  81         ptimer_transaction_commit(s->ptimer);
  82         break;
  83     case 0x14: /* Status Register */
  84         assert(value == 0);
  85         if (s->reg_OSSR) {
  86             s->reg_OSSR = value;
  87             qemu_irq_lower(s->irq);
  88         }
  89         break;
  90     case 0x1c: /* Interrupt Enable Register */
  91         s->reg_OIER = value;
  92         break;
  93     default:
  94         qemu_log_mask(LOG_GUEST_ERROR,
  95                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  96                       __func__, offset);
  97     }
  98 }
  99
 100 static const MemoryRegionOps puv3_ost_ops = {
 101     .read = puv3_ost_read,
 102     .write = puv3_ost_write,
 103     .impl = {
 104         .min_access_size = 4,
 105         .max_access_size = 4,
 106     },
 107     .endianness = DEVICE_NATIVE_ENDIAN,
 108 };
 109
 110 static void puv3_ost_tick(void *opaque)
 111 {
 112     PUV3OSTState *s = opaque;
 113
 114     DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 115             s->reg_OSCR, s->reg_OSMR0);
 116
 117     s->reg_OSCR = s->reg_OSMR0;
 118     if (s->reg_OIER) {
 119         s->reg_OSSR = 1;
 120         qemu_irq_raise(s->irq);
 121     }
 122 }
 123
 124 static void puv3_ost_realize(DeviceState *dev, Error **errp)
 125 {
 126     PUV3OSTState *s = PUV3_OST(dev);
 127     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 128
 129     s->reg_OIER = 0;
 130     s->reg_OSSR = 0;
 131     s->reg_OSMR0 = 0;
 132     s->reg_OSCR = 0;
 133
 134     sysbus_init_irq(sbd, &s->irq);
 135
 136     s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT);
 137     ptimer_transaction_begin(s->ptimer);
 138     ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 139     ptimer_transaction_commit(s->ptimer);
 140
 141     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
 142             PUV3_REGS_OFFSET);
 143     sysbus_init_mmio(sbd, &s->iomem);
 144 }
 145
 146 static void puv3_ost_class_init(ObjectClass *klass, void *data)
 147 {
 148     DeviceClass *dc = DEVICE_CLASS(klass);
 149
 150     dc->realize = puv3_ost_realize;
 151 }
 152
 153 static const TypeInfo puv3_ost_info = {
 154     .name = TYPE_PUV3_OST,
 155     .parent = TYPE_SYS_BUS_DEVICE,
 156     .instance_size = sizeof(PUV3OSTState),
 157     .class_init = puv3_ost_class_init,
 158 };
 159
 160 static void puv3_ost_register_type(void)
 161 {
 162     type_register_static(&puv3_ost_info);
 163 }
 164
 165 type_init(puv3_ost_register_type)