hw/timer/pxa2xx_timer.c

   1 /*
   2  * Intel XScale PXA255/270 OS Timers.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/irq.h"
  12 #include "hw/qdev-properties.h"
  13 #include "qemu/timer.h"
  14 #include "sysemu/runstate.h"
  15 #include "hw/arm/pxa.h"
  16 #include "hw/sysbus.h"
  17 #include "migration/vmstate.h"
  18 #include "qemu/log.h"
  19 #include "qemu/module.h"
  20
  21 #define OSMR0   0x00
  22 #define OSMR1   0x04
  23 #define OSMR2   0x08
  24 #define OSMR3   0x0c
  25 #define OSMR4   0x80
  26 #define OSMR5   0x84
  27 #define OSMR6   0x88
  28 #define OSMR7   0x8c
  29 #define OSMR8   0x90
  30 #define OSMR9   0x94
  31 #define OSMR10  0x98
  32 #define OSMR11  0x9c
  33 #define OSCR    0x10    /* OS Timer Count */
  34 #define OSCR4   0x40
  35 #define OSCR5   0x44
  36 #define OSCR6   0x48
  37 #define OSCR7   0x4c
  38 #define OSCR8   0x50
  39 #define OSCR9   0x54
  40 #define OSCR10  0x58
  41 #define OSCR11  0x5c
  42 #define OSSR    0x14    /* Timer status register */
  43 #define OWER    0x18
  44 #define OIER    0x1c    /* Interrupt enable register  3-0 to E3-E0 */
  45 #define OMCR4   0xc0    /* OS Match Control registers */
  46 #define OMCR5   0xc4
  47 #define OMCR6   0xc8
  48 #define OMCR7   0xcc
  49 #define OMCR8   0xd0
  50 #define OMCR9   0xd4
  51 #define OMCR10  0xd8
  52 #define OMCR11  0xdc
  53 #define OSNR    0x20
  54
  55 #define PXA25X_FREQ     3686400 /* 3.6864 MHz */
  56 #define PXA27X_FREQ     3250000 /* 3.25 MHz */
  57
  58 static int pxa2xx_timer4_freq[8] = {
  59     [0] = 0,
  60     [1] = 32768,
  61     [2] = 1000,
  62     [3] = 1,
  63     [4] = 1000000,
  64     /* [5] is the "Externally supplied clock".  Assign if necessary.  */
  65     [5 ... 7] = 0,
  66 };
  67
  68 #define TYPE_PXA2XX_TIMER "pxa2xx-timer"
  69 #define PXA2XX_TIMER(obj) \
  70     OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
  71
  72 typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
  73
  74 typedef struct {
  75     uint32_t value;
  76     qemu_irq irq;
  77     QEMUTimer *qtimer;
  78     int num;
  79     PXA2xxTimerInfo *info;
  80 } PXA2xxTimer0;
  81
  82 typedef struct {
  83     PXA2xxTimer0 tm;
  84     int32_t oldclock;
  85     int32_t clock;
  86     uint64_t lastload;
  87     uint32_t freq;
  88     uint32_t control;
  89 } PXA2xxTimer4;
  90
  91 struct PXA2xxTimerInfo {
  92     SysBusDevice parent_obj;
  93
  94     MemoryRegion iomem;
  95     uint32_t flags;
  96
  97     int32_t clock;
  98     int32_t oldclock;
  99     uint64_t lastload;
 100     uint32_t freq;
 101     PXA2xxTimer0 timer[4];
 102     uint32_t events;
 103     uint32_t irq_enabled;
 104     uint32_t reset3;
 105     uint32_t snapshot;
 106
 107     qemu_irq irq4;
 108     PXA2xxTimer4 tm4[8];
 109 };
 110
 111 #define PXA2XX_TIMER_HAVE_TM4   0
 112
 113 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
 114 {
 115     return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
 116 }
 117
 118 static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
 119 {
 120     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 121     int i;
 122     uint32_t now_vm;
 123     uint64_t new_qemu;
 124
 125     now_vm = s->clock +
 126             muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
 127
 128     for (i = 0; i < 4; i ++) {
 129         new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
 130                         NANOSECONDS_PER_SECOND, s->freq);
 131         timer_mod(s->timer[i].qtimer, new_qemu);
 132     }
 133 }
 134
 135 static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
 136 {
 137     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 138     uint32_t now_vm;
 139     uint64_t new_qemu;
 140     static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
 141     int counter;
 142
 143     assert(n < ARRAY_SIZE(counters));
 144     if (s->tm4[n].control & (1 << 7))
 145         counter = n;
 146     else
 147         counter = counters[n];
 148
 149     if (!s->tm4[counter].freq) {
 150         timer_del(s->tm4[n].tm.qtimer);
 151         return;
 152     }
 153
 154     now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
 155                     s->tm4[counter].lastload,
 156                     s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
 157
 158     new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
 159                     NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
 160     timer_mod(s->tm4[n].tm.qtimer, new_qemu);
 161 }
 162
 163 static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
 164                                   unsigned size)
 165 {
 166     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 167     int tm = 0;
 168
 169     switch (offset) {
 170     case OSMR3:  tm ++;
 171         /* fall through */
 172     case OSMR2:  tm ++;
 173         /* fall through */
 174     case OSMR1:  tm ++;
 175         /* fall through */
 176     case OSMR0:
 177         return s->timer[tm].value;
 178     case OSMR11: tm ++;
 179         /* fall through */
 180     case OSMR10: tm ++;
 181         /* fall through */
 182     case OSMR9:  tm ++;
 183         /* fall through */
 184     case OSMR8:  tm ++;
 185         /* fall through */
 186     case OSMR7:  tm ++;
 187         /* fall through */
 188     case OSMR6:  tm ++;
 189         /* fall through */
 190     case OSMR5:  tm ++;
 191         /* fall through */
 192     case OSMR4:
 193         if (!pxa2xx_timer_has_tm4(s))
 194             goto badreg;
 195         return s->tm4[tm].tm.value;
 196     case OSCR:
 197         return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 198                         s->lastload, s->freq, NANOSECONDS_PER_SECOND);
 199     case OSCR11: tm ++;
 200         /* fall through */
 201     case OSCR10: tm ++;
 202         /* fall through */
 203     case OSCR9:  tm ++;
 204         /* fall through */
 205     case OSCR8:  tm ++;
 206         /* fall through */
 207     case OSCR7:  tm ++;
 208         /* fall through */
 209     case OSCR6:  tm ++;
 210         /* fall through */
 211     case OSCR5:  tm ++;
 212         /* fall through */
 213     case OSCR4:
 214         if (!pxa2xx_timer_has_tm4(s))
 215             goto badreg;
 216
 217         if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
 218             if (s->tm4[tm - 1].freq)
 219                 s->snapshot = s->tm4[tm - 1].clock + muldiv64(
 220                                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 221                                 s->tm4[tm - 1].lastload,
 222                                 s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
 223             else
 224                 s->snapshot = s->tm4[tm - 1].clock;
 225         }
 226
 227         if (!s->tm4[tm].freq)
 228             return s->tm4[tm].clock;
 229         return s->tm4[tm].clock +
 230             muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 231                      s->tm4[tm].lastload, s->tm4[tm].freq,
 232                      NANOSECONDS_PER_SECOND);
 233     case OIER:
 234         return s->irq_enabled;
 235     case OSSR:  /* Status register */
 236         return s->events;
 237     case OWER:
 238         return s->reset3;
 239     case OMCR11: tm ++;
 240         /* fall through */
 241     case OMCR10: tm ++;
 242         /* fall through */
 243     case OMCR9:  tm ++;
 244         /* fall through */
 245     case OMCR8:  tm ++;
 246         /* fall through */
 247     case OMCR7:  tm ++;
 248         /* fall through */
 249     case OMCR6:  tm ++;
 250         /* fall through */
 251     case OMCR5:  tm ++;
 252         /* fall through */
 253     case OMCR4:
 254         if (!pxa2xx_timer_has_tm4(s))
 255             goto badreg;
 256         return s->tm4[tm].control;
 257     case OSNR:
 258         return s->snapshot;
 259     default:
 260         qemu_log_mask(LOG_UNIMP,
 261                       "%s: unknown register 0x%02" HWADDR_PRIx "\n",
 262                       __func__, offset);
 263         break;
 264     badreg:
 265         qemu_log_mask(LOG_GUEST_ERROR,
 266                       "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
 267                       __func__, offset);
 268     }
 269
 270     return 0;
 271 }
 272
 273 static void pxa2xx_timer_write(void *opaque, hwaddr offset,
 274                                uint64_t value, unsigned size)
 275 {
 276     int i, tm = 0;
 277     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 278
 279     switch (offset) {
 280     case OSMR3:  tm ++;
 281         /* fall through */
 282     case OSMR2:  tm ++;
 283         /* fall through */
 284     case OSMR1:  tm ++;
 285         /* fall through */
 286     case OSMR0:
 287         s->timer[tm].value = value;
 288         pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 289         break;
 290     case OSMR11: tm ++;
 291         /* fall through */
 292     case OSMR10: tm ++;
 293         /* fall through */
 294     case OSMR9:  tm ++;
 295         /* fall through */
 296     case OSMR8:  tm ++;
 297         /* fall through */
 298     case OSMR7:  tm ++;
 299         /* fall through */
 300     case OSMR6:  tm ++;
 301         /* fall through */
 302     case OSMR5:  tm ++;
 303         /* fall through */
 304     case OSMR4:
 305         if (!pxa2xx_timer_has_tm4(s))
 306             goto badreg;
 307         s->tm4[tm].tm.value = value;
 308         pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 309         break;
 310     case OSCR:
 311         s->oldclock = s->clock;
 312         s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 313         s->clock = value;
 314         pxa2xx_timer_update(s, s->lastload);
 315         break;
 316     case OSCR11: tm ++;
 317         /* fall through */
 318     case OSCR10: tm ++;
 319         /* fall through */
 320     case OSCR9:  tm ++;
 321         /* fall through */
 322     case OSCR8:  tm ++;
 323         /* fall through */
 324     case OSCR7:  tm ++;
 325         /* fall through */
 326     case OSCR6:  tm ++;
 327         /* fall through */
 328     case OSCR5:  tm ++;
 329         /* fall through */
 330     case OSCR4:
 331         if (!pxa2xx_timer_has_tm4(s))
 332             goto badreg;
 333         s->tm4[tm].oldclock = s->tm4[tm].clock;
 334         s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 335         s->tm4[tm].clock = value;
 336         pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
 337         break;
 338     case OIER:
 339         s->irq_enabled = value & 0xfff;
 340         break;
 341     case OSSR:  /* Status register */
 342         value &= s->events;
 343         s->events &= ~value;
 344         for (i = 0; i < 4; i ++, value >>= 1)
 345             if (value & 1)
 346                 qemu_irq_lower(s->timer[i].irq);
 347         if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
 348             qemu_irq_lower(s->irq4);
 349         break;
 350     case OWER:  /* XXX: Reset on OSMR3 match? */
 351         s->reset3 = value;
 352         break;
 353     case OMCR7:  tm ++;
 354         /* fall through */
 355     case OMCR6:  tm ++;
 356         /* fall through */
 357     case OMCR5:  tm ++;
 358         /* fall through */
 359     case OMCR4:
 360         if (!pxa2xx_timer_has_tm4(s))
 361             goto badreg;
 362         s->tm4[tm].control = value & 0x0ff;
 363         /* XXX Stop if running (shouldn't happen) */
 364         if ((value & (1 << 7)) || tm == 0)
 365             s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
 366         else {
 367             s->tm4[tm].freq = 0;
 368             pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 369         }
 370         break;
 371     case OMCR11: tm ++;
 372         /* fall through */
 373     case OMCR10: tm ++;
 374         /* fall through */
 375     case OMCR9:  tm ++;
 376         /* fall through */
 377     case OMCR8:  tm += 4;
 378         if (!pxa2xx_timer_has_tm4(s))
 379             goto badreg;
 380         s->tm4[tm].control = value & 0x3ff;
 381         /* XXX Stop if running (shouldn't happen) */
 382         if ((value & (1 << 7)) || !(tm & 1))
 383             s->tm4[tm].freq =
 384                     pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
 385         else {
 386             s->tm4[tm].freq = 0;
 387             pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
 388         }
 389         break;
 390     default:
 391         qemu_log_mask(LOG_UNIMP,
 392                       "%s: unknown register 0x%02" HWADDR_PRIx " "
 393                       "(value 0x%08" PRIx64 ")\n",  __func__, offset, value);
 394         break;
 395     badreg:
 396         qemu_log_mask(LOG_GUEST_ERROR,
 397                       "%s: incorrect register 0x%02" HWADDR_PRIx " "
 398                       "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
 399     }
 400 }
 401
 402 static const MemoryRegionOps pxa2xx_timer_ops = {
 403     .read = pxa2xx_timer_read,
 404     .write = pxa2xx_timer_write,
 405     .endianness = DEVICE_NATIVE_ENDIAN,
 406 };
 407
 408 static void pxa2xx_timer_tick(void *opaque)
 409 {
 410     PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
 411     PXA2xxTimerInfo *i = t->info;
 412
 413     if (i->irq_enabled & (1 << t->num)) {
 414         i->events |= 1 << t->num;
 415         qemu_irq_raise(t->irq);
 416     }
 417
 418     if (t->num == 3)
 419         if (i->reset3 & 1) {
 420             i->reset3 = 0;
 421             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 422         }
 423 }
 424
 425 static void pxa2xx_timer_tick4(void *opaque)
 426 {
 427     PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
 428     PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
 429
 430     pxa2xx_timer_tick(&t->tm);
 431     if (t->control & (1 << 3))
 432         t->clock = 0;
 433     if (t->control & (1 << 6))
 434         pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
 435     if (i->events & 0xff0)
 436         qemu_irq_raise(i->irq4);
 437 }
 438
 439 static int pxa25x_timer_post_load(void *opaque, int version_id)
 440 {
 441     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 442     int64_t now;
 443     int i;
 444
 445     now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 446     pxa2xx_timer_update(s, now);
 447
 448     if (pxa2xx_timer_has_tm4(s))
 449         for (i = 0; i < 8; i ++)
 450             pxa2xx_timer_update4(s, now, i);
 451
 452     return 0;
 453 }
 454
 455 static void pxa2xx_timer_init(Object *obj)
 456 {
 457     PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
 458     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 459
 460     s->irq_enabled = 0;
 461     s->oldclock = 0;
 462     s->clock = 0;
 463     s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 464     s->reset3 = 0;
 465
 466     memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
 467                           "pxa2xx-timer", 0x00001000);
 468     sysbus_init_mmio(dev, &s->iomem);
 469 }
 470
 471 static void pxa2xx_timer_realize(DeviceState *dev, Error **errp)
 472 {
 473     PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
 474     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 475     int i;
 476
 477     for (i = 0; i < 4; i ++) {
 478         s->timer[i].value = 0;
 479         sysbus_init_irq(sbd, &s->timer[i].irq);
 480         s->timer[i].info = s;
 481         s->timer[i].num = i;
 482         s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 483                                           pxa2xx_timer_tick, &s->timer[i]);
 484     }
 485
 486     if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
 487         sysbus_init_irq(sbd, &s->irq4);
 488
 489         for (i = 0; i < 8; i ++) {
 490             s->tm4[i].tm.value = 0;
 491             s->tm4[i].tm.info = s;
 492             s->tm4[i].tm.num = i + 4;
 493             s->tm4[i].freq = 0;
 494             s->tm4[i].control = 0x0;
 495             s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 496                                                pxa2xx_timer_tick4, &s->tm4[i]);
 497         }
 498     }
 499 }
 500
 501 static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
 502     .name = "pxa2xx_timer0",
 503     .version_id = 2,
 504     .minimum_version_id = 2,
 505     .fields = (VMStateField[]) {
 506         VMSTATE_UINT32(value, PXA2xxTimer0),
 507         VMSTATE_END_OF_LIST(),
 508     },
 509 };
 510
 511 static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
 512     .name = "pxa2xx_timer4",
 513     .version_id = 1,
 514     .minimum_version_id = 1,
 515     .fields = (VMStateField[]) {
 516         VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
 517                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 518         VMSTATE_INT32(oldclock, PXA2xxTimer4),
 519         VMSTATE_INT32(clock, PXA2xxTimer4),
 520         VMSTATE_UINT64(lastload, PXA2xxTimer4),
 521         VMSTATE_UINT32(freq, PXA2xxTimer4),
 522         VMSTATE_UINT32(control, PXA2xxTimer4),
 523         VMSTATE_END_OF_LIST(),
 524     },
 525 };
 526
 527 static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
 528 {
 529     return pxa2xx_timer_has_tm4(opaque);
 530 }
 531
 532 static const VMStateDescription vmstate_pxa2xx_timer_regs = {
 533     .name = "pxa2xx_timer",
 534     .version_id = 1,
 535     .minimum_version_id = 1,
 536     .post_load = pxa25x_timer_post_load,
 537     .fields = (VMStateField[]) {
 538         VMSTATE_INT32(clock, PXA2xxTimerInfo),
 539         VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
 540         VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
 541         VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
 542                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 543         VMSTATE_UINT32(events, PXA2xxTimerInfo),
 544         VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
 545         VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
 546         VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
 547         VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
 548                         pxa2xx_timer_has_tm4_test, 0,
 549                         vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
 550         VMSTATE_END_OF_LIST(),
 551     }
 552 };
 553
 554 static Property pxa25x_timer_dev_properties[] = {
 555     DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
 556     DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
 557                     PXA2XX_TIMER_HAVE_TM4, false),
 558     DEFINE_PROP_END_OF_LIST(),
 559 };
 560
 561 static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
 562 {
 563     DeviceClass *dc = DEVICE_CLASS(klass);
 564
 565     dc->desc = "PXA25x timer";
 566     device_class_set_props(dc, pxa25x_timer_dev_properties);
 567 }
 568
 569 static const TypeInfo pxa25x_timer_dev_info = {
 570     .name          = "pxa25x-timer",
 571     .parent        = TYPE_PXA2XX_TIMER,
 572     .instance_size = sizeof(PXA2xxTimerInfo),
 573     .class_init    = pxa25x_timer_dev_class_init,
 574 };
 575
 576 static Property pxa27x_timer_dev_properties[] = {
 577     DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
 578     DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
 579                     PXA2XX_TIMER_HAVE_TM4, true),
 580     DEFINE_PROP_END_OF_LIST(),
 581 };
 582
 583 static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
 584 {
 585     DeviceClass *dc = DEVICE_CLASS(klass);
 586
 587     dc->desc = "PXA27x timer";
 588     device_class_set_props(dc, pxa27x_timer_dev_properties);
 589 }
 590
 591 static const TypeInfo pxa27x_timer_dev_info = {
 592     .name          = "pxa27x-timer",
 593     .parent        = TYPE_PXA2XX_TIMER,
 594     .instance_size = sizeof(PXA2xxTimerInfo),
 595     .class_init    = pxa27x_timer_dev_class_init,
 596 };
 597
 598 static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
 599 {
 600     DeviceClass *dc = DEVICE_CLASS(oc);
 601
 602     dc->realize  = pxa2xx_timer_realize;
 603     dc->vmsd = &vmstate_pxa2xx_timer_regs;
 604 }
 605
 606 static const TypeInfo pxa2xx_timer_type_info = {
 607     .name          = TYPE_PXA2XX_TIMER,
 608     .parent        = TYPE_SYS_BUS_DEVICE,
 609     .instance_size = sizeof(PXA2xxTimerInfo),
 610     .instance_init = pxa2xx_timer_init,
 611     .abstract      = true,
 612     .class_init    = pxa2xx_timer_class_init,
 613 };
 614
 615 static void pxa2xx_timer_register_types(void)
 616 {
 617     type_register_static(&pxa2xx_timer_type_info);
 618     type_register_static(&pxa25x_timer_dev_info);
 619     type_register_static(&pxa27x_timer_dev_info);
 620 }
 621
 622 type_init(pxa2xx_timer_register_types)