hw/timer/sh_timer.c

   1 /*
   2  * SuperH Timer modules.
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Based on arm_timer.c by Paul Brook
   6  * Copyright (c) 2005-2006 CodeSourcery.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "exec/memory.h"
  13 #include "hw/hw.h"
  14 #include "hw/irq.h"
  15 #include "hw/sh4/sh.h"
  16 #include "hw/timer/tmu012.h"
  17 #include "hw/ptimer.h"
  18
  19 //#define DEBUG_TIMER
  20
  21 #define TIMER_TCR_TPSC          (7 << 0)
  22 #define TIMER_TCR_CKEG          (3 << 3)
  23 #define TIMER_TCR_UNIE          (1 << 5)
  24 #define TIMER_TCR_ICPE          (3 << 6)
  25 #define TIMER_TCR_UNF           (1 << 8)
  26 #define TIMER_TCR_ICPF          (1 << 9)
  27 #define TIMER_TCR_RESERVED      (0x3f << 10)
  28
  29 #define TIMER_FEAT_CAPT   (1 << 0)
  30 #define TIMER_FEAT_EXTCLK (1 << 1)
  31
  32 #define OFFSET_TCOR   0
  33 #define OFFSET_TCNT   1
  34 #define OFFSET_TCR    2
  35 #define OFFSET_TCPR   3
  36
  37 typedef struct {
  38     ptimer_state *timer;
  39     uint32_t tcnt;
  40     uint32_t tcor;
  41     uint32_t tcr;
  42     uint32_t tcpr;
  43     int freq;
  44     int int_level;
  45     int old_level;
  46     int feat;
  47     int enabled;
  48     qemu_irq irq;
  49 } sh_timer_state;
  50
  51 /* Check all active timers, and schedule the next timer interrupt. */
  52
  53 static void sh_timer_update(sh_timer_state *s)
  54 {
  55     int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
  56
  57     if (new_level != s->old_level)
  58       qemu_set_irq (s->irq, new_level);
  59
  60     s->old_level = s->int_level;
  61     s->int_level = new_level;
  62 }
  63
  64 static uint32_t sh_timer_read(void *opaque, hwaddr offset)
  65 {
  66     sh_timer_state *s = (sh_timer_state *)opaque;
  67
  68     switch (offset >> 2) {
  69     case OFFSET_TCOR:
  70         return s->tcor;
  71     case OFFSET_TCNT:
  72         return ptimer_get_count(s->timer);
  73     case OFFSET_TCR:
  74         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
  75     case OFFSET_TCPR:
  76         if (s->feat & TIMER_FEAT_CAPT)
  77             return s->tcpr;
  78         /* fall through */
  79     default:
  80         hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
  81         return 0;
  82     }
  83 }
  84
  85 static void sh_timer_write(void *opaque, hwaddr offset,
  86                             uint32_t value)
  87 {
  88     sh_timer_state *s = (sh_timer_state *)opaque;
  89     int freq;
  90
  91     switch (offset >> 2) {
  92     case OFFSET_TCOR:
  93         s->tcor = value;
  94         ptimer_transaction_begin(s->timer);
  95         ptimer_set_limit(s->timer, s->tcor, 0);
  96         ptimer_transaction_commit(s->timer);
  97         break;
  98     case OFFSET_TCNT:
  99         s->tcnt = value;
 100         ptimer_transaction_begin(s->timer);
 101         ptimer_set_count(s->timer, s->tcnt);
 102         ptimer_transaction_commit(s->timer);
 103         break;
 104     case OFFSET_TCR:
 105         ptimer_transaction_begin(s->timer);
 106         if (s->enabled) {
 107             /* Pause the timer if it is running.  This may cause some
 108                inaccuracy dure to rounding, but avoids a whole lot of other
 109                messyness.  */
 110             ptimer_stop(s->timer);
 111         }
 112         freq = s->freq;
 113         /* ??? Need to recalculate expiry time after changing divisor.  */
 114         switch (value & TIMER_TCR_TPSC) {
 115         case 0: freq >>= 2; break;
 116         case 1: freq >>= 4; break;
 117         case 2: freq >>= 6; break;
 118         case 3: freq >>= 8; break;
 119         case 4: freq >>= 10; break;
 120         case 6:
 121         case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
 122         default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
 123         }
 124         switch ((value & TIMER_TCR_CKEG) >> 3) {
 125         case 0: break;
 126         case 1:
 127         case 2:
 128         case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
 129         default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
 130         }
 131         switch ((value & TIMER_TCR_ICPE) >> 6) {
 132         case 0: break;
 133         case 2:
 134         case 3: if (s->feat & TIMER_FEAT_CAPT) break;
 135         default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
 136         }
 137         if ((value & TIMER_TCR_UNF) == 0)
 138             s->int_level = 0;
 139
 140         value &= ~TIMER_TCR_UNF;
 141
 142         if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
 143             hw_error("sh_timer_write: Reserved ICPF value\n");
 144
 145         value &= ~TIMER_TCR_ICPF; /* capture not supported */
 146
 147         if (value & TIMER_TCR_RESERVED)
 148             hw_error("sh_timer_write: Reserved TCR bits set\n");
 149         s->tcr = value;
 150         ptimer_set_limit(s->timer, s->tcor, 0);
 151         ptimer_set_freq(s->timer, freq);
 152         if (s->enabled) {
 153             /* Restart the timer if still enabled.  */
 154             ptimer_run(s->timer, 0);
 155         }
 156         ptimer_transaction_commit(s->timer);
 157         break;
 158     case OFFSET_TCPR:
 159         if (s->feat & TIMER_FEAT_CAPT) {
 160             s->tcpr = value;
 161             break;
 162         }
 163     default:
 164         hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
 165     }
 166     sh_timer_update(s);
 167 }
 168
 169 static void sh_timer_start_stop(void *opaque, int enable)
 170 {
 171     sh_timer_state *s = (sh_timer_state *)opaque;
 172
 173 #ifdef DEBUG_TIMER
 174     printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
 175 #endif
 176
 177     ptimer_transaction_begin(s->timer);
 178     if (s->enabled && !enable) {
 179         ptimer_stop(s->timer);
 180     }
 181     if (!s->enabled && enable) {
 182         ptimer_run(s->timer, 0);
 183     }
 184     ptimer_transaction_commit(s->timer);
 185     s->enabled = !!enable;
 186
 187 #ifdef DEBUG_TIMER
 188     printf("sh_timer_start_stop done %d\n", s->enabled);
 189 #endif
 190 }
 191
 192 static void sh_timer_tick(void *opaque)
 193 {
 194     sh_timer_state *s = (sh_timer_state *)opaque;
 195     s->int_level = s->enabled;
 196     sh_timer_update(s);
 197 }
 198
 199 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
 200 {
 201     sh_timer_state *s;
 202
 203     s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
 204     s->freq = freq;
 205     s->feat = feat;
 206     s->tcor = 0xffffffff;
 207     s->tcnt = 0xffffffff;
 208     s->tcpr = 0xdeadbeef;
 209     s->tcr = 0;
 210     s->enabled = 0;
 211     s->irq = irq;
 212
 213     s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
 214
 215     sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
 216     sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
 217     sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
 218     sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
 219     /* ??? Save/restore.  */
 220     return s;
 221 }
 222
 223 typedef struct {
 224     MemoryRegion iomem;
 225     MemoryRegion iomem_p4;
 226     MemoryRegion iomem_a7;
 227     void *timer[3];
 228     int level[3];
 229     uint32_t tocr;
 230     uint32_t tstr;
 231     int feat;
 232 } tmu012_state;
 233
 234 static uint64_t tmu012_read(void *opaque, hwaddr offset,
 235                             unsigned size)
 236 {
 237     tmu012_state *s = (tmu012_state *)opaque;
 238
 239 #ifdef DEBUG_TIMER
 240     printf("tmu012_read 0x%lx\n", (unsigned long) offset);
 241 #endif
 242
 243     if (offset >= 0x20) {
 244         if (!(s->feat & TMU012_FEAT_3CHAN))
 245             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 246         return sh_timer_read(s->timer[2], offset - 0x20);
 247     }
 248
 249     if (offset >= 0x14)
 250         return sh_timer_read(s->timer[1], offset - 0x14);
 251
 252     if (offset >= 0x08)
 253         return sh_timer_read(s->timer[0], offset - 0x08);
 254
 255     if (offset == 4)
 256         return s->tstr;
 257
 258     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
 259         return s->tocr;
 260
 261     hw_error("tmu012_write: Bad offset %x\n", (int)offset);
 262     return 0;
 263 }
 264
 265 static void tmu012_write(void *opaque, hwaddr offset,
 266                         uint64_t value, unsigned size)
 267 {
 268     tmu012_state *s = (tmu012_state *)opaque;
 269
 270 #ifdef DEBUG_TIMER
 271     printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
 272 #endif
 273
 274     if (offset >= 0x20) {
 275         if (!(s->feat & TMU012_FEAT_3CHAN))
 276             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 277         sh_timer_write(s->timer[2], offset - 0x20, value);
 278         return;
 279     }
 280
 281     if (offset >= 0x14) {
 282         sh_timer_write(s->timer[1], offset - 0x14, value);
 283         return;
 284     }
 285
 286     if (offset >= 0x08) {
 287         sh_timer_write(s->timer[0], offset - 0x08, value);
 288         return;
 289     }
 290
 291     if (offset == 4) {
 292         sh_timer_start_stop(s->timer[0], value & (1 << 0));
 293         sh_timer_start_stop(s->timer[1], value & (1 << 1));
 294         if (s->feat & TMU012_FEAT_3CHAN)
 295             sh_timer_start_stop(s->timer[2], value & (1 << 2));
 296         else
 297             if (value & (1 << 2))
 298                 hw_error("tmu012_write: Bad channel\n");
 299
 300         s->tstr = value;
 301         return;
 302     }
 303
 304     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
 305         s->tocr = value & (1 << 0);
 306     }
 307 }
 308
 309 static const MemoryRegionOps tmu012_ops = {
 310     .read = tmu012_read,
 311     .write = tmu012_write,
 312     .endianness = DEVICE_NATIVE_ENDIAN,
 313 };
 314
 315 void tmu012_init(MemoryRegion *sysmem, hwaddr base,
 316                  int feat, uint32_t freq,
 317                  qemu_irq ch0_irq, qemu_irq ch1_irq,
 318                  qemu_irq ch2_irq0, qemu_irq ch2_irq1)
 319 {
 320     tmu012_state *s;
 321     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
 322
 323     s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
 324     s->feat = feat;
 325     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
 326     s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
 327     if (feat & TMU012_FEAT_3CHAN)
 328         s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
 329                                     ch2_irq0); /* ch2_irq1 not supported */
 330
 331     memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
 332                           "timer", 0x100000000ULL);
 333
 334     memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
 335                              &s->iomem, 0, 0x1000);
 336     memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
 337
 338     memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
 339                              &s->iomem, 0, 0x1000);
 340     memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
 341     /* ??? Save/restore.  */
 342 }